KR20100076766A - Delay locked loop circuit - Google Patents

Delay locked loop circuit Download PDF

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Publication number
KR20100076766A
KR20100076766A KR1020080134928A KR20080134928A KR20100076766A KR 20100076766 A KR20100076766 A KR 20100076766A KR 1020080134928 A KR1020080134928 A KR 1020080134928A KR 20080134928 A KR20080134928 A KR 20080134928A KR 20100076766 A KR20100076766 A KR 20100076766A
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South Korea
Prior art keywords
delay
clock
signal
lock
delay lock
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KR1020080134928A
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Korean (ko)
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도창호
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주식회사 하이닉스반도체
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Priority to KR1020080134928A priority Critical patent/KR20100076766A/en
Publication of KR20100076766A publication Critical patent/KR20100076766A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop circuit of a semiconductor device. A timing pulse generator for generating a timing pulse, a phase comparator for receiving the source clock and a feedback clock at a time defined by the timing pulse, and comparing the phases, and a time defined by the timing pulse The delay amount is adjusted in response to the output signal of the phase comparator, and the phase delay unit receives the source clock to delay the phase and outputs the delay locked clock, and the delay delay of the actual output path. A delay model unit for outputting the feedback clock while reflecting time; and A delay locked loop circuit including an operation control unit for controlling on / off operation of the timing pulse generator, the phase comparator, and the delay model unit in response to a delay lock signal and a refresh period signal is provided.

Description

DELAY LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a delay locked loop circuit of a semiconductor device.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller (CTRL).

This is because, in order to stably transfer data between the memory and the memory controller, the time synchronization between the external clock and the data output from the memory is very important.

At this time, the data output from the memory is output in synchronization with the internal clock. When the internal clock is initially applied to the memory, the internal clock is applied in synchronization with the external clock, but is delayed through each component in the memory and output to the outside of the memory. If it does, it is output out of sync with external clock.

Therefore, for stable transmission of data output from the memory, the delayed internal clock is accurately positioned at the edge or center of the external clock applied by the memory controller while passing through each component in the memory transmitting the data. To do this, the time the data is on the bus must be compensated back to the internal clock so that the internal and external clocks are synchronized.

Clock synchronizing circuits that perform this role include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.

Of these, when the frequency of the external clock and the internal clock are different, the frequency-locking function should be used. Therefore, a phase locked loop (PLL) is used. However, when the frequency of the external clock is the same as the frequency of the internal clock, a delayed fixed loop (DLL) circuit that can be implemented in a relatively small area is mainly used compared to the phase locked loop (PLL).

That is, in the case of the semiconductor memory device, since the frequency used is the same, a delay locked loop (DLL) circuit is mainly used as the clock synchronization circuit.

In particular, the semiconductor memory device includes a register for storing a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register, and when the power is applied again, the internal clock is fixed by loading the fixed delay value stored in the register. In this case, the clock synchronization operation can be performed when the phase difference between the internal clock and the external clock is relatively small during the initial operation of the semiconductor memory device, and the delay value of the register according to the phase difference between the internal clock and the external clock even after the initial operation The most widely used register controlled delayed loop circuit is to adjust the fluctuation width to reduce the time it takes for the internal and external clocks to synchronize.

1 is a block diagram showing a general register controlled delay locked loop (DLL) circuit.

Referring to FIG. 1, a buffering unit 100 for buffering an externally applied clock EXTCLK and generating a source clock CLK_IN, and a predetermined time at a predetermined time in response to the source clock CLK_IN. The timing pulse generator 120 for generating the timing pulse TM_PUL that is activated by the number of times and the source clock CLK_IN and the feedback clock F_CLK are inputted at a time defined by the timing pulse TM_PUL. The delay amount is adjusted in response to the phase comparator 140 for comparison and the output signals COMPP_SIG and LOCK_STATE of the phase comparator 140 at a point defined by the timing pulse TM_PUL, and the source clock CLK_IN. Phase delay unit 160 for delaying the phase and outputting it as delay locked clock DLL_CLK and delay locked clock DLL_CLK, and reflecting the delay time of the actual output path to output as feedback clock F_CLK. doing The delay model unit 180 is provided.

Here, the phase delay unit 160 receives the source clock CLK_IN and delays by a delay amount corresponding to the value of the delay control code DLY <0: N> and outputs it as a delay locked clock DLL_CLK. The value of the delay control code DLY <0: N> is changed in response to the output signals COMP_SIG and LOCK_STATE of the phase comparison unit 140 at the time defined by the line 162 and the timing pulse TM_PUL. A delay control unit 164 is provided.

Referring to the operation of the register-controlled delayed fixed loop (DLL) circuit according to the prior art based on the above configuration as follows.

First, a state immediately before the delay lock loop (DLL) circuit performs the delay lock operation is performed. In the state based on the source clock CLK_IN, the delay lock clock DLL_CLK sets the source clock CLK_IN to the phase delay unit ( The delay time is delayed by a time corresponding to the initial delay amount of 160, and the feedback clock F_CLK is delayed by the delay lock clock DLL_CLK by the delay time of the actual output path defined in the delay model unit 180.

In this state, the delay lock operation of the delay lock loop (DLL) circuit for synchronizing the phases of the source clock CLK_IN and the feedback clock F_CLK is performed. It is divided into actions.

First, the initialization delay lock operation is an operation performed when the delay lock loop (DLL) circuit performs the delay lock operation for the first time. Therefore, the reference edge of the source clock CLK_IN-which generally indicates a rising edge and can be a falling edge-is unconditionally located ahead of the reference edge of the feedback clock F_CLK. The phase of the source clock CLK_IN and the feedback clock F_CLK may be synchronized by increasing the delay amount of the phase delay unit 160, which increases in a relatively large unit.

After the initialization, the delay lock operation is performed even if the phases of the source clock CLK_IN and the feedback clock F_CLK are synchronized through the initialization delay lock operation. The source clock CLK_IN and the feedback clock F_CLK may be out of phase again due to a change in the surrounding environment, such as a change in the potential level of the power supply voltage VDD, and the source clock CLK_IN and the feedback are corrected again. This operation is performed to synchronize the phase of the clock F_CLK. Therefore, it is impossible to predict whether the reference edge of the feedback clock F_CLK is located in front of or behind the reference edge of the source clock CLK_IN, and the operation of increasing or decreasing the delay amount of the phase delay unit 160 alternately. Iterating-increasing or decreasing in relatively small increments-synchronizes the phase of the source clock CLK_IN and the feedback clock F_CLK.

Specifically, the components in the delay locked loop (DLL) circuit operate as follows to synchronize the phases of the source clock CLK_IN and the feedback clock F_CLK, whether the initialization delay lock operation or the delay lock operation after initialization is performed as follows.

First, the phase comparison unit 140 operates first in the order defined by the timing pulse TM_PUL to determine whether the phase of the reference edge of the source clock CLK_IN and the reference edge of the feedback clock F_CLK coincide with each other. .

In addition, the phase delay unit 160 is terminated at the same time as the operation of the phase comparator 140 is terminated in the order defined by the timing pulse TM_PUL, and the delay controller 160 is provided in the phase delay unit 160. In 164, the delay amount of the variable delay line 162 is changed by changing the value of the delay control code DLY <0: N> in response to the output signals COMP_SIG and LOCK_STATE of the phase comparison unit 140.

At this time, the comparison signal COMPP_SIG of the signals COMPP_SIG and LOCK_STATE output from the phase comparator 140 may have a phase delay when the reference edge of the source clock CLK_IN and the reference edge of the feedback clock F_CLK do not coincide with each other. A signal used to change the value of the delay control code DLY <0: N> of the delay control unit 164 provided in the 160, and the delay lock signal LOCK_STATE is an initialization delay lock operation and a delay lock after initialization. This signal is used to divide the operation.

That is, if the delay amount of the phase delay unit 160 changes in response to the comparison signal COMPP_SIG while the delay lock signal LOCK_STATE is deactivated, the initialization delay lock operation is performed and the delay lock signal LOCK_STATE is activated. If the delay amount of the phase delay unit 160 changes in response to the signal COMP_SIG, it is a delay lock operation after initialization.

On the other hand, the initialization of the delay locked loop (DLL) circuit is generally performed for the first time when the power is supplied to the semiconductor device, and for resetting the delay locked loop (DLL) circuit. In this case, the self-refreshing operation resets the delay lock loop (DLL) circuit.

On the other hand, after the initialization of the delay locked loop (DLL) circuit, the delay lock operation may be performed by changing the temperature of the semiconductor device or the potential level of the power supply voltage VDD supplied to the semiconductor device according to the operation of the semiconductor device. Since the operation is performed in case the phase of the source clock CLK_IN and the feedback clock F_CLK are changed again due to the change, the operation is always performed in the remaining sections other than the section in which the initialization delay lock operation is performed.

That is, in the case of a semiconductor device including a delay locked loop (DLL) circuit according to the related art, an operation mode for resetting a delay locked loop (DLL) circuit including a self-refresh operation may be performed in a state in which power is supplied. Other than-indicates that either the delay delay operation or the delay lock operation after initialization is performed.

By the way, while the delay lock operation is performed, current is continuously consumed inside the delay lock loop (DLL) circuit, and the long duration of the delay lock operation means that a large amount of current is consumed. .

In particular, in the case of a semiconductor device used in a mobile device, since the current consumption is greater than the performance of the semiconductor device, a delay locked loop (DLL) circuit that maintains a long duration of delay delay operation as in the prior art is used in a mobile device. When included in the semiconductor device to be used, there is a problem that the current consumption of the delayed fixed loop (DLL) circuit is too large compared to the total current consumption of the semiconductor device.

Therefore, there is a problem in that it is difficult to apply a delay locked loop (DLL) circuit as in the prior art to a semiconductor device used in a mobile device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems in the prior art, and an object thereof is to provide a delay locked loop (DLL) circuit that consumes a relatively small amount of current by performing a delay locked operation only in a predetermined section. .

According to an aspect of the present invention for achieving the above object to be solved, a delay for outputting a delay locked loop clock by comparing the phase of the source clock and the feedback clock to give a delay value that is fixed to the source clock Fixed loop; And a control unit for controlling a delay correction operation of the delay lock loop in response to the refresh period signal after delay lock.

According to another aspect of the present invention for achieving the above object to be solved, the step of comparing the phase of the source clock and the feedback clock to give a delay value that is fixed to the source clock outputting a delay locked loop clock; And controlling the clock path of the delay locked loop to disable the delay correction operation of the delay locked loop during the non-refresh interval after the delay lock.

According to another aspect of the present invention for achieving the above object, a buffering unit for generating a source clock by buffering the clock applied from the outside; A timing pulse generator for generating a timing pulse that is activated at a predetermined number of times at a predetermined time point in response to the source clock at a predetermined time; A phase comparator configured to receive the source clock and the feedback clock at a time defined by the timing pulse and compare phases thereof; A phase delay unit configured to adjust a delay amount corresponding to an output signal of the phase comparison unit at a time point defined by the timing pulse, receive the source clock, delay the phase, and output the delayed clock as a delay locked clock; A delay model unit for receiving the delay lock clock and outputting the delay clock of the actual output path as the feedback clock; And an operation control unit for controlling on / off operation of the timing pulse generator, the phase comparison unit, and the delay model unit in response to the delay lock signal and the refresh period signal.

The present invention described above has the effect of greatly reducing the current consumed in the delay locked loop DLL circuit by controlling the delay locked loop DLL to perform the delay lock operation only in a specific operation mode after the initialization delay lock operation.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is to make the disclosure of the present invention complete and to those of ordinary skill in the art It is provided to fully inform the category.

2 is a block diagram illustrating a register controlled delay locked loop (DLL) circuit according to an embodiment of the present invention.

Referring to FIG. 2, a register-controlled delay locked loop (DLL) circuit according to an embodiment of the present invention compares a phase of a source clock CLK_IN and a feedback clock F_CLK to determine a delay value at which a delay is fixed. Components 200, 220, 240, and 260 for outputting the delay locked loop clock DLL_CLK by applying to CLK_IN, and after delay lock-after delay lock signal LOCK_STATE is activated-refresh interval signal REF_FLAG Components for controlling delay correction operations of the components 200, 220, 240, and 260 for finding a delay value between the source clock CLK_IN and the feedback clock F_CLK. 210, 230, 270, 290.

More specifically, the components of the register controlled delay locked loop (DLL) circuit according to an embodiment of the present invention, the buffering unit 200 for generating a source clock (CLK_IN) by buffering the clock (EXTCLK) applied from the outside ), A timing pulse generator 220 for generating a timing pulse TM_PUL that is activated at a predetermined number of times at a predetermined time in response to the source clock CLK_IN, and a timing pulse TM_PUL. The phase comparison unit 240 for receiving the source clock CLK_IN and the feedback clock F_CLK at a point in time and comparing the phases, and the output of the phase comparison unit 240 at a point defined by the timing pulse TM_PUL. The delay amount is adjusted in response to the signals COMP_SIG and LOCK_STATE, and the phase delay unit 260 which receives the source clock CLK_IN and delays its phase and outputs it as the delay locked clock DLL_CLK, and a delay lock clock. Delay fixed among the delay model unit 280 for outputting the DLL_CLK and reflecting the delay time of the actual output path as the feedback clock F_CLK, and the signals COMPP_SIG and LOCK_STATE output from the phase comparator 240. Operation controllers 210 and 230 for controlling the operation of the timing pulse generator 220, the phase comparator 240, and the delay model unit 280 in response to the signal LOCK_STATE and the refresh period signal REF_FLAG. 270). The apparatus further includes a refresh section signal generator 290 for generating a refresh section signal REF_FLAG that maintains an activation state for a predetermined time in response to the refresh command REF_CMD.

Here, the operation controllers 210, 230, and 270 may generate a source clock CLK_IN in response to the delay lock signal LOCK_STATE and the refresh period signal REF_FLAG between the buffering unit 200 and the timing pulse generator 220. The source clock in response to the delay lock signal LOCK_STATE and the refresh period signal REF_FLAG between the first operation controller 210 and the buffering unit 200 and the phase comparator 240 for controlling the transmission of the signal. The second operation control unit 230 for controlling the on / off of the transmission of the CLK_IN, and the delay lock signal LOCK_STATE and the refresh period signal REF_FLAG between the phase delay unit 260 and the delay model unit 280. In response to the delay lock clock (DLL_CLK) is provided with a third operation control unit 270 for controlling on / off.

FIG. 3A is a circuit diagram illustrating in detail an operation control unit among components of a register controlled delay locked loop (DLL) circuit according to an exemplary embodiment of the present invention illustrated in FIG. 2.

FIG. 3B is a timing diagram illustrating an operation of an operation control unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG. 2.

Referring to FIG. 3A, the first to third operation control units 210, 230, and 270 of the components of the register controlled delay locked loop (DLL) circuit according to an embodiment of the present invention input a delay locked signal LOCK_STATE. The first inverter INV1 for receiving the inverted phase and outputting the output signal of the first inverter INV1 and the NOA gate and the second gate NOR for performing the logical sum operation for receiving the refresh period signal REF_FLAG. Inputting the output signal of the inverter INV2 and the second inverter INV2 and the source clock or the delay locked clock CLK_IN or DLL_CLK and performing an AND operation to output the output signal as the source clock or the delay locked clock CLK_IN or DLL_CLK. And a NAND gate and a third inverter INV3.

Referring to FIG. 3B, the first and second operation controllers 210 and 230 may configure the refresh period signal REF_FLAG as logic 'high' while the delay lock signal LOCK_STATE is activated as logic 'high'. (High) When enabled, outputs the input source clock (CLK_IN) as it is.

However, the first and second operation controllers 210 and 230 may set the refresh period signal REF_FLAG to logic 'low' while the delay lock signal LOCK_STATE is activated as logic 'high'. When deactivated, the input source clock CLK_IN is ignored, and a signal fixed at a specific logic level, which is fixed at a logic 'high' in the drawing, is output.

The first and second operation controllers 210 and 230 activate the refresh period signal REF_FLAG as logic 'high' when the delay lock signal LOCK_STATE is logic 'low'. The input source clock (CLK_IN) is output as is, regardless of whether the logic is 'low' or disabled.

The third operation controller 270 receives an input when the refresh period signal REF_FLAG is activated with logic 'high' while the delay lock signal LOCK_STATE is activated with logic 'high'. Print the delay lock clock (DLL_CLK) as it is.

However, when the refresh period signal REF_FLAG is deactivated to logic 'low' while the delay lock signal LOCK_STATE is activated to logic 'high', the third operation controller 270 is inputted. It ignores the delayed high / low clock (DLL_CLK) and outputs a signal fixed to a specific logic level-a signal fixed to logic 'high' in the figure.

The third operation controller 270 may determine whether the refresh period signal REF_FLAG is activated as logic 'high' when the delay lock signal LOCK_STATE is logic 'low'. Regardless of whether it is deactivated as (Low), the delay lock clock received is output as it is.

FIG. 4A is a circuit diagram illustrating in detail a refresh section signal generation unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG. 2.

FIG. 4B is a timing diagram illustrating an operation of a refresh period signal generation unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG. 2.

Referring to FIG. 4A, the first inverter INV1 for receiving the refresh command REF_CMD and inverting the phase thereof and receiving the refresh command REF_CMD is delayed for a predetermined time and then inverted and outputted. A delay element DELAY and a second inverter INV2, a refresh period signal REF_FLAG, an output signal of the second inverter INV2, and a reset signal RSTB to receive a negative logic operation The second NAND gate and the second signal for receiving the output signal of the first inverter (INV1) and the output signal of the first NAND gate (NAND1) to perform a negative logic operation to output as a refresh period signal (REF_FLAG) And a NAND gate NAND2.

Referring to FIG. 4B, in response to the refresh command REF_CMD being activated with logic 'High', the refresh period signal REF_FLAG is activated with logic 'High', but the refresh command REF_CMD is logic. The refresh period signal REF_FLAG is not deactivated as logic 'low' even when deactivated to 'low' and remains logic 'high', and the logic 'low' after a predetermined time tD has passed. Deactivated with '(Low)'.

That is, the refresh period signal REF_FLAG is activated at the same time as the refresh command REF_CMD, but becomes a signal for maintaining the activation period for a predetermined time tD, and the predetermined time tD can be changed by the designer. It's time.

The operation of the register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention will be described as follows.

First, a delay lock operation of a register controlled delay lock loop (DLL) circuit according to an embodiment of the present invention is divided into an initialization delay lock operation and a delay lock operation similarly to a register controlled delay lock loop (DLL) circuit according to the prior art.

In the initialization delay lock operation, since the delay lock signal LOCK_STATE output from the phase comparator 240 is in a state of being deactivated by logic 'low', regardless of the logic level of the refresh period signal REF_FLAG, To the source clock CLK_IN and the delay locked clock DLL_CLK which are always input from the third operation controllers 210, 230, and 270.

As such, when the first to third operation controllers 210, 230, and 270 output the source clock CLK_IN and the delay lock clock DLL_CLK as they are, the register controlled delay lock loop DLL according to the embodiment of the present invention is provided. Performing the initialization delay lock operation of the circuit is in the same state as performing the initialization delay lock operation in the register controlled delay lock loop (DLL) circuit according to the prior art.

That is, the timing pulse generator 220, the phase comparator 240, the phase delay unit 260, and the delay model unit 280 provided inside the delay locked loop (DLL) circuit all operate normally and their phases are shifted. The phase of synchronizing the phase of the source clock CLK_IN and the feedback clock F_CLK is performed.

However, in the delay lock operation after initialization, since the delay lock signal LOCK_STATE output from the phase comparator 240 is activated with logic 'High', the delay lock signal LOCK_STATE is activated according to the logic level of the refresh period signal REF_FLAG. The source clock CLK_IN and the delay locked clock DLL_CLK inputted by the first to third operation controllers 210, 230, and 270 may be output as they are, or the source clock CLK_IN and the delay locked clock DLL_CLK may be input. It will decide whether to output a fixed signal regardless of the predetermined value.

First, when the refresh period signal REF_FLAG is activated as logic 'high' in the delay lock operation after initialization, the source clock CLK_IN and the delay input from the first to third operation controllers 210, 230, and 270 are delayed. Since the fixed clock DLL_CLK is output as it is, the timing pulse generator 220, the phase comparator 240, the phase delay unit 260, and the delay model unit provided inside the delay locked loop (DLL) circuit ( All of the operations 280 normally operate to synchronize phases of the source clock CLK_IN and the feedback clock F_CLK.

On the other hand, when the refresh period signal REF_FLAG is deactivated to logic 'low' in the delay lock operation after initialization, the source clock CLK_IN and the delay input from the first to third operation controllers 210, 230, and 270 are delayed. Since a fixed signal is output to a predetermined value irrespective of the fixed clock DLL_CLK, the timing pulse generator 220, the phase comparator 240, and the phase delay unit 260 provided inside the delay locked loop DLL circuit. ) And the delay model unit 280 do not operate normally so that the phase of the source clock CLK_IN and the feedback clock F_CLK are no longer performed.

That is, when a signal fixed to a predetermined value is output regardless of the source clock CLK_IN and the delay lock clock DLL_CLK input from the first to third operation controllers 210, 230, and 270, the delay lock loop DLL The source clock CLK_IN is no longer provided to the timing pulse generator 220 and the phase comparator 240 provided inside the circuit, and the delay locked clock DLL_CLK is no longer provided to the delay model unit 280. Not provided. Accordingly, the timing pulse generator 220, the phase comparator 240, and the delay model unit 280 do not perform any operation, and the values of the output signals TM_PUL, COMP_SIG, LOCK_STATE, and F_CLK are further increased. The state does not change abnormally.

Therefore, the value of the signal DLY <0: N> output from the delay control unit 264 among the components of the phase delay unit 260 is no longer changed, and therefore, the component of the phase delay unit 260 The delay amount of the variable delay line 262 also does not change any more.

Therefore, the phase difference between the source clock CLK_IN and the delay lock clock DLL_CLK whose phase difference is determined by the phase delay unit 260 is no longer changed, which means that the delay lock operation is no longer performed. It means the same thing as not being.

In conclusion, the delay locked loop (DLL) circuit according to the embodiment of the present invention, the delay after the initialization is performed after the initialization delay lock operation is completed and the delay lock signal (LOCK_STATE) is activated to the logic 'High' In the fixed operation, the phase of the source clock CLK_IN and the feedback clock F_CLK are synchronized only in a section in which the refresh section signal REF_FLAG is activated with logic 'high'.

That is, even after delay initialization operation, the phase of the source clock CLK_IN and the feedback clock F_CLK are synchronized only in a section in which the refresh section signal REF_FLAG is activated with logic 'high'. In the period where the refresh period signal REF_FLAG is logic 'low', the phase of the source clock CLK_IN and the feedback clock F_CLK are not synchronized, thus consuming current. I never do that.

At this time, the refresh period signal REF_FLAG is a signal that is activated at the time when the refresh command REF_CMD is activated and maintains the activation period for a predetermined time, and the refresh command REF_CMD is always in a state where power is supplied to the semiconductor memory device. Since the signal should be activated with a certain period, the operation of synchronizing the phases of the source clock CLK_IN and the feedback clock F_CLK may also be performed periodically.

As described above, according to the embodiment of the present invention, after the delay lock loop DLL performs the initialization delay lock operation, the phases of the source clock CLK_IN and the feedback clock F_CLK are synchronized once, After the delay lock signal LOCK_STATE is activated, the delay lock loop DLL may be synchronized with the phase of the source clock CLK_IN and the feedback clock F_CLK only when the refresh period signal REF_FLAG is activated. The current consumed in the circuit can be greatly reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, in the above-described embodiment, the phase of the source clock CLK_IN and the feedback clock F_CLK are synchronized in response to the refresh period signal REF_FLAG corresponding to the refresh command REF_CMD in the delay lock operation after initialization. Although it is said that the control is controlled, it is included in the scope of the present invention even when a signal which is periodically activated like the refresh command REF_CMD is used instead of the refresh period signal REF_FLAG corresponding to the refresh command REF_CMD.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram showing a general register controlled delay locked loop (DLL) circuit.

2 is a block diagram illustrating a register controlled delay locked loop (DLL) circuit in accordance with an embodiment of the present invention.

FIG. 3A is a circuit diagram showing in detail an operation control unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG.

FIG. 3B is a timing diagram showing the operation of the operation control unit among the components of the register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG. 2; FIG.

4A is a circuit diagram illustrating in detail a refresh section signal generation unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG.

4B is a timing diagram illustrating an operation of a refresh section signal generation unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100, 200: buffering unit 120, 220: timing pulse generator

140, 240: phase comparison unit 160, 260: phase delay unit

180, 280: delay model unit 162, 262: variable delay line

164, 264: delay control unit 210: first operation control unit

230: second operation control unit 270: third operation control unit

290: refresh section signal generator

Claims (15)

A delay locked loop for comparing a phase of a source clock and a feedback clock to give a delay value to be delayed to the source clock and outputting a delay locked loop clock; And Control unit for controlling the delay correction operation of the delay lock loop in response to the refresh section signal after delay lock Delay fixed loop circuit having a. The method of claim 1, The control unit, Enable the delay correction operation of the delay lock loop in response to the activation of the refresh period signal after the delay lock operation, And a delay correction loop of the delay lock loop is disabled in response to the refresh period signal being deactivated after the delay lock operation. The method of claim 1, The delay lock loop, A phase comparator for comparing phases of the source clock and the feedback clock; A phase delay unit for delaying the source clock by a delay amount that changes in correspondence with an output signal of the phase comparison unit and outputting the delayed clock as the delay locked loop clock; And And a delay model section for reflecting the delay time of an actual output path in the delay lock loop clock and outputting the delay clock as the feedback clock. The method of claim 3, The control unit, A source clock transfer control unit for controlling on / off of providing the source clock to the phase comparator in response to a delay lock signal and the refresh period signal; And And a delay lock clock transfer control unit for controlling on / off of providing the delay lock loop clock to the delay model in response to the delay lock signal and the refresh period signal. The method of claim 4, wherein The source clock transfer control unit, When the refresh period signal is activated while the delay lock signal is activated, the source clock is provided to the phase comparator. When the refresh period signal is deactivated while the delay lock signal is activated, the source clock is not provided to the phase comparator. And the source clock is supplied to the phase comparator, regardless of the refresh period signal, when the delay lock signal is inactivated. The method of claim 4, wherein The delay locked clock transfer control unit, When the refresh period signal is activated in the state that the delay lock signal is activated, the delay lock clock is provided to the phase comparator, When the refresh period signal is deactivated while the delay lock signal is activated, the delay lock clock is not provided to the phase comparator. And the delay lock signal is provided to the phase comparison unit irrespective of the refresh period signal when the delay lock signal is inactivated. The method of claim 1, And a refresh section signal generation section for generating the refresh section signal that maintains an active state for a predetermined time in response to a refresh command. Comparing a phase of a source clock and a feedback clock to give a delay value that is delay locked to the source clock and outputting a delay locked loop clock; And Controlling a clock path of the delay locked loop to disable delay correction of the delay locked loop during the non-refresh interval after the delay lock. Method of driving a delay locked loop comprising a. The method of claim 8, And controlling the clock path of the delay lock loop to enable delay correction operation of the delay lock loop during the refresh period after delay lock. 10. The method of claim 9, The step of outputting the delay locked loop clock, Comparing phases of the source clock and the feedback clock; Delaying the source clock by a variable amount of delay corresponding to a result of comparing the phases and outputting the delayed clock as the delay locked loop clock; And reflecting the delay time of an actual output path to the delay locked loop clock and outputting the feedback clock as the feedback clock. The method of claim 10, The controlling of the clock path of the delay locked loop may include: Opening a path through which the source clock is transferred to comparing the phases during a non-refresh period after delay lock; And And shortening a path through which the source clock is transferred to comparing the phases during a refresh period after delay lock. The method of claim 10, The controlling of the clock path of the delay locked loop may include: Opening a path through which the delay locked loop clock is transmitted to reflect the delay time of the actual output path during the non-refresh interval after the delay lock; And And shortening a path from which the delay locked loop clock is transmitted to reflect the delay time of the actual output path during the refresh period after the delay lock. A buffering unit configured to generate a source clock by buffering an externally applied clock; A timing pulse generator for generating a timing pulse that is activated at a predetermined number of times at a predetermined time point in response to the source clock at a predetermined time; A phase comparator configured to receive the source clock and the feedback clock at a time defined by the timing pulse and compare phases thereof; A phase delay unit configured to adjust a delay amount corresponding to an output signal of the phase comparison unit at a time point defined by the timing pulse, receive the source clock, delay the phase, and output the delayed clock as a delay locked clock; A delay model unit for receiving the delay lock clock and outputting the delay clock of the actual output path as the feedback clock; And An operation control unit for controlling on / off operation of the timing pulse generator, the phase comparison unit, and the delay model unit in response to a delay lock signal and a refresh period signal; Delay fixed loop circuit having a. The method of claim 13, The operation control unit, A first operation controller configured to control on / off that the source clock is transmitted in response to the delay lock signal and the refresh period signal between the buffering unit and the timing pulse generator; A second operation controller configured to control on / off that the source clock is transmitted in response to the delay lock signal and the refresh period signal between the buffering unit and the phase comparator; And And a third operation control unit configured to control on / off that the delay locked clock is transmitted between the phase delay unit and the delay model unit in response to the delay lock signal and the refresh period signal. Circuit. The method of claim 13, And a refresh section signal generation section for generating the refresh section signal that maintains an active state for a predetermined time in response to a refresh command.
KR1020080134928A 2008-12-26 2008-12-26 Delay locked loop circuit KR20100076766A (en)

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