KR100922881B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR100922881B1
KR100922881B1 KR1020080034608A KR20080034608A KR100922881B1 KR 100922881 B1 KR100922881 B1 KR 100922881B1 KR 1020080034608 A KR1020080034608 A KR 1020080034608A KR 20080034608 A KR20080034608 A KR 20080034608A KR 100922881 B1 KR100922881 B1 KR 100922881B1
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South Korea
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clock
data
output
control clock
response
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KR1020080034608A
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Korean (ko)
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구영준
이강설
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주식회사 하이닉스반도체
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals

Abstract

PURPOSE: A semiconductor memory device is provided to reduce a miss match between a replica circuit and a real data path. CONSTITUTION: A semiconductor memory device includes a first clock driving unit(300), an internal circuit(370), a second clock driving unit(310), and a data output unit(360). The first clock driving unit drives a first delay-locked loop clock(RCLK) and a second delay-locked loop clock(FCLK). The internal circuit performs a predetermined internal operation in response to an output clock of the first clock driving unit. The second clock driving unit drives the first delay-locked loop clock and the second delay-locked loop clock, and outputs the driven clocks as a first output control clock and a second output control clock. The data output unit applies a first internal data as an output data to a data pad in response to the first output control clock. The data output unit applies a second internal data as an output data to the data pad in response to the second output control clock.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor design technology, and more particularly, to a data output device of a semiconductor memory device, and more particularly to a data output device of a semiconductor memory device capable of stably outputting data even in a low power supply (LOW VDD) state. It is about.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller (CTRL).

This is because the temporal synchronization between the external clock and the data output from the memory is very important to the stable data transfer between the memory and the memory controller.

At this time, the data output from the memory is output in synchronization with the internal clock. When the internal clock is initially applied to the memory, the internal clock is applied in synchronization with the external clock. When it is output, it is output out of sync with external clock.

Therefore, for stable transmission of data output from the memory, the delayed internal clock is accurately positioned at the edge or center of the external clock applied by the memory controller while passing through each component in the memory transmitting the data. The risk is to compensate the internal clock time with the internal clock so that the internal and external clocks are synchronized.

Clock synchronizing circuits that perform this role include a phase locked loop (PLL) circuit and a delay locked loop circuit (DLL) circuit.

Of these, when the frequency of the external clock and the internal clock are different from each other, the frequency lock function should be used. Therefore, a phase locked loop (PLL) is used. However, when the frequency of the external clock is the same as the frequency of the internal clock, a delayed fixed loop circuit (DLL) that can be implemented in a relatively small area is mainly used compared to the phase locked loop (PLL). That is, in the case of the semiconductor memory device, since the frequency used is the same, the delay locked loop circuit DLL is mainly used as the clock synchronization circuit.

1 is a circuit diagram illustrating a data output apparatus of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a data output apparatus of a semiconductor memory device according to the related art includes a first drive clock RCLK_DLL and an external clock configured to drive a first delay locked loop clock RCLK synchronized to a rising edge of an external clock. It can be seen that the data RDO and FDO inside the semiconductor memory device are output by using the second driving clock FCLK_DLL driving the second delay locked loop clock FCLK synchronized to the falling edge.

Specifically, the first clock driver 100 for driving the first delay locked loop clock RCLK in the activation period of the drive control signal DRV_EN and outputting the first delayed clock RRC_DLL as the first drive clock RCLK_DLL and the drive control signal DRV_EN The second clock driver 105 for driving the second delay locked loop clock FCLK and outputting it as the second drive clock FCLK_DLL in the activation period of the first delay signal and the first command signal ROUTEN. The third clock driver 110 for driving the driving clock RCLK_DLL and outputting the first output control clock RCLK_DOb and the second driving clock FCLK_DLL in the activation section of the second command signal FOUTEN are driven. First activation for adjusting the activation period of the first output control clock RCLK_DOb based on the fourth clock driver 115 for outputting as the second output control clock FCLK_DOb and the second output control clock FCLK_DOb. Second output control based on the section controller 120 and the first output control clock RCLK_DOb First output control by receiving the second activation section control unit 125 for adjusting the activation section of the lock FCLK_DOb and the first output control clock RCLK_DOb output through the first activation section adjustment unit 120. A first split part for splitting the first control clock RCLK_DO2b corresponding to the rising edge of the clock RCLK_DOb and the second control clock RCLK_DO2 corresponding to the falling edge of the first output control clock RCLK_DOb. 130 and the third control clock FCLK_DO2b corresponding to the rising edge of the second output control clock FCLK_DOb by receiving the second output control clock FCLK_DOb outputted through the second activation section adjusting unit 125. And a second split unit 135 for splitting into the fourth control clock FCLK_DO2 corresponding to the falling edge of the second output control clock FCLK_DOb, the first control clock RCLK_DO2b, and the second control clock. The first transfer control unit 1 for controlling the transfer of the first internal data RDO to the output node OUT_NODE in response to RCLK_DO2. A second transfer control unit 145 for controlling the transfer of the second internal data FDO to the output node OUT_NODE in response to the 40 and the third control clock FCLK_DO2b and the fourth control clock FCLK_DO2; In response to the data driving unit 150 for driving data loaded on the output node OUT_NODE to the data pad DQ, and in response to the first driving clock RCLK_DLL and the second driving clock FCLK_DLL, a predetermined internal operation is performed. An internal circuit 170 is provided.

The operation thereof will be described based on the configuration of the data output device of the semiconductor memory device according to the related art as described above.

FIG. 2 is a timing diagram illustrating an operation of a data output apparatus of a semiconductor memory device according to the related art shown in FIG. 1.

Referring to FIG. 2, the first clock driver 100 and the second clock driver 105 of the components of the data output apparatus of the semiconductor memory device according to the related art each have a first delay synchronized to the rising edge of the external clock. The fixed loop clock RCLK is driven and output as the first driving clock RCLK_DLL, and the second delayed fixed loop clock FCLK synchronized with the falling edge of the external clock is driven to output the second driving clock FCLK_DLL. It can be seen that. In this case, since the driving control signal DRV_EN is always in a logic 'high' state, the first delay locked loop clock RCLK and the first driving clock RCLK_DLL are always synchronized and toggled at the same time. It seems that the second delay locked loop clock FCLK and the second drive clock FCLK_DLL are always synchronized and toggled at the same time, but in reality, if the driving control signal DRV_EN becomes a logic 'low', the first Even when the delay locked loop clock RCLK is toggled, the first drive clock RCLK_DLL is not toggled and the second drive clock FCLK_DLL is toggled even when the second delayed locked clock FCLK is toggled. It is in a state of not ringing. That is, the operation of the first clock driver 100 and the second clock driver 105 is controlled on / off according to the driving control signal DRV_EN.

The third clock driving unit 110 and the fourth clock driving unit 115 respectively drive the first driving clock RCLK_DLL to output the first output control clock RCLK_DOb, and the second driving clock FCLK_DLL. It can be seen that the output signal is driven as the second output control clock FCLK_DOb.

At this time, the first command signal ROUTEN and the second command signal FOUTEN remain active at a logic 'high' in a predetermined section, and become inactive at a logic 'low' in the remaining sections. .

Accordingly, the first driving clock RCLK_DLL is driven and output as the first output control clock RCLK_DOb in the section in which the first command signal ROUTEN is activated with logic 'high', so that the first driving clock ( RCLK_DLL) and the first output control clock RCLK_DOb are synchronized and toggled at the same time. In the section where the first command signal ROUTEN is deactivated as logic 'low', the first drive clock RCLK_DLL is executed. Since it is not driven, the first output control clock RCLK_DOb is not toggled regardless of the toggling of the first driving clock RCLK_DLL.

Similarly, in the period in which the second command signal FOUTEN is activated with logic 'High', the second drive clock FCLK_DLL is output as the second output control clock FCLK_DOb by driving the second drive clock FCLK_DLL. ) And the second output control clock FCLK_DOb are synchronized and simultaneously toggled, and the second drive clock FCLK_DLL is driven in a section in which the second command signal FOUTEN is deactivated by logic 'low'. Therefore, the second output control clock FCLK_DOb is not toggled regardless of the toggling of the second driving clock FCLK_DLL.

As such, the first command signal ROUTEN and the second command signal FOUTEN, which control the operations of the third clock driver 110 and the fourth clock driver 115, are externally output to output data from the semiconductor memory device. When a read command is applied, the signal is activated after a Cas Latency value preset in a memory register set (MRS).

In addition, referring to FIG. 2, the first activation section adjustment unit 120 and the second activation section adjustment unit 125 may not know exactly what operation.

Therefore, the operation of the first activation section adjusting unit 120 will be described in detail. When the second output control clock FCLK_DOb becomes logic 'low' and is inactive, the first output control clock RCLK_DOb is disabled. This unconditional logic is controlled to be in an active state of 'High'.

Similarly, when the operation of the second activation section adjusting unit 125 is described in detail, when the first output control clock RCLK_DOb becomes logic 'low' and is in an inactive state, the second output control clock FCLK_DOb is inactive. This unconditional logic is controlled to be in an active state of 'High'.

That is, the first activation section adjusting unit 120 and the second activation section adjusting unit 125 may overlap the activation section of the first output control clock RCLK_DOb and the activation section of the second output control clock FCLK_DOb. Prevents.

The first splitter 130 receives the first output control clock RCLK_DOb and receives the first control clock RCLK_DO2b and the second control clock corresponding to the rising and falling edges of the first output control clock RCLK_DOb. It can be seen that an operation of splitting and outputting to (RCLK_DO2) is performed. That is, the first split unit 130 receives the first output control clock RCLK_DOb and maintains a synchronous state with the first output control clock RCLK_DOb, while the first control clock RCLK_DO2b and the second control clock are mutually opposite. This role is to generate (RCLK_DO2).

Similarly, the second split unit 135 receives the second output control clock FCLK_DOb and receives a third control clock FCLK_DO2b and a fourth control clock corresponding to the rising and falling edges of the second output control clock FCLK_DOb. It can be seen that an operation of splitting and outputting to (FCLK_DO2) is performed. That is, the second split unit 135 receives the second output control clock FCLK_DOb and maintains a synchronous state with the second output control clock FCLK_DOb, while the third control clock FCLK_DO2b and the fourth control clock are opposite to each other. It is a role for generating (FCLK_DO2).

The first transfer control unit 140 is applied when the first control clock RCLK_DO2b is deactivated to a logic 'low' and the second control clock RCLK_DO2 is activated to a logic 'high'. The first internal data RDO-'D1', 'D3', 'D5', and 'D7'-is transmitted to the output node OUT_NODE in the drawing.

Similarly, the second transfer control unit 145 is applied when the third control clock FCLK_DO2b is deactivated logic 'low' and the fourth control clock FCLK_DO2 is activated logic 'high'. The second internal data FDO-'D2', 'D4', 'D6', and 'D8'-are transmitted to the output node OUT_NODE (②).

In addition, the data driving unit 150 always displays the data contained in the output node OUT_NODE regardless of whether the data contained in the output node OUT_NODE is the first internal data RDO or the second internal data FDO. Driving to the data pad DQ is performed.

The data output device of the semiconductor memory device according to the prior art operates through the above-described process, and the data output device of the semiconductor memory device according to the prior art may cause the following problems.

In the delay locked loop (DLL), a duty ratio correction circuit for adjusting the duty ratio of the first delay locked loop clock RCLK and the second delay locked loop clock FCLK to 50 to 50 is generally output. : DCC), which causes the first delay locked loop clock (RCLK) and the second delay locked loop clock (FCLK) to be set to a 50 to 50 duty ratio, as well as the first delay locked loop clock ( The duty ratio of the first driving clock RCLK_DLL and the second driving clock FCLK_DLL generated by driving the RCLK and the second delay locked loop clock FCLK is also set to 50 to 50. In other words, the activation section of the first delayed fixed loop clock RCLK and the activation section of the second delayed fixed loop clock FCLK overlap, or the activation section of the first driving clock RCLK_DLL and the activation of the second driving clock FCLK_DLL overlap. Intervals cannot overlap.

In this way, the duty ratio of the first driving clock RCLK_DLL and the second driving clock FCLK_DLL is set to be exactly 50 to 50 so that the activation section of the first driving clock RCLK_DLL and the activation section of the second driving clock FCLK_DLL are output. Although not overlapped, the activation period of the first output control clock RCLK_DOb and the second output control clock FCLK_DOb generated for use in the data output apparatus of the semiconductor memory device according to the prior art overlap Can lose.

The reason is that the first driving clock RCLK_DLL and the second driving clock FCLK_DLL are not used only in the third clock driving unit 110 and the fourth clock driving unit 115. The first driving clock RCLK_DLL generated by the first clock driving unit 100 and the second driving clock FCLK_DLL generated by the second clock driving unit 105 are respectively the third clock driving unit 110 and the fourth clock driving unit ( It is used not only in 115 but also in the internal circuit 170 for performing a predetermined internal operation. Therefore, the load on the first drive clock RCLK_DLL and the load on the second drive clock FCLK_DLL may be different from each other, which causes the duty ratio of the first drive clock RCLK_DLL and the second drive clock FCLK_DLL to be different. This may cause a problem that the activation section of the first driving clock RCLK_DLL overlaps with the activation section of the second driving clock FCLK_DLL, and thus, the first output control clock RCLK_DOb and the second output may occur. The activation interval of the control clock FCLK_DOb may also overlap.

Accordingly, in the data output apparatus of the semiconductor memory device according to the related art, the first output control clock RCLK_DOb and the second output are provided by including the first activation section adjusting unit 120 and the second activation section adjusting section 125 therein. We tried to solve the problem of overlapping the activation section of the control clock (FCLK_DOb).

Of course, when the first activation section adjusting unit 120 and the second activation section adjusting unit 125 operate normally, the activation sections of the first output control clock RCLK_DOb and the second output control clock FCLK_DOb overlap each other. I could solve the problem.

However, the first activation period adjusting unit 120 and the second activation period adjusting unit 125 use the second output control clock FCLK_DOb as described above to determine the activation period of the first output control clock RCLK_DOb. And the activation period of the second output control clock FCLK_DOb is adjusted using the first output control clock RCLK_DOb, so that the level of the power supply voltage VDD supplied to the semiconductor memory device is lower than or equal to the predetermined voltage level. When the low voltage supplied to the low voltage (Low VDD) state does not operate normally, there is a problem that does not properly correct the overlap between the activation period of the first output control clock (RCLK_DOb) and the second output control clock (FCLK_DOb).

As such, in the semiconductor memory device having a low voltage (VDD) state, the first activation period adjusting unit 120 and the second activation period adjusting unit 125 may not operate properly. As a result, the first output control clock RCLK_DOb may not operate properly. When the first and second output control clocks FCLK_DOb are applied to the first splitter 130 and the second splitter 140 in an overlapping state, the first output control clock RCLK_DOb and the second output control clock ( The first transfer control unit 140 and the first operation control unit (On / Off) is controlled in response to the first split unit 130 and the second split unit 140 for a time overlapping the activation period of FCLK_DOb) There arises a problem that the operation timing of the two transfer control unit 145 overlaps.

That is, the first internal data RDO and the second internal having different values on the same data pad DQ during the time period where the activation periods of the first output control clock RCLK_DOb and the second output control clock FCLK_DOb overlap. Since the data FDO is simultaneously transmitted and output as the output data DATA through the data pad DQ, the output data during the overlapping period of activation of the first output control clock RCLK_DOb and the second output control clock FCLK_DOb. There is a problem that (DATA) can not be trusted.

The present invention has been proposed to solve the above problems of the prior art, by using an output control clock corresponding to a delay locked loop clock only in a data output device of a semiconductor memory device, thereby ensuring stable data even in a low power supply (LOW VDD) state. It is an object of the present invention to provide a data output device of a semiconductor memory device capable of outputting the.

According to an aspect of the present invention for achieving the above object, the first clock driving means for driving the first delay locked loop clock and the second delay locked loop clock; An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means; Second clock driving means for driving the first delay locked loop clock and the second delay locked loop clock to output each of the first delay control loop clock and the second delay control loop clock; And a data output for applying first internal data to the data pad in response to the first output control clock and applying the second internal data to the data pad in response to the second output control clock. A semiconductor memory device having means is provided.

In addition, according to another aspect of the present invention for achieving the above object to be solved, the first clock driving for driving the first delay locked loop clock and the second delay locked loop clock in the activation period of the drive control signal, respectively; Way; An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means; Second clock driving means for driving the first delay locked loop clock and the second delay locked loop clock to output as a first output control clock and a second output control clock in an activation period of a command signal; And a data output for applying first internal data to the data pad in response to the first output control clock and applying the second internal data to the data pad in response to the second output control clock. A semiconductor memory device having means is provided.

In addition, according to another aspect of the present invention for achieving the above object to be solved, the first clock driving means for driving each of the clock and the sub-clock; An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means; Second clock driving means for driving the positive clock and the subclock, respectively, and outputting them as a constant output control clock and a sub output control clock; And data output means for applying first internal data to the data pad in response to the positive output control clock, and applying second internal data as the output data to the data pad in response to the sub output control clock. Provided is a semiconductor memory device.

Further, according to another aspect of the present invention for achieving the above object to be solved, the first clock driving means for driving each of the positive clock and the sub-clock in the activation period of the drive control signal; An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means; Second clock driving means for driving the positive clock and the sub-clock in the activation period of the command signal and outputting the positive clock and the sub-output control clock respectively; And data output means for applying first internal data to the data pad in response to the positive output control clock, and applying second internal data as the output data to the data pad in response to the sub output control clock. Provided is a semiconductor memory device.

The present invention described above generates a first output control clock and a second output control clock corresponding to the first delay locked loop clock and the second delay locked loop clock having phases opposite to each other, and are used only in the data output device of the semiconductor memory device. In this case, the data can be stably output even in a low power supply (LOW VDD) state.

This reduces the miss match between the replica circuit and the actual data path, which model and use the data path inside the delay locked loop (DLL). There is.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. Therefore, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform complete.

3A is a circuit diagram illustrating a data output apparatus of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 3A, a data output apparatus of a semiconductor memory device according to a first embodiment of the present invention may include a first output control clock driving a first delay locked loop clock RCLK_DLL synchronized to a rising edge of an external clock. It is seen that the data RDO and FDO inside the semiconductor memory device are output using the second output control clock FCLK_DLL_DQ driving the RCLK_DLL_DQ) and the second delay locked loop clock FCLK synchronized to the falling edge of the external clock. Can be.

Specifically, the output clocks RCLK_DLL and FCLK_DLL of the first clock driver 300 and the first clock driver 300 for driving the first delay locked loop clock RCLK and the second delay locked loop clock FCLK, respectively. In response to the first output control clock RCLK_DLL_DQ by driving the internal circuit 370 and the first delay locked loop clock RCLK and the second delay locked loop clock FCLK, respectively, to perform a predetermined internal operation. In response to the second clock driver 310 for outputting as the second output control clock FCLK_DLL_DQ, and the first output control clock RCLK_DLL_DQ, the first internal data RDO is used as the output data DATA and the data pad DQ. ) And a data output unit 360 for applying the second internal data FDO as the output data DATA to the data pad DQ in response to the second output control clock FCLK_DLL_DQ.

Here, the first clock driver 300 may include a first drive clock output unit 302 and a second delay locked loop for driving the first delay locked loop clock RCLK and outputting the first clock clock RCLK_DLL. A second drive clock output unit 304 is provided for driving the clock FCLK to output the second drive clock FCLK_DLL.

In addition, the second clock driver 310 drives the first delay locked loop clock RCLK to output the first output control clock RCLK_DLL_DQ to output the first output control clock 312 and the second delay. A second output control clock output unit 314 for driving the fixed loop clock FCLK and outputting the second output control clock FCLK_DLL_DQ is provided.

The data output unit 360 transfers the first data for transmitting the first internal data RDO to the output node OUT_NODE in response to the first command signal ROUTEN and the first output control clock RCLK_DLL_DQ. A second data transfer unit 364 for transferring the second internal data FDO to the output node OUT_NODE in response to the unit 362 and the second command signal FOUTEN and the second output control clock FCLK_DLL_DQ. And a data driving unit 366 for driving the data on the output node OUT_NODE-the first internal data RDO or the second internal data FDO-to the data pad DQ.

In addition, among the components of the data output unit 360, the first data transfer unit 362 receives the first output control clock RCLK_DLL_DQ during the activation period of the first command signal ROUTEN, and receives the first output control clock ( A split unit 3622 for splitting into the first control clock RCLK_DLL_DQ2 corresponding to the rising edge of the RCLK_DLL_DQ and the second control clock RCLK_DLL_DQ2b corresponding to the falling edge, and the first control. The transfer control unit 3624 is configured to control the transfer of the first internal data RDO to the output node OUT_NODE in response to the clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b.

The second data transfer unit 364 of the components of the data output unit 360 receives the second output control clock FCLK_DLL_DQ during the activation period of the second command signal FOUTEN and receives the second output control clock ( A split part 3424 for splitting into the first control clock FCLK_DLL_DQ2 corresponding to the rising edge of the FCLK_DLL_DQ and the second control clock FCLK_DLL_DQ2b corresponding to the falling edge, and the first control. A transfer control unit 3644 is provided to control the transfer of the second internal data FDO to the output node OUT_NODE in response to the clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b.

The operation thereof will be described based on the configuration of the data output apparatus of the semiconductor memory device according to the first embodiment of the present invention as described above.

3B is a timing diagram illustrating an operation of a data output apparatus of a semiconductor memory device according to the first embodiment of the present invention shown in FIG. 3A.

Referring to FIG. 3B, the first clock driver 300 of the components of the data output apparatus of the semiconductor memory device according to the first embodiment of the present invention may include a first delay locked loop clock synchronized to the rising edge of the external clock. It can be seen that the RCLK is driven and output as the first driving clock RCLK_DLL, and the second delay locked loop clock FCLK synchronized with the falling edge of the external clock is driven and output as the second driving clock FCLK_DLL. .

The second clock driver 310 drives the first delay locked loop clock RCLK synchronized with the rising edge of the external clock to output the first delay control loop clock RCLK_DLL_DQ and synchronizes with the falling edge of the external clock. It can be seen that the second delay locked loop clock FCLK is driven and output as the second output control clock FCLK_DLL_DQ.

That is, it can be seen that the first clock driver 300 and the second clock driver 310 operate independently without affecting each other's driving operation.

Here, how the first driving clock RCLK_DLL and the second driving clock FCLK_DLL output from the first clock driving unit 300 among the first clock driving unit 300 and the second clock driving unit 310 are used. Although not shown in FIG. 3B, as described in the configuration of FIG. 3A, it is applied to the internal circuit 370 of the semiconductor memory device to perform a predetermined internal operation.

That is, the internal circuit 370 performs a predetermined internal operation in response to the first driving clock RCLK_DLL and the second driving clock FCLK_DLL in the activation section of the driving control signal DRV_EN, and drives the driving control signal DRV_EN. In the deactivation section, the internal operation is not performed regardless of the first driving clock RCLK_DLL and the second driving clock FCLK_DLL.

In addition, the data output unit 360 uses the first internal data RDO as the output data DATA in response to the first output control clock RCLK_DLL_DQ in the activation period of the first command signal ROUTEN. ), And does not apply the first internal data RDO to the data pad DQ regardless of the first output control clock RCLK_DLL_DQ during the inactivation period of the first command signal ROUTEN.

In addition, the data output unit 360 outputs the second internal data FDO as the output data DATA in response to the second output control clock FCLK_DLL_DQ during the activation period of the second command signal FOUTEN. DQ) and the second internal data FDO is not applied to the data pad DQ regardless of the second output control clock FCLK_DLL_DQ in the inactivation section of the second command signal FOUTEN.

The first data transfer unit 362 of the components of the data output unit 360 may be connected to the first clock driver 300 in a section in which the first command signal ROUTEN is activated as logic 'high'. Splitting the first output control clock (RCLK_DLL_DQ) output from the second clock driver 310 of the second clock driver 310 outputs the first control clock (RCLK_DLL_DQ2) and the second control clock (RCLK_DLL_DQ2b), and the split The first internal data RDO is transmitted to the output node OUT_NODE by using the first control clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b.

Similarly, the second data transfer unit 364 of the components of the data output unit 360 may be connected to the first clock driver 300 in a section in which the second command signal FOUTEN is activated as logic 'high'. The second output control clock FCLK_DLL_DQ output from the second clock driver 310 of the second clock driver 310 is split to output the first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b. The second internal data FDO is controlled to be transmitted to the output node OUT_NODE by using the first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b.

Among the components of the data output unit 360, the data driving unit 366 always outputs the data contained in the output node OUT_NODE regardless of whether the first internal data RDO or the second internal data FDO is used. The data stored in the node OUT_NODE is driven to the predetermined data pad DQ.

That is, among the components of the data output unit 360, the first data transfer unit 362 and the data driving unit 366 have a state in which the first output control clock RCLK_DLL_DQ is activated with logic 'High'. The first internal data RDO applied when the first control clock RCLK_DLL_DQ2 is activated with logic 'high' and the second control clock RCLK_DLL_DQ2b is deactivated with logic 'low'-in the drawing. Performs the operation (①) of transferring 'D1', 'D3', 'D5', 'D7'-to the output node OUT_NODE.

Similarly, among the components of the data output unit 360, the second data transfer unit 364 and the data driving unit 366 may have a state in which the second output control clock FCLK_DLL_DQ is activated with logic 'High'. Second internal data FDO applied while the first control clock FCLK_DLL_DQ2 is activated with logic 'high' and the second control clock FCLK_DLL_DQ2b is deactivated with logic 'low'-in the drawing. 'D2', 'D4', 'D6', 'D8'-transmits the output node OUT_NODE (②).

4A is a circuit diagram illustrating a data output apparatus of a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 4A, the data output apparatus of the semiconductor memory device according to the second embodiment of the present invention is synchronized with the rising edge of the external clock, similarly to the data output apparatus of the semiconductor memory device according to the first embodiment of the present invention. The first output control clock RCLK_DLL_DQ driving the first delay locked loop clock RCLK_DLL and the second output control clock FCLK_DLL_DQ driving the second delay locked loop clock FCLK synchronized to the falling edge of the external clock. It can be seen that the data RDO and FDO in the semiconductor memory device are output by using the same.

Specifically, the first clock driver 400 and the first clock driver for driving the first delay locked loop clock RCLK and the second delay locked loop clock FCLK in the activation period of the drive control signal DRV_EN, respectively. In response to the output clocks RCLK_DLL and FCLK_DLL of 400, an internal circuit 470 for performing a predetermined internal operation, and a first delayed fixed loop clock RCLK and a first signal in an activation period of the command signals ROUTEN and FOUTEN. The second clock driver 410 and the first output control clock RCLK_DLL_DQ for driving the two delay locked loop clocks FCLK and outputting the first output control clock RCLK_DLL_DQ and the second output control clock FCLK_DLL_DQ, respectively. In response to the first internal data RDO, the first internal data RDO is applied to the data pad DQ as the output data DATA, and the second internal data FDO is output to the output data DATA in response to the second output control clock FCLK_DLL_DQ. And a data output unit 460 for applying to the data pad DQ.

Here, the first clock driver 400 drives the first delay locked loop clock RCLK in the activation period of the driving control signal DRV_EN to output the first clock clock RCLK_DLL as the first driving clock RCLK_DLL. 402, and a second drive clock output unit 404 for driving the second delay locked loop clock FCLK in the activation period of the drive control signal DRV_EN and outputting it as a second drive clock FCLK_DLL. .

In addition, the second clock driver 410 drives the first delay locked loop clock RCLK during the activation period of the first command signal ROUTEN to output the first output control clock RCLK_DLL_DQ as a first output. The second output control clock output for driving the second delay locked loop clock FCLK in the activation period of the second command signal FOUTEN and outputting it as the second output control clock FCLK_DLL_DQ during the activation period of the second command signal FOUTEN. The part 414 is provided.

The data output unit 460 may include a first data transfer unit 462 for transferring the first internal data RDO to the output node OUT_NODE in response to the first output control clock RCLK_DLL_DQ. A second data transfer unit 464 for transferring the second internal data FDO to the output node OUT_NODE in response to the output control clock FCLK_DLL_DQ, and data contained in the output node OUT_NODE-the first internal data. And a data driving unit 466 for driving the RDO or the second internal data FDO to the data pad DQ.

In addition, among the components of the data output unit 460, the first data transfer unit 462 receives the first output control clock RCLK_DLL_DQ and corresponds to a rising edge of the first output control clock RCLK_DLL_DQ. A split unit 4462 for splitting the first control clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b corresponding to the falling edge, and the first control clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b. A transfer control unit 4624 for controlling the transfer of the first internal data RDO to the output node OUT_NODE.

The second data transfer unit 464 of the components of the data output unit 460 receives the second output control clock FCLK_DLL_DQ and corresponds to the rising edge of the second output control clock FCLK_DLL_DQ. Split section 4442 for splitting into the first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b corresponding to the falling edge, and the first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b. And a transfer control unit 4446 for controlling the transfer of the second internal data FDO to the output node OUT_NODE.

The operation thereof will be described based on the configuration of the data output device of the semiconductor memory device according to the second embodiment of the present invention as described above.

4B is a timing diagram illustrating an operation of a data output apparatus of a semiconductor memory device according to the second embodiment of the present invention shown in FIG. 4A.

Referring to FIG. 4B, the first clock driver 400 of the components of the data output apparatus of the semiconductor memory device according to the second embodiment of the present invention may include a first delay locked loop clock synchronized to the rising edge of the external clock. RCLK is driven in the activation period of the drive control signal DRV_EN to output it as the first drive clock RCLK_DLL, and the second delayed fixed loop clock FCLK synchronized to the falling edge of the external clock is driven by the drive control signal DRV_EN. It can be seen that the device is driven in the activation section of and output as the second drive clock FCLK_DLL.

In this case, since the driving control signal DRV_EN is always in a logic 'high' state, the first delay locked loop clock RCLK and the first driving clock RCLK_DLL are always synchronized and toggled at the same time. It seems that the second delay locked loop clock FCLK and the second drive clock FCLK_DLL are always synchronized and toggled at the same time, but in reality, if the driving control signal DRV_EN becomes a logic 'low', the first Even when the delay locked loop clock RCLK is toggled, the first drive clock RCLK_DLL is not toggled, and even when the second delayed locked clock FCLK is toggled, the second drive clock FCLK_DLL is not toggled. It is in a non-toggling state. That is, the first clock driver 400 is controlled on / off according to the driving control signal DRV_EN.

The second clock driver 410 drives the first delay locked loop clock RCLK synchronized with the rising edge of the external clock in the activation period of the first command signal ROUTEN to thereby output the first output control clock RCLK_DLL_DQ. It can be seen that the second delay locked loop clock FCLK synchronized to the falling edge of the external clock is driven as the second output control clock FCLK_DLL_DQ in the activation period of the first command signal ROUTEN. .

At this time, the first command signal ROUTEN and the second command signal FOUTEN remain active at logic 'High' in a predetermined section, and are deactivated at logic 'Low' in the remaining sections. It can be seen that.

Accordingly, in the section in which the first command signal ROUTEN is activated with logic 'High', the first drive clock RCLK_DLL is driven to output as the first output control clock RCLK_DLL_DQ, so the first drive clock ( The RCLK_DLL and the first output control clock RCLK_DLL_DQ are synchronized and toggled at the same time, and the first driving clock RCLK_DLL is executed in a section in which the first command signal ROUTEN is deactivated as logic 'low'. Since it is not driven, the first output control clock RCLK_DLL_DQ is not toggled regardless of the toggling of the first driving clock RCLK_DLL.

Similarly, in the section in which the second command signal FOUTEN is activated with logic 'high', the second drive clock FCLK_DLL is driven to output as the second output control clock FCLK_DLL_DQb, so the second drive clock ( FCLK_DLL) and the second output control clock FCLK_DLL_DQb are synchronized and toggled at the same time, and the second drive clock FCLK_DLL is executed in a section in which the second command signal FOUTEN is deactivated as logic 'low'. Since it is not driven, the second output control clock FCLK_DLL_DQb is not toggled regardless of the second driving clock FCLK_DLL.

As such, the first command signal ROUTEN and the second command signal FOUTEN, which control the operation of the second clock driver 410, are externally supplied with a read command to output data from the semiconductor memory device. The signal is activated after a Cas Latency value preset in the memory register set (MRS).

In conclusion, since the first clock driver 400 and the second clock driver 410 receive the first delay locked loop clock RCLK and the second delay locked loop clock FCLK, respectively, the first clock driver 400 and the second clock driver 410 operate. It can be seen that it does not affect.

And, how the first driving clock (RCLK_DLL) and the second driving clock (FCLK_DLL) output from the first clock driving unit 400 of the first clock driving unit 400 and the second clock driving unit 410 is used. Although not shown in FIG. 4B, as described in the configuration of FIG. 4A, it is applied to the internal circuit 470 of the semiconductor memory device to perform a predetermined internal operation.

The data output unit 460 applies the first internal data RDO as the output data DATA to the data pad DQ in response to the first output control clock RCLK_DLL_DQ and outputs the second output control clock. In response to FCLK_DLL_DQ, the second internal data FDO is applied to the data pad DQ as output data DATA.

At this time, the first data transfer unit 462 of the components of the data output unit 460, the first clock output unit 410 and the second clock driver 410 of the second clock driver 410 is output from the first Splitting the output control clock RCLK_DLL_DQ to output the first control clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b, and using the split first control clock RCLK_DLL_DQ2 and the second control clock RCLK_DLL_DQ2b. Controls that the internal data RDO is transmitted to the output node OUT_NODE.

Similarly, the second data transfer unit 464 of the components of the data output unit 460 is the second output from the second clock driver 410 of the first clock driver 400 and the second clock driver 410. Splitting the output control clock FCLK_DLL_DQ to output the first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b, and using the split first control clock FCLK_DLL_DQ2 and the second control clock FCLK_DLL_DQ2b. Controls that the internal data FDO is transmitted to the output node OUT_NODE.

The data driving unit 466 among the components of the data output unit 460 always outputs whether the data contained in the output node OUT_NODE is the first internal data RDO or the second internal data FDO. The operation of driving the data loaded in the node OUT_NODE to the predetermined data pad DQ is performed.

That is, among the components of the data output unit 460, the first data transfer unit 462 and the data driving unit 466 may include the first internal data RDO-'D1', 'D3', and 'D5' in the drawing. Performs the operation (①) of passing 'D7'-to the output node (OUT_NODE).

Similarly, among the components of the data output unit 460, the second data transfer unit 464 and the data driving unit 466 may include the second internal data FDO-'D2', 'D4', and 'D6' in the drawing. Performs the operation (②) of transmitting 'D8'-to the output node OUT_NODE.

As described above, when the first and second embodiments of the present invention are applied, the first delay locked loop clock RCLK and the phases having opposite phases and having a duty ratio of 50 to 50 do not overlap activation intervals. Power supplied to the semiconductor memory device by generating the first output control clock RCLK_DLL_DQ and the second output control clock FCLK_DLL_DQ corresponding to the second delay locked loop clock FCLK and using only the data output device of the semiconductor memory device. Even in this low power supply (Low VDD) state, data can be output stably.

That is, the first output control clock RCLK_DLL_DQ and the second output control clock FCLK_DLL_DQ are not used simultaneously in the internal circuit and the data output device of the semiconductor memory device as in the prior art.

Accordingly, the first output control clock RCLK_DLL_DQ and the second output control clock FCLK_DLL_DQ have phases opposite to each other like the first delay locked loop clock RCLK and the second delay locked loop clock FCLK and have a duty ratio of 50. Maintaining 50, the activation intervals do not overlap each other.

This is a circuit for preventing the activation section of the first output control clock RCLK_DLL_DQ and the second output control clock FCLK_DLL_DQ from overlapping in the data output device of the semiconductor memory device. 120 and the second activation section adjusting unit 125 may be omitted. Accordingly, even when the power supplied to the semiconductor memory device is in a low power supply state (Low VDD), the data output device of the semiconductor memory device Can work stably.

In addition, the circuit inside the data output device of the semiconductor memory device is simplified because the internal data (from the first delay locked loop clock RCLK and the second delay locked loop clock FCLK output from the delay locked loop circuit DLL) is stored. This means that the data path passed to the exit of RDO and FDO is reduced. Therefore, the replica circuit is used to model and use the data path inside the delay locked loop (DLL). This means fewer miss matches between the actual data paths. That is, the tDQSCK value can be reduced.

The present invention described above is not limited to the above-described embodiments and drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

1 is a circuit diagram showing a data output apparatus of a semiconductor memory device according to the prior art.

2 is a timing diagram illustrating an operation of a data output apparatus of a semiconductor memory device according to the related art shown in FIG. 1.

3A is a circuit diagram showing a data output device of a semiconductor memory device according to the first embodiment of the present invention.

FIG. 3B is a timing diagram showing the operation of the data output apparatus of the semiconductor memory device according to the first embodiment of the present invention shown in FIG. 3A.

4A is a circuit diagram showing a data output device of a semiconductor memory device according to the second embodiment of the present invention.

FIG. 4B is a timing diagram showing the operation of the data output apparatus of the semiconductor memory device according to the second embodiment of the present invention shown in FIG. 4A.

* Explanation of symbols for main parts of the drawings

100: first clock driving unit 105: second clock driving unit

110: third clock drive unit 115: fourth clock drive unit

120: first activation section adjusting unit 125: second activation section adjusting unit

130: first split portion 135: second split portion

140: first transfer control unit 145: second transfer control unit

150: data driving unit 170: internal circuit

300, 400: first clock driving unit 310, 410: second clock driving unit

360, 460: data output unit 370, 470: internal circuit

362, 462: first data transfer unit 364, 464: second data transfer unit

366, 366: data driving unit

Claims (22)

  1. First clock driving means for driving the first delay locked loop clock and the second delay locked loop clock, respectively;
    An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means;
    Second clock driving means for driving the first delay locked loop clock and the second delay locked loop clock to output each of the first delay control loop clock and the second delay control loop clock; And
    Data output means for applying first internal data to the data pad in response to the first output control clock and applying the second internal data to the data pad in response to the second output control clock.
    A semiconductor memory device having a.
  2. The method of claim 1,
    The internal circuit,
    Perform the predetermined internal operation in response to an output clock of the first clock driving means in an activation section of a drive control signal,
    And the predetermined internal operation is not performed regardless of the output clock of the first clock driving means in the inactivation section of the drive control signal.
  3. The method of claim 1,
    The data output means,
    In response to the first output control clock in the activation period of the first command signal, the first internal data is applied to the data pad as the output data,
    And wherein the first internal data is not applied to the data pad regardless of the first output control clock during the inactivation period of the first command signal.
  4. The method of claim 3,
    The data output means,
    In response to the second output control clock in the activation period of the second command signal, the second internal data is applied to the data pad as the output data,
    And wherein the second internal data is not applied to the data pad regardless of the second output control clock during the inactivation period of the second command signal.
  5. The method of claim 1,
    The data output means,
    A first data transfer unit configured to transfer the first internal data to an output node in response to a first command signal and the first output control clock;
    A second data transfer unit for transferring the second internal data to the output node in response to a second command signal and the second output control clock; And
    And a data driving unit for driving data loaded on the output node to the data pad.
  6. The method of claim 5,
    The first data transfer unit,
    The first output control clock is received in the activation period of the first command signal for splitting the first control clock corresponding to the first edge of the first output control clock and the second control clock corresponding to the second edge. Split portion;
    And a transfer control unit for controlling the transfer of the first internal data to the output node in response to the first and second control clocks.
  7. The method of claim 5,
    The second data transfer unit,
    The second output control clock is inputted in the activation period of the second command signal to split the first control clock corresponding to the first edge of the second output control clock and the second control clock corresponding to the second edge. Split portion;
    And a transfer control unit for controlling the transfer of the second internal data to the output node in response to the first and second control clocks.
  8. First clock driving means for driving the first delay locked loop clock and the second delay locked loop clock respectively in the activation section of the drive control signal;
    An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means;
    Second clock driving means for driving the first delay locked loop clock and the second delay locked loop clock to output as a first output control clock and a second output control clock in an activation period of a command signal; And
    Data output for applying first internal data to the data pad in response to the first output control clock and applying the second internal data to the data pad in response to the second output control clock. Way
    A semiconductor memory device having a.
  9. The method of claim 8,
    The data output means,
    A first data transfer unit for transferring the first internal data to an output node in response to the first output control clock;
    A second data transfer unit for transferring the second internal data to the output node in response to the second output control clock; And
    And a data driving unit for driving data loaded on the output node to the data pad.
  10. The method of claim 9,
    The first data transfer unit,
    A split unit configured to receive the first output control clock and split the first output control clock into a first control clock corresponding to a first edge of the first output control clock and a second control clock corresponding to a second edge;
    And a transfer control unit for controlling the transfer of the first internal data to the output node in response to the first and second control clocks.
  11. The method of claim 9,
    The second data transfer unit,
    A split unit configured to receive the second output control clock and split the first control clock corresponding to the first edge of the second output control clock and the second control clock corresponding to the second edge;
    And a transfer control unit for controlling the transfer of the second internal data to the output node in response to the first and second control clocks.
  12. First clock driving means for driving each of the right and second clocks;
    An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means;
    Second clock driving means for driving the positive clock and the subclock, respectively, and outputting them as a constant output control clock and a sub output control clock; And
    Data output means for applying first internal data to the data pad in response to the positive output control clock and applying the second internal data to the data pad in response to the sub output control clock.
    A semiconductor memory device having a.
  13. The method of claim 12,
    The internal circuit,
    Perform the predetermined internal operation in response to an output clock of the first clock driving means in an activation section of a drive control signal,
    And the predetermined internal operation is not performed regardless of the output clock of the first clock driving means in the inactivation section of the driving control signal.
  14. The method of claim 12,
    The data output means,
    The first internal data is applied to the data pad as the output data in response to the constant output control clock in the activation period of the first command signal,
    And wherein the first internal data is not applied to the data pad regardless of the constant output control clock during the inactivation period of the first command signal.
  15. The method of claim 14,
    The data output means,
    In response to the sub-output control clock in the activation period of the second command signal, the second internal data is applied to the data pad as the output data,
    And wherein the second internal data is not applied to the data pad regardless of the sub-output control clock during the inactivation period of the second command signal.
  16. The method of claim 12,
    The data output means,
    A first data transfer unit for transferring the first internal data to an output node in response to a first command signal and the positive output control clock;
    A second data transfer unit for transferring the second internal data to the output node in response to a second command signal and the sub-output control clock; And
    And a data driving unit for driving data loaded on the output node to the data pad.
  17. The method of claim 16,
    The first data transfer unit,
    A split unit for receiving the constant output control clock in the activation period of the first command signal and splitting the first control clock corresponding to the first edge of the constant output control clock and the second control clock corresponding to the second edge. ;
    And a transfer control unit for controlling the transfer of the first internal data to the output node in response to the first and second control clocks.
  18. The method of claim 16,
    The second data transfer unit,
    A split unit for receiving the sub output control clock in the activation period of the second command signal and splitting the sub output control clock into a first control clock corresponding to the first edge of the sub output control clock and a second control clock corresponding to the second edge. ;
    And a transfer control unit for controlling the transfer of the second internal data to the output node in response to the first and second control clocks.
  19. First clock driving means for driving the positive clock and the subclock respectively in the activation section of the drive control signal;
    An internal circuit for performing a predetermined internal operation in response to an output clock of the first clock driving means;
    Second clock driving means for driving the positive clock and the sub-clock in the activation period of the command signal and outputting the positive clock and the sub-output control clock respectively; And
    Data output means for applying first internal data to the data pad in response to the positive output control clock and applying the second internal data to the data pad in response to the sub output control clock.
    A semiconductor memory device having a.
  20. The method of claim 19,
    The data output means,
    A first data transfer unit for transferring the first internal data to an output node in response to the constant output control clock;
    A second data transfer unit for transferring the second internal data to the output node in response to the sub-output control clock; And
    And a data driving unit for driving data loaded on the output node to the data pad.
  21. The method of claim 20,
    The first data transfer unit,
    A split unit configured to receive the constant output control clock and split the control signal into a first control clock corresponding to a first edge of the constant output control clock and a second control clock corresponding to a second edge;
    And a transfer control unit for controlling the transfer of the first internal data to the output node in response to the first and second control clocks.
  22. The method of claim 20,
    The second data transfer unit,
    A split unit configured to receive the sub output control clock and split the sub output control clock into a first control clock corresponding to a first edge of the sub output control clock and a second control clock corresponding to a second edge;
    And a transfer control unit for controlling the transfer of the second internal data to the output node in response to the first and second control clocks.
KR1020080034608A 2008-04-15 2008-04-15 Semiconductor memory device KR100922881B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050041613A (en) * 2003-10-31 2005-05-04 주식회사 하이닉스반도체 Data output control circuit
KR20060054610A (en) * 2004-11-15 2006-05-23 주식회사 하이닉스반도체 Data output circuit for memory device
KR20060075060A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Clock generation apparatus in semiconductor memory device and its method
KR20070115056A (en) * 2006-05-30 2007-12-05 주식회사 하이닉스반도체 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050041613A (en) * 2003-10-31 2005-05-04 주식회사 하이닉스반도체 Data output control circuit
KR20060054610A (en) * 2004-11-15 2006-05-23 주식회사 하이닉스반도체 Data output circuit for memory device
KR20060075060A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Clock generation apparatus in semiconductor memory device and its method
KR20070115056A (en) * 2006-05-30 2007-12-05 주식회사 하이닉스반도체 Semiconductor device

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