KR20050097700A - Register controlled delay locked loop with low-power - Google Patents

Abstract

The present invention provides an external clock signal, which is a reference clock inputted from an external device, of a phase of an internal clock signal required for data transmission in a synchronous semiconductor memory device such as DDR SDRAM (Double Date Rate Synchronous DRAM). The present invention relates to a delay locked loop (DLL) circuit for accurately synchronizing and locking a power supply by a delay locked loop circuit after the internal clock signal is locked in synchronization with an external clock signal. The present invention relates to a low power register controlled delay locked loop circuit (Register Controlled DLL) that can reduce consumption.

In the delay lock loop circuit of the present invention, a delay unit for delaying an external clock signal input from an external device and a delay signal by the delay unit are controlled by inputting an external clock signal and a clock signal delayed by the delay unit. The feedback unit and the delayed clock signal is locked in synchronization with the external clock signal, the operation of the feedback unit is interrupted, and the feedback control unit for periodically driving the feedback unit.

Description

Low power register controlled delay locked loop circuit {REGISTER CONTROLLED DELAY LOCKED LOOP WITH LOW-POWER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop (DLL) of a semiconductor memory device, and more particularly, a clock signal delayed through a delay locked loop circuit including a register is synchronized with an external clock signal. The present invention relates to a low power register controlled delay locked loop (Register Controlled DLL) circuit which can reduce power consumption by a delay locked loop circuit after being locked.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using a fixed internal clock signal in synchronization with a reference clock signal input from an external device such as a memory controller. Do this. This is because the time synchronization between the reference clock signal and the data is very important for stable data transfer between the memory and the memory controller. In other words, for reliable transmission of data, data must be accurately located at the edge or center of the clock by back-compensating the time that the data is loaded on the bus from the clock of each component transmitting the data. Because. The clock synchronizing circuit which performs this role includes a phase locked loop (PLL) circuit and a delay locked loop circuit. When the frequency of the external clock signal and the frequency of the internal clock signal are different, a frequency multiplication function is used. Phase locked loop circuit is mainly used. When the frequency of the external clock signal and the frequency of the internal clock signal are the same, most of the delay locked loop circuits are used. The delay lock loop circuit generates an internal clock signal by compensating for a clock delay component generated in the process of outputting the clock signal to the data output terminal of the semiconductor memory device, thereby synchronizing the clock signal used for the final data input / output with the external clock signal. To be. Since the delay locked loop circuit has less noise than the phase locked loop circuit and can be implemented with a small area, it is common to use a delay locked loop circuit as a synchronous circuit in a semiconductor memory device. Among them, the register has a register that can store the most recent fixed delay value, and when the power is cut off, the fixed delay value is stored in the register and when the power is applied again, the fixed delay value stored in the register is loaded and used to fix the clock. Register controlled delayed loop circuits (Register Controlled DLL), which can reduce the time required for initial clock lock, are the most widely used.

1 is a block diagram of a conventional general register controlled delay locked loop circuit used in a semiconductor memory device. As shown in FIG. 1, the delay locked loop circuit is largely composed of a delay unit 100, a delay reproduction unit 102, a phase detector 104, a delay control unit 106 and a register unit 108. do.

The delay unit 100 includes a plurality of delay cells and outputs a delayed clock signal dCLK obtained by delaying the external clock signal CLK, which is a reference clock input from an external device, for a predetermined time. At this time, the delay amount by the delay unit 100 is controlled by the delay control unit 106, which is fed back through the external clock signal CLK and the delay regeneration unit 102 (dfCLK). Is determined by the phase difference PDIFF.

The delay regeneration unit 102 is a circuit configured to have a delay condition identical to an actual clock path (also called tSAC path) in which the delay clock signal dCLK is transmitted to the final data output terminal of the semiconductor memory device. It is called. The delayed clock signal dfCLK reproduced and fed back through the delay regenerator 102 has the same phase as the clock signal transmitted to the final data output terminal of the semiconductor memory device.

The phase detector 104 compares the phase of the external clock signal CLK and the delayed clock signal dfCLK fed back from the delay regenerator 102 and inputs the phase difference PDIFF to the delay controller 106. 106 determines the increase / decrease (UP / DN) of the delay amount of the delay unit 100 according to the phase detection result PDIFF input from the phase detection unit 104, and inputs the result to the register unit 108. do. The register unit 108 includes a plurality of shift registers, and controls the delay amount of the delay unit 100 according to the delay amount increase / decrease information UP / DN from the delay control unit 106. In addition, the register unit 108 stores the final fixed delay value in the register when the power is cut off, and when the power is applied again, the register unit 108 first fixes the delay clock signal dCLK by using the fixed delay value stored in the register. The time required for clock fixing can be reduced.

Through the above configuration, the delay lock loop circuit fixes the delay clock signal dCLK such that the phase of the clock signal used for the final data input / output terminal of the memory device is synchronized with the external clock signal CLK. That is, the delay time generated in the process of transferring the clock signal dCLK delayed by the delay lock loop circuit to the final data input / output terminal is reproduced and fed back through the delay reproducing unit 102, and the external clock signal CLK is fed back. By controlling the delay amount of the delay unit 100 by using the phase difference of the delayed clock signal dfCLK to fix the delayed clock signal dCLK, the phase of the clock signal used for the final data input / output is external clock signal ECLK. To be motivated.

On the other hand, when the delay clock signal dCLK is fixed in the delay lock loop circuit as described above, the phase detector 104, the delay regeneration unit 102, the delay control unit 106, and the register unit 108 are fixed clock signals ( No longer plays a role except dCLK) is distorted by external noise. Nevertheless, the conventional delay locked loop circuit consumes unnecessary power by continuously supplying power to the phase detector 104, the delay regenerator 102, and the delay controller 106 even after the delayed clock signal is fixed.

An object of the present invention is to provide a low power delay locked loop circuit which can reduce power consumed by a delay locked loop circuit while maintaining a stable supply of a fixed clock signal in a delay locked loop circuit of a semiconductor memory device.

The delay lock loop circuit of the present invention uses a delay unit for delaying an external clock signal input from an external device and a feedback unit for controlling the delay amount of the delay unit by receiving an external clock signal and a clock signal delayed by the delay unit. When the signal is fixed, the operation of the feedback unit is interrupted, and then it is composed of a feedback control unit for periodically driving the feedback unit.

(Example)

FIG. 2 is a detailed block diagram showing an embodiment of a low power register controlled delay locked loop circuit applied to a synchronous semiconductor memory device such as DDR SDRAM in the present invention. Referring to FIG. 2, the low power register controlled delay locked loop circuit of the present invention may be largely divided into a delay unit 200, a feedback unit 210, and a feedback control unit 220.

The delay unit 200 outputs a delayed clock signal dCLK obtained by delaying the external clock signal CLK, which is a reference clock input from an external device, for a predetermined time according to the register values from the feedback unit 210.

As shown in FIG. 2, the delay unit 200 is divided into a delay chain 202, an interpolator 204, a duty cycle corrector DCC, and an external clock signal CLK. The clock is fixed by delay.

The delay chain 202 is composed of a plurality of delay cells, and delays the external clock signal CLK through the delay cells. On the other hand, the number of delay cells to be used for the delay is determined according to the register values from the feedback unit 210, the delay operation by the delay chain 202 is made of a long time interval of the unit of the clock rough lock (Coarse Lock ) Is performed.

The interpolator 204 receives the delay cell information and the delayed clock signal used for the delay of the external clock signal from the delay chain 202, and sets the external clock signal CLK according to the register value from the feedback unit 210. Delay the car. Since the delay operation by the interpolator 204 is made in a small time unit compared to the delay operation by the delay chain 202, detailed clock lock is possible.

The duty compensator 206 outputs a delayed clock signal dCLK obtained by correcting the duty of the clock signal dCLK 'input from the interpolator 204 at a ratio of 50:50. 3 is a block diagram of a duty corrector. Referring to FIG. 3, generally, the duty compensator 206 is a duty amplifier (DCC_AMP) 302, a duty detector 304, an analog / digital converter 306, and a register 308 and a digital / analog converter 310. It is composed. In addition, the duty detector 304 is generally implemented using a charge pump. The use of the duty compensator in the delay locked loop circuit performs data transmission in synchronization with both the rising edge and the falling edge of the clock signal in the case of DDR SDRAM. This is because the interval between the high section and the low section must match. To this end, a duty compensator is further included at the front end or the rear end of the delay locked loop circuit. The duty compensator as described above is a general technique that can be known to anyone having ordinary skill in the art, so detailed description thereof will be omitted.

The feedback unit 210 controls the delay amount of the delay unit 200 by using the phase difference PDIFF of the clock signal dCLK delayed by the delay unit 200 and the external clock signal CLK, and delay regenerator. 211), phase detector 212, up / down generator 213, mode controller 214, mux circuit 215, first register 216 and The second register section 217 is configured.

The delay regenerator 211 delays the delay clock signal dCLK input from the delay unit 200 by a delay time generated on the actual clock path and feeds it back to the phase detector 212. The delay regenerator 211 is a circuit configured such that the delay clock signal dCLK from the delay unit 200 has the same delay condition as the actual clock path tSAC Path transmitted to the final data output terminal of the semiconductor memory device. That is, the clock signal dCLK delayed by the delay lock loop circuit passes through a plurality of clock drivers and buffers in the process of being transferred to the final data output terminal of the memory. In this process, another delay with respect to the delay clock signal dCLK Will occur. Delay regenerator 211 is designed to have a delay time equal to the delay time on the actual clock path to compensate for this delay. On the other hand, the operation of the delay regenerator 211 is enabled or disabled in response to the feedback control signal STB_FB from the feedback control unit 220.

The phase detector 212 detects the phase difference PDIFF between the two clock signals by comparing the phase of the external clock signal CLK and the delayed clock signal dfCLK fed back by the delay regenerator.

The mode controller 214 inputs the phase difference information PDIFF from the phase detector 212 to determine whether the delay unit 200 performs approximate clock fixing through the delay chain 202 or the interpolator 204. Generates a mode control signal (MODE) on whether or not to perform detailed clock fixation.

The up / down generator 213 determines the amount of delay to be performed by the delay chain 202 or the interpolator 204 using the mode control signal MODE and the phase difference information PDIFF. That is, when the phase of the external clock signal CLK is earlier than the phase of the fed back delayed clock signal dfCLK, the up / down generator 213 increases the amount of delay caused by the delay unit 200 and vice versa. If the phase of the delayed clock signal dfCLK is earlier than the phase of the external clock signal CLK, the up / down generator 213 reduces the delay amount DN by the delay unit 200 (DN). In addition, the operation of the up / down generator 213 is enabled or disabled in response to the feedback control signal STB_FB from the feedback control unit 220.

The mux circuit 215 adjusts the delay amount of the delay chain 202 in response to the mode control signal MODE from the mode controller 214 and the up / down information UP / DN from the up / down generator 213. The first delay control signal E_UP / DN or O_UP / DN to be controlled is input to the first register (aka TAP register 216), or the second delay control signal for controlling the delay amount of the interpolator 204 ( W_UP / DN is input to the second register (aka I register, 217).

 The first register 216 or the second register 217 respectively controls the delay amount of the delay chain 202 or the interpolator 204 in response to the delay control signal from the mux circuit 215, and stores the delay values. do.

When the delay clock signal dCLK is fixed by the delay locked loop circuit, the feedback controller 220 disables the operation of the feedback unit 210 to reduce power consumption of the delay locked loop circuit. Then, by periodically enabling the feedback unit 210 and re-driving, the fixed clock signal is updated. More specifically, the feedback control unit 210 of the present invention disables the operation of the feedback unit 210 by using the reset signal DLL_reset of the delay locked loop circuit, and CBR (CAS Before RAS) which is an internal command of the semiconductor memory device. In response to the signal), the operation of the disabled feedback unit 210 is restarted. The CBR (CAS Before RAS) signal is a column address strobe (CAS) signal, which is a read / write command in DRAM, than a row address strobe (RAS) signal, which is an active command. When applied first, it is a signal that is used for periodic refresh operations in DRAM.

4 is a block diagram showing an embodiment of a feedback control unit in the present invention, Figure 5 is a waveform diagram showing the operation of the feedback control unit shown in FIG. As shown in FIG. 4, the feedback control unit 220 includes two counters 402 and 404 and a feedback control signal generator 406. Hereinafter, the operation of the feedback controller used in the present invention will be described in detail with reference to FIGS. 4 and 5.

The first counter 402 of the feedback control unit 220 performs a predetermined counter operation in response to the reset signal DLL_reset of the delay locked loop circuit input from the outside. In general, the delay clock signal dCLK is fixed after a reset signal DLL_reset of the delay locked loop circuit is applied in the register controlled delay locked loop circuit and about 200 cycles have passed. Accordingly, as shown in FIG. 5, the first counter 402 starts the counter operation at the time when the reset signal DLL_reset of the delay locked loop circuit is applied (A in FIG. 5), and 200 cycles have elapsed (B in FIG. 5). ), The first feedback blocking signal DIS_FB1 is toggled high and input to the feedback control signal generator 406.

After the delay clock signal dCLK of the delay locked loop circuit is fixed, the second counter 404 performs a counter operation in response to a CBR signal, which is an internal command of a periodically generated DRAM. The second counter 404 starts the counter operation at the time when the CBR signal is applied (C of FIG. 5), and when 64 cycles elapse (D of FIG. 5), toggles the second feedback blocking signal DIS_FB2 high. Input to feedback control signal generator 406.

 The feedback control signal generator 406 responds to the first feedback blocking signal DIS_FB1 and the CBR signal from the first counter 402 and the second feedback blocking signal DIS_FB2 from the second counter 404. The feedback control signal STB_FB for controlling the operation of the controller 210 is generated. That is, the feedback control signal generator 406 disables the operation of the feedback unit 210 when the first feedback blocking signal DIS_FB1 is applied, and enables the feedback unit 210 to be re-driven in response to the CBR signal. After the CBR signal is applied, the feedback control signal STB_FB is generated to disable the operation of the feedback unit 210 in response to the second feedback blocking signal DIS_FB2.

Meanwhile, as mentioned above, the feedback control signal STB_FB generated by the feedback control unit 220 is applied to the delay regenerator 211 and the up / down generator 213 of the feedback unit 210 so that the delay regenerator 211 The operation of the up / down generator 213 is controlled. If the operations of the delay regenerator 211 and the up / down generator 213 are disabled, the feedback unit 210 does not perform an operation for controlling the delay amount of the delay unit 200. Therefore, the power consumed by the delay locked loop circuit can be reduced. In addition, the feedback control signal STB_FB periodically enables the disabled delay regenerator 211 and the up / down generator 213 and restarts the delayed clock for a predetermined period. Meanwhile, the feedback control signal STB_FB of the present invention is applied to the duty compensator 206 included in the delay unit 200 to operate the duty compensator 206 similarly to the delay regenerator 211 and the up / down generator 213. Can also be controlled. However, when the duty cycle corrector 206 is disabled by the feedback control signal STB_FB, the duty cycle correction operation of the delayed clock signal dCLK 'is stopped, and the clock signal dCLK' input from the interpolator 204 is stopped. Bypass the output.

 In the above, the configuration and operation of the low-power register controlled delay locked loop circuit according to the present invention have been described in detail through the above-described embodiments, but these are merely exemplary, and a person of ordinary skill in the art does not depart from the spirit of the present invention. It will be appreciated that various applications and modifications can be made without departing from the scope of the present invention.

As described above, the low power register controlled delay locked loop circuit of the present invention can maintain the stable clock supply while reducing power consumption by the delay locked loop circuit after the delay clock signal is fixed.

1 is a block diagram of a conventional general register controlled delay locked loop circuit used in DDR SDRAM.

2 is a block diagram showing an embodiment of a low power register controlled delay locked loop circuit of the present invention.

3 is a block diagram illustrating a general configuration of a duty compensator in FIG. 2.

4 is a block diagram illustrating an embodiment of a feedback controller in the present invention shown in FIG. 2.

5 is a waveform diagram illustrating in detail the operation of the feedback controller shown in FIG. 4.

* Explanation of symbols on the main parts of the drawings

200: delay unit 202: delay chain

204: Interpolator

206: Duty Cycle Corrector

210: feedback unit 211: delay circuit (Replica Circuit)

212 Phase Detector

213: UP / DN Generator

214: mode controller 215: mux circuit (MUX)

216: first register 217: second register

220: feedback control unit 402: first counter

404: second counter 406: feedback control signal generator

Claims (14)

In a register controlled delay locked loop circuit of a semiconductor memory device, A delay unit delaying an external clock signal input from an external device; A feedback unit configured to control the delay amount of the delay unit by inputting the external clock signal and the clock signal delayed by the delay unit; And And a feedback controller configured to disable operation of the feedback unit when the delayed clock signal is locked in synchronization with the external clock signal, and thereafter, enable the feedback unit to periodically drive the feedback unit. Loop circuit. The method of claim 1, The feedback control unit disables the operation of the feedback unit after a predetermined time elapses after the reset signal of the delay locked loop circuit is applied from the outside, and in response to the CBR (CAS Before RAS) refresh signal of the semiconductor memory device. And enabling the feedback unit and disabling the feedback unit when a predetermined time elapses after the CBR refresh signal is applied. The method of claim 2, The feedback control unit may include a first counter that performs a counter operation for a predetermined cycle at the time when the reset signal is applied; A second counter that performs a counter operation for a predetermined cycle when the CBR refresh signal is applied; And And a feedback control signal generator configured to control an operation of the feedback unit in response to the CBR refresh signal and inputs from the first counter and the second counter. The method of claim 1, The delay unit may include a delay chain configured to delay the external clock signal in response to a first control signal from the feedback unit; And And an interpolator interpolating a clock signal delayed by the delay chain in response to a second control signal from the feedback unit. The delay chain is operated in a first delay mode that performs clock lock through coarse clock delay, and the interpolator operates in a second delay mode that performs clock lock through detailed clock delay. Delayed fixed loop circuit. The method of claim 4, wherein And the delay chain comprises a plurality of delay cells. The method of claim 4, wherein And the delay unit further comprises a duty compensator for correcting the duty of the delayed clock signal. The method of claim 6, And said duty compensator is disabled or enabled by said feedback control unit. The method of claim 7, wherein And if the duty compensator is disabled, bypasses the clock signal from the interpolator. The method of claim 1, The feedback unit includes a delay regenerator for delaying the delay clock signal for a predetermined time; A phase detector for detecting a phase difference between the clock signal reproduced by the delay regenerator and the external clock signal; And a delay controller for controlling a delay amount of the delay unit in response to a phase difference detection result from the phase detector. The method of claim 9, And the delay regenerator is a circuit for reproducing a delay time in a process in which an output clock signal of the delay locked loop circuit is transmitted to a data input / output terminal of the semiconductor memory device. The method of claim 9, And the delay regenerator is enabled or disabled by the feedback control unit. The method of claim 9, The delay controller may include a first register controlling a delay amount of the delay chain; A second register for controlling a delay amount of the interpolator; A mode controller configured to determine a delay mode of the delay unit in response to the phase difference detection result; An up / down generator configured to control the increase / decrease of the delay amount by the delay unit in response to the phase difference detection result and the delay mode information from the mode controller; And And a mux circuit for transferring a delay amount from the up / down generator to the first register or the second register in response to the delay mode information from the mode controller. The method of claim 12, And the operation of the up / down generator is enabled or disabled by the feedback control unit. A register control type which is applied to a semiconductor memory device and includes a delay unit for delaying a clock signal input from an external device and a feedback unit for controlling a delay amount of the delay unit by using a delay clock signal from the delay unit. In the control method of the delay locked loop circuit, Disabling an operation of the feedback unit when a predetermined time elapses after the reset signal is applied to the delay locked loop circuit; A second step of enabling the operation of the feedback unit disabled in the first step when the semiconductor memory device operates in a CBR (CAS Before RAS) refresh mode; And a third step of disabling the operation of the feedback unit, enabled in the second step, after a predetermined time has passed since the semiconductor memory device enters the CBR refresh mode. Control method of fixed loop circuit.