CN109116958A - A kind of production method, circuit and the server of chip reset signal - Google Patents
A kind of production method, circuit and the server of chip reset signal Download PDFInfo
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- CN109116958A CN109116958A CN201810994315.0A CN201810994315A CN109116958A CN 109116958 A CN109116958 A CN 109116958A CN 201810994315 A CN201810994315 A CN 201810994315A CN 109116958 A CN109116958 A CN 109116958A
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- reset signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
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- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention discloses production method, circuit and the servers of a kind of chip reset signal, belong to server circuit design field.The embodiment of the present invention exports first waveform by that will control chip；The first waveform is postponed into the second waveform of time acquisition；Second waveform is subjected to inverse and obtains third waveform；Third waveform and first waveform carry out or operation obtains the 4th waveform as chip reset pin input waveform, and the embodiment of the present invention can receive a variety of pulse reset signals, improve the ability of reply input signal exception.Through the embodiment of the present invention, it breaks down even if controlling input pulse signal, the module extension for such as issuing low pulse signal is dead, and input signal is constantly in second segment low level, high level can also be become by chip reseting pin by finally entering, it is ensured that chip is by normal reset.The embodiment of the present invention can simplify control flow, save each control unit pin resource.
Description
Technical field
The present invention relates to server circuit design fields.
Background technique
I2C switch chip and IO expander chip are easily grasped with its more small and exquisite specification and more at present
It is widely applied in server as method, the extension of I2C signal can be realized by the device and makes up GPIO pin number
The deficiency of amount.
For I2C switch chip and IO expander chip sometimes for carrying out reset operation.Currently, existing
The hardware circuit of I2C switch chip and IO expander chip reset is by harmonizing processor chip directly chip
Reseting pin (reset pin) is set to low level, resets to realize to I2C switch chip etc..
But there are certain risks in existing design, after reseting pin (reset pin) is set to low level, if IC
After chip etc. resets, reseting pin cannot become high level, cause chip to be hung dead, can not work normally.
Summary of the invention
The present invention is after solving chip reset, and reseting pin cannot become high level, cause chip to hang dead technology and ask
Topic.For this purpose, the present invention provides production method, circuit and the server of a kind of chip reset signal, it, which has, can guarantee that chip is multiple
Reseting pin becomes high level behind position, prevents chip from hanging dead advantage.
To achieve the goals above, the present invention adopts the following technical scheme that.
On the one hand the embodiment of the present invention provides a kind of production method of chip reset signal, comprise the steps of,
Export first waveform；
The first waveform is postponed into the second waveform of time acquisition；
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform；
The first waveform is selected from one kind of low impulse waveform or high impulse waveform, the low impulse waveform start-up portion
It is high level comprising first segment, second segment is low level, the waveform that third section is high level；The high impulse waveform start-up portion
It is low level comprising first segment, second segment is high level, third section is low level waveform.
Preferably, low impulse waveform does not include the waveform portion that third section is high level.
The another aspect of the embodiment of the present invention provides a kind of chip reset method, comprising by above the 4th waveform
Input chip reset pin.
The another aspect of the embodiment of the present invention provides a kind of generation circuit of chip reset signal, includes:
One delay chip, a NOT gate and one or door, the input terminal connection of the output end NAND gate of the delay chip are described
The input terminal of the output end of NOT gate and delay chip with or door connect.
The another aspect of the embodiment of the present invention provides a kind of server, the generation circuit comprising the chip reset signal,
The input terminal of the delay chip is connect with a control chip, and described or door output end is connect with the reseting pin of a chip.
The embodiment of the present invention the utility model has the advantages that
The embodiment of the present invention can receive a variety of pulse reset signals, improve the ability of reply input signal exception.
Through the embodiment of the present invention, even if control input pulse signal breaks down, the module of low pulse signal is such as issued
It hangs extremely, input signal is constantly in second segment low level, and high level can also be become by chip reseting pin by finally entering, really
Chip is protected by normal reset.
In the server, chip reset generally instructs control chip to be controlled by baseboard management controller chip, this hair
Bright embodiment can simplify control flow, save each control unit pin resource.
Detailed description of the invention
Fig. 1 is the pulsed logic figure of embodiment 1.
Fig. 2 is the pulsed logic figure of embodiment 2.
Fig. 3 is the pulsed logic figure of embodiment 3.
Fig. 4 is the pulsed logic figure of embodiment 4.
Fig. 5 is the circuit connection diagram of embodiment 5.
In figure, A. first waveform, the second waveform of B., the 4th waveform of Z., 1. delay chips, 2. NOT gates, 3. or door.
Specific embodiment
The invention will be further described with embodiment with reference to the accompanying drawing.
Embodiment 1.
The production method of chip reset signal as shown in Figure 1, comprises the steps of,
Export first waveform；The first waveform include first segment be high level, second segment is low level, third Duan Weigao electricity
Flat waveform.
The first waveform is postponed into the second waveform of time acquisition；
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform.The 4th waveform that the present embodiment obtains meets multiple
Digit wave form requirement.
Embodiment 2.
The production method of chip reset signal as shown in Figure 2, comprises the steps of,
Export first waveform；The first waveform include first segment be high level, second segment is low level, third Duan Weigao electricity
Flat waveform.
The first waveform is postponed into the second waveform of time acquisition；The second waveform delay time was more than the in the present embodiment
Two sections of waveform durations.
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform.The 4th waveform that the present embodiment obtains meets multiple
Digit wave form requirement, and only one reset wave, avoid resetting.
Embodiment 3.
The production method of chip reset signal as shown in Figure 3, comprises the steps of,
Export first waveform；The first waveform be first segment be high level, second segment is low level waveform.The present embodiment
It is high level not comprising third section.
The first waveform is postponed into the second waveform of time acquisition；
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform.The 4th waveform that the present embodiment obtains meets multiple
Digit wave form requirement.
Embodiment 4.
The production method of chip reset signal as shown in Figure 4, comprises the steps of,
Export first waveform；The first waveform include first segment be low level, second segment is high level, third section is low electricity
Flat waveform.
The first waveform is postponed into the second waveform of time acquisition；
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform.The 4th waveform that the present embodiment obtains meets multiple
Digit wave form requirement.
Embodiment 5.
As shown in figure 5, including the present embodiment provides a kind of generation circuit of chip reset signal:
The input terminal of one delay chip 1, a NOT gate 2 and one or door 3, the output end NAND gate 2 of the delay chip 1 connects
Connect, the input terminal of the output end of the NOT gate 2 and delay chip 1 with or door 3 connect.
The present embodiment work when, by one control chip output first waveform A be input to delay chip 1 input terminal and
Or 3 input terminal of door；First waveform A be first segment be high level, second segment is low level waveform.
By delay chip 1 by the first waveform A postpone the time obtain the second waveform B, the second waveform B from delay core
The output end of piece 1 exports；
Second waveform B is input to NOT gate 2 and carries out inverse acquisition third waveform；In the present embodiment, third waveform is the
One section is low level, the waveform that second segment is high level.
Third waveform and first waveform are input to jointly or door 4, progress or operation obtain the 4th waveform Z.The present embodiment
The 4th waveform obtained includes one section of low level and a continuous high level, meets chip reset waveform requirements.
Embodiment 6.
The embodiment of the present invention provides a kind of server, the generation circuit comprising the chip reset signal, the delay
The input terminal of chip is connect with a control chip, and described or door output end is connect with the reseting pin of a chip.
It is specially that (Complex Programmable Logic Device is answered CPLD chip that chip is controlled in the present embodiment
Miscellaneous programmable logic device).
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.
Claims (5)
1. a kind of production method of chip reset signal, which is characterized in that it comprises the steps of,
Export first waveform；
The first waveform is postponed into the second waveform of time acquisition；
Second waveform is subjected to inverse and obtains third waveform；
Third waveform and first waveform carry out or operation obtains the 4th waveform；
The first waveform is selected from one kind of low impulse waveform or high impulse waveform, and the low impulse waveform start-up portion includes the
One section is high level, second segment is low level, the waveform that third section is high level；The high impulse waveform start-up portion includes the
One section is low level, second segment is high level, third section is low level waveform.
2. the production method of chip reset signal as described in claim 1, which is characterized in that the low impulse waveform does not include
Third section is the waveform portion of high level.
3. a kind of chip reset method, which is characterized in that include by any 4th Waveform Input chip as claimed in claim 1 or 2
Reseting pin.
4. a kind of generation circuit of chip reset signal, characterized by comprising:
One delay chip, a NOT gate and one or door, the input terminal connection of the output end NAND gate of the delay chip, the NOT gate
Output end and delay chip input terminal with or door connect.
5. a kind of server, which is characterized in that the generation circuit comprising the chip reset signal, the input of the delay chip
End is connect with a control chip, and described or door output end is connect with the reseting pin of a chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810994315.0A CN109116958A (en) | 2018-08-29 | 2018-08-29 | A kind of production method, circuit and the server of chip reset signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810994315.0A CN109116958A (en) | 2018-08-29 | 2018-08-29 | A kind of production method, circuit and the server of chip reset signal |
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| CN109116958A true CN109116958A (en) | 2019-01-01 |
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| CN201810994315.0A Pending CN109116958A (en) | 2018-08-29 | 2018-08-29 | A kind of production method, circuit and the server of chip reset signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111736678A (en) * | 2020-06-12 | 2020-10-02 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
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| US20050116754A1 (en) * | 2003-11-27 | 2005-06-02 | Oki Electric Industry Co., Ltd. | Reset circuit |
| CN1898867A (en) * | 2003-12-23 | 2007-01-17 | 密克罗奇普技术公司 | Wake-up reset circuit |
| CN101938269A (en) * | 2009-06-30 | 2011-01-05 | 瑞昱半导体股份有限公司 | Starting-up reset circuit |
| CN102006039A (en) * | 2010-12-14 | 2011-04-06 | 苏州华芯微电子股份有限公司 | Reset circuit |
| CN103457586A (en) * | 2013-08-08 | 2013-12-18 | 南京熊猫电子股份有限公司 | Method for achieving electronic device shutdown zero power consumption |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
| CN107861597A (en) * | 2017-11-30 | 2018-03-30 | 无锡中微爱芯电子有限公司 | A kind of Anti-interference Design method being applied in MCU reset systems |
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2018
- 2018-08-29 CN CN201810994315.0A patent/CN109116958A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050116754A1 (en) * | 2003-11-27 | 2005-06-02 | Oki Electric Industry Co., Ltd. | Reset circuit |
| CN1898867A (en) * | 2003-12-23 | 2007-01-17 | 密克罗奇普技术公司 | Wake-up reset circuit |
| CN101938269A (en) * | 2009-06-30 | 2011-01-05 | 瑞昱半导体股份有限公司 | Starting-up reset circuit |
| CN102006039A (en) * | 2010-12-14 | 2011-04-06 | 苏州华芯微电子股份有限公司 | Reset circuit |
| CN103457586A (en) * | 2013-08-08 | 2013-12-18 | 南京熊猫电子股份有限公司 | Method for achieving electronic device shutdown zero power consumption |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
| CN107861597A (en) * | 2017-11-30 | 2018-03-30 | 无锡中微爱芯电子有限公司 | A kind of Anti-interference Design method being applied in MCU reset systems |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111736678A (en) * | 2020-06-12 | 2020-10-02 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
| CN111736678B (en) * | 2020-06-12 | 2022-06-10 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
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