CN203054679U

CN203054679U - Printed circuit board (PCB) main board

Info

Publication number: CN203054679U
Application number: CN 201220749725
Authority: CN
Inventors: 林志洪; 龚泽; 王国华; 黄金生; 王勇
Original assignee: Fujian Star Net eVideo Information Systems Co Ltd
Current assignee: Fujian Star Net eVideo Information Systems Co Ltd
Priority date: 2012-12-31
Filing date: 2012-12-31
Publication date: 2013-07-10
Anticipated expiration: 2022-12-31

Abstract

The utility model discloses a printed circuit board (PCB) main board which comprises a central processing unit (CPU) and an internal memory device electrically connected with the CPU. The type of the CPU is i.MX6Q/i.MX6D, and the topological structure of the internal memory device is of a fly-by topological structure. By the utilization of the PCB main board, the main board of a T-type topological structure which is inconvenient to process and uses the CPU which is of the i.MX6Q/i.MX6D type can be replaced by a fly-by topology which is convenient to process, through the topological structure of the internal memory device supplied by the PCB main board, the wire routing difficult of a PCB is reduced, the wire routing space of the PCB is enlarged, difficult is reduced, follow-up maintenance cost is low, and a plurality of defects mentioned in the prior art are solved.

Description

A kind of PCB mainboard

Technical field

The utility model relates to memory device, relates in particular to a kind of reduction because of the PCB mainboard of the risk of internal memory topology change generation.

Background technology

Development along with embedded system, the use of DDR3 internal memory particle is more and more, DDR3 internal memory particle is because the lifting of process technique, uses that DDR3 internal memory particle cost is low, speed is fast and low in energy consumption, and these advantages make that DDR3 internal memory particle is more and more used in embedded system.The topological mode of DDR3 internal memory particle mainly contains two kinds, and a kind of is T type topology, and a kind of is the Fly-by topology.

The internal memory particle of T type topological structure is very short from host CPU chip distance, so signal quality is fine, and the internal memory topology that therefore a lot of host CPU manufacturer's recommended clients use is T type topological structure.For the PCB mainboard that type is the CPU of i.MX6Q/i.MX6D is housed, what its memory device prior art was used is T type topological structure.But T type topology is concerning this kind PCB mainboard type of production producer, and more than PCB cabling level will promote, and production technology also will promote, and the cost of follow-up maintenance also will promote.Therefore this topology is not the making that is well suited for little producer.

The utility model content

The technical matters that the utility model mainly solves provides the PCB mainboard of a kind of CPU of the use i.MX6Q/i.MX6D type of being convenient to production and processing.

For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of PCB mainboard is provided, comprise: CPU and the memory device that is electrically connected with CPU, the type of described CPU is i.MX6Q/i.MX6D, the topological structure of described memory device is the Fly-by topological structure.

Wherein, described memory device comprises:

The PCB base plate which is provided with through hole;

A plurality of memory chips comprise a first memory chip, a plurality of middle memory chip and a tail memory chip, and described memory chip is located at the front of described PCB base plate;

With described memory chip memory power supply one to one, be provided with decoupling capacitor, described memory chip is connected with described decoupling capacitor, and described decoupling capacitor is arranged at the back side of described PCB base plate and is electrically connected with memory chip by described through hole;

First control/the address wire, one end are connected to described first memory chip, and the other end receives the control signal from the corresponding signal line;

Second control/the address wire, described first memory chip linked to each other with memory chip in the middle of, memory chip in the middle of another is linked to each other with the tail memory chip and adjacent middle memory chip is continuous, and it is isometric to connect the second instruction/address wire length of described these memory chips;

Build-out resistor is electrically connected with described tail memory chip;

And, the VTT terminal organ, it is electrically connected with described build-out resistor.

Wherein, described memory device also comprises the Memory Controller Hub that is electrically connected with CPU, is connected in the other end of the described first control/address wire.

Wherein, described memory chip is third generation ddr sdram.

Wherein, the matched impedance circuit of the differential clocks line of described memory device comprises: first resistance, its resistance are 50 ohm, and an end is connected in the positive differential clock line; Second resistance, its resistance are 50 ohm, and an end connects the other end of described first resistance, and the other end connects minus tolerance and divides clock line; And one 104 electric capacity, the one end is connected in the common node place of described first resistance, second resistance, and the other end is connected to external power supply.

The beneficial effects of the utility model are: the PCB mainboard that uses the technical program to provide, the mainboard of the T type topology that the inconvenience of using i.MX6Q/i.MX6D Type C PU can be processed is changed to the Fly-by topology of being convenient to process, the memory device topological structure that provides by the technical program, PCB cabling difficulty is reduced, it is big that cabling space becomes, difficulty reduces, and follow-up maintenance maintenance cost is low, has solved many deficiencies of mentioning in the present technology.

Description of drawings

Fig. 1 is the configuration diagram of memory device in the utility model one embodiment;

Fig. 2 is the structural representation of memory device in another embodiment of the utility model.

Label declaration:

The 100-memory device; The 101-Memory Controller Hub;

The 102-memory chip, the first memory chip of 1021-, memory chip in the middle of the 1022-, 1023-tail memory chip;

The 103-first control/address wire; The 105-second control/address wire;

The 106-VTT terminal organ.

Embodiment

By describing technology contents of the present utility model, structural attitude in detail, realized purpose and effect, give explanation below in conjunction with embodiment and conjunction with figs. are detailed.

The utility model specifically provides a kind of PCB mainboard, comprising: CPU and the memory device 100 that is electrically connected with CPU, and the type of described CPU is i.MX6Q/i.MX6D, the topological structure of described memory device is the Fly-by topological structure.

See also Fig. 1 and Fig. 2, present embodiment provides a kind of memory device, comprising: Memory Controller Hub 101, a plurality of memory chip 102, memory power supply, the first control/address wire 103, the second control/address wire 105, VTT terminal organ 106 and the build-out resistor that is connected with described VTT terminal organ 106.Described memory device also comprises the PCB base plate, the build-out resistor that it is provided with above-mentioned a plurality of memory chip 102, memory power supply, the first control/address wire 103, the second control/address wire 105, VTT terminal organ 106 and is connected with described VTT terminal organ 106.Described PCB base plate comprises front, the back side, which is provided with through hole.

In the present embodiment, a plurality of memory chips 102 are located at the front (being the internal memory particle of mentioning in the background technology) of described PCB base plate, comprise a first memory chip 1021, a plurality of middle memory chip 1022 and a tail memory chip 1023; Concrete, the particular type of memory chip 102 is third generation ddr sdram DDR3 in the embodiment shown in Fig. 1, have 4: DDR3SDRAM0～DDR3SDRAM3, wherein, first memory chip 1021 is that DDR3SDRAM0, a plurality of middle memory chip 1022 are that DDR3SDRAM1～DDR3SDRAM2 and tail memory chip 1023 are DDR3SDRAM3.

A plurality of memory power supplies connect one to one with described memory chip 102, and each memory power supply is provided with the decoupling capacitor that is electrically connected with memory chip, and described decoupling capacitor is evenly distributed on the PCB base plate of memory device.In concrete embodiment, memory chip 102 is placed in the same one side (front) of PCB base plate, and decoupling capacitor is placed on the another side (back side) of PCB base plate, and namely memory chip 102 is placed in the front of PCB base plate, and decoupling capacitor is placed at the back side.Described decoupling capacitor is electrically connected with memory chip 102 by the through hole on the PCB base plate.For can the decoupling better effects if, decoupling capacitor be just in time relative with the position of memory chip 102, so also can reduce PCB cabling difficulty to a greater extent.

First control/the address wire 103, one end are connected to described first memory chip 1021, and the other end is connected with Memory Controller Hub 101, receive the control signal from CPU.Memory Controller Hub 101 is electrically connected with CPU, and the control that CPU is sent is sent to memory chip 102 by the first control/address wire 103, and is concrete, is sent to first memory chip 1021DDR3SDRAM0.

Second control/the address wire 105, described first memory chip 1021 is linked to each other with memory chip 1022 in the middle of, memory chip 1022 in the middle of another is linked to each other with tail memory chip 1023 and adjacent middle memory chip 1022 is linked to each other, and the length of the second control/address wire 105 that connects described these memory chips 102 is isometric, realize isometric control in the data line group, solve the delay issue that exists between each memory chip 102.Memory chip 1022DDR3SDRAM1～DDR3SDRAM2 in the middle of will being sent to successively from first memory chip 1021DDR3SDRAM0 by the control that the first control/address wire 103 sends by the second control/address wire 105 like this is sent to tail memory chip 1023 again and is DDR3SDRAM3.

In a preferred embodiment, the anchoring wire that connects these memory chips reaches the shortest as far as possible.For hardware conditions such as dissimilar memory chips, CPU speed, the shortest scope of anchoring wire also is not quite similar.These need be debugged according to actual conditions, all can realize in the art.

Build-out resistor is located in the middle of CPU and the memory chip 102 in the prior art, and in the technical program, change has taken place in the position of build-out resistor, and described tail memory chip 1023 is linked to each other with build-out resistor.VTT terminal organ 106 is electrically connected with described build-out resistor.As shown in Figure 2, change the distal-most end that is located at memory chip 102 into, namely be located at after last a slice memory chip 102.

In other embodiment, described memory chip 102 can also be ddr sdram, or is second generation ddr sdram.In the concrete embodiment of the technical program, memory chip 102 will be noted the processing of bag ground, can realize the isolation of memory chip 102 and other signals and power supply.

In the present embodiment, the matched impedance circuit of the differential clocks line of described memory device comprises: first resistance, its resistance are 50 ohm, and an end is connected in the positive differential clock line; Second resistance, its resistance are 50 ohm, and an end connects the other end of described first resistance, and the other end connects minus tolerance and divides clock line; And one 104 electric capacity, the one end is connected in the common node place of described first resistance, second resistance, and the other end is connected to external power supply.

Can obtain following technique effect by the above-mentioned technical scheme that provides:

1, improves the success ratio that the Fly-by topological structure is applied to corresponding platform;

2, PCB cabling difficulty reduces, and it is big that cabling space becomes, and difficulty reduces;

3, manufacturing technique requirent reduces, memory chip is the BGA encapsulation, and peripheral decoupling capacitor has requirement from its position, for example can place it in the memory chip below, namely satisfy production technology, when reducing the risk that produces because of topology change, also guaranteed the action effect of decoupling capacitor;

4, memory chip and memory power supply connect one to one, and the power supply integrality of its memory chip is effectively guaranteed;

5, in addition, follow-up maintenance maintenance cost is low.

The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.

Claims

1. a PCB mainboard is characterized in that, comprising: CPU and the memory device that is electrically connected with CPU, and the type of described CPU is i.MX6Q/i.MX6D, the topological structure of described memory device is the fly-by topological structure.

2. PCB mainboard according to claim 1 is characterized in that, described memory device comprises:

The PCB base plate which is provided with through hole;

Second control/the address wire links to each other described first memory chip, memory chip in the middle of another is linked to each other with the tail memory chip and adjacent middle memory chip is linked to each other with memory chip in the middle of;

Build-out resistor is electrically connected with described tail memory chip;

3. PCB mainboard according to claim 2 is characterized in that, also comprises the Memory Controller Hub that is electrically connected with CPU, is connected in the other end of the described first control/address wire.

4. PCB mainboard according to claim 2 is characterized in that, described memory chip is third generation ddr sdram.

5. according to each described PCB mainboard of claim 2-4, it is characterized in that the matched impedance circuit of the differential clocks line of described memory device comprises:

First resistance, its resistance are 50 ohm, and an end is connected in the positive differential clock line;

Second resistance, its resistance are 50 ohm, and an end connects the other end of described first resistance, and the other end connects minus tolerance and divides clock line;

And one 104 electric capacity, the one end is connected in the common node place of described first resistance, second resistance, and the other end is connected to external power supply.