CN209946765U

CN209946765U - High-performance server structure based on domestic CPU

Info

Publication number: CN209946765U
Application number: CN201921289995.2U
Authority: CN
Inventors: 李伟希; 于治楼; 陈乃阔; 吴之光
Original assignee: Shandong Chaoyue CNC Electronics Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2019-08-10
Filing date: 2019-08-10
Publication date: 2020-01-14
Anticipated expiration: 2029-08-10

Abstract

The utility model discloses a high performance server structure based on domestic CPU, including core processing module, network extension module, BMC management module and supply circuit, the core processing module passes through PCIE 8 expansion slot connection PCI-E exchange chip, and PCI-E exchange chip connects the SATA extension chip, USB controller and the network controller of network extension module, and PCI-E exchange chip passes through the USB mouth connection BMC management module of USB extension chip, and BMC management module passes through SMBUS connection and monitors domestic processor; the utility model relates to a BMC management module is an external module, which realizes the remote monitoring and management of the BMC management module; by adopting the Jingjia micro JM7200XMC interface, the execution capacity of the processor is improved in a multi-line concurrent mode, and the processing overhead of a single core is reduced by optimizing the complex execution flow of a software stack.

Description

High-performance server structure based on domestic CPU

Technical Field

The utility model relates to an electron device technical field, concretely relates to high performance server structure based on domestic CPU.

Background

With the increasing demand for localization, the performance of localization processors has increased dramatically in recent years. The method is very important for the main board design technology reserve based on the domestic platform. Therefore, the problem to be solved is to design a high-performance server structure based on domestic CPU, which has strong storage capacity and BMC out-of-band management.

SUMMERY OF THE UTILITY MODEL

To the problem that exists among the prior art, the utility model aims to provide a high performance server structure based on domestic CPU.

The utility model provides a technical scheme that its technical problem adopted is: a high-performance server structure based on a domestic CPU comprises a core processing module, a network expansion module, a BMC management module and a power supply circuit, wherein the core processing module is connected with a PCI-E exchange chip through a PCIE multiplied by 8 expansion slot, the PCI-E exchange chip is connected with an SATA expansion chip, a USB controller and a network controller of the network expansion module, the PCI-E exchange chip is connected with the BMC management module through a USB port of the USB expansion chip, the BMC management module is connected with and monitors a domestic processor through an SMBUS, the domestic processor of the core processing module is connected with a plurality of DDR3 patch memory particles, and the domestic processor is connected with an XMC interface, a tera chip 82599, an SATA controller and a standard 7-wire RS232 functional port.

Specifically, the domestic processor adopts an FT1500A/16 processor.

Specifically, the BMC management module employs an AST2400 chip.

Specifically, the XMC interface adopts a Jingjia micro JM7200 type XMC interface card.

Specifically, the SATA expansion chip adopts 88SE9235 type, and is connected to a domestic processor and a PCI-E exchange chip through 1 path of PCI-E multiplied by 2 signals.

Specifically, the PCI-E exchange chip adopts a PEX8748 chip.

The utility model discloses following beneficial effect has:

the utility model discloses a BMC management module is external module, realizes BMC management module's remote monitoring management, utilizes the outband management network, logs in the management interface, uses the BMC instruction to carry out extensive unmanned on duty operation, and adopts the AST2400 chip, realizes the high performance and the low-power consumption of treater; by adopting a Jingjiami JM7200XMC interface, the execution capacity of the processor is improved in a multi-line concurrent mode, the processing overhead of a single core is reduced by optimizing the complex execution flow of a software stack, and the performance overhead caused by insufficient processing capacity of domestic hardware is greatly relieved; the utility model discloses possess calculation and very strong storage performance, greatly promoted the reusability of product, the stable function is reliable, peripheral circuit design is simple.

Drawings

Fig. 1 is a block diagram of a high-performance server architecture based on a domestic CPU.

Detailed Description

The technical solution in the embodiments of the present invention will be described in further detail in the following clearly and completely with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, a high performance server structure based on a domestic CPU includes a core processing module, a network expansion module, a BMC management module, and a power supply circuit, where the core processing module is connected to a PCI-E switching chip through a PCIE × 8 expansion slot, the PCI-E switching chip is connected to an SATA expansion chip of the network expansion module, a USB controller, and a network controller, the PCI-E switching chip is connected to the BMC management module through a USB port of the USB expansion chip, the BMC management module is connected to and monitors a domestic processor through an SMBUS bus, the domestic processor of the core processing module is connected to a plurality of DDR3 chip memory granules, and the domestic processor is connected to an XMC interface, a tera chip 82599, an SATA controller, and a standard 7-wire RS232 functional port.

The domestic processor adopts an FT1500A/16 processor, for the convenience of layout and later-stage adaptation, the memory particles adopt a DDR3 patch surface-mounted form, and the FPGA controls the power-on time sequence and level conversion of the whole machine; the BMC management module adopts an AST2400 chip, has the advantages of high performance, low power consumption, rich interfaces and the like, and provides important interfaces such as LPC, SPI, JTAG and the like; the XMC interface adopts Jingjia micro JM7200 type XMC interface card; the SATA expansion chip adopts 88SE9235 model, and is connected to the domestic processor and the PCI-E exchange chip through 1 path of PCI-E multiplied by 2 signals; the PCI-E exchange chip adopts a PEX8748 chip.

The domestic processor is matched with the autonomous GPU to design a high-performance server, so that the ten-gigabit communication is realized. The method adopts a domestic GPU, combines the multi-core characteristics of a domestic processor platform, performs optimization and enhancement based on the existing graphics software stack, fully improves the execution capacity of the multiprocessor through a multi-line concurrent mode, and reduces the processing overhead of a single core through optimizing the complex execution flow of the graphics software stack. The server structure has the advantages of calculation and strong storage performance, and reusability of products is greatly improved.

The storage unit is connected to the domestic processor and the PCI-E exchange chip through 1 path of PCI-E multiplied by 2 signals by using an 88SE9235SATA expansion chip, and the scheme has stable and reliable functions and simple design of peripheral circuits. 6 paths of SATA/SAS interfaces can be expanded outwards. The BMC management module acquires real-time temperature information of key chips such as a domestic processor in the platform through the SMBUS, acquires key voltage information through the sensor, and sends the acquired information to the upper management unit through a network. In addition, under the condition of server clustering, an out-of-band management network is utilized, a management interface is logged in, and a BMC management module instruction is used for carrying out large-scale unattended operation.

The utility model discloses not be limited to above-mentioned embodiment, anybody should learn the structural change who makes under the teaching of the utility model, all with the utility model discloses have the same or close technical scheme, all fall into the utility model discloses an within the protection scope.

The technology, shape and construction parts which are not described in detail in the present invention are all known technology.

Claims

1. A high-performance server structure based on a domestic CPU is characterized by comprising a core processing module, a network expansion module, a BMC management module and a power supply circuit, wherein the core processing module is connected with a PCI-E exchange chip through a PCIE x8 expansion slot, the PCI-E exchange chip is connected with an SATA expansion chip, a USB controller and a network controller of the network expansion module, the PCI-E exchange chip is connected with the BMC management module through a USB port of the USB expansion chip, the BMC management module is connected with and monitors a domestic processor through an SMBUS, the domestic processor of the core processing module is connected with a plurality of DDR3 patch memory particles, and the domestic processor is connected with an XMC interface, a tera chip 82599, an SATA controller and a standard 7-wire RS232 functional port.

2. The domestic CPU-based high performance server architecture of claim 1, wherein said domestic processor employs an FT1500A/16 processor.

3. The domestic CPU-based high performance server architecture of claim 1, wherein said BMC management module employs an AST2400 chip.

4. The domestic CPU-based high performance server architecture of claim 1, wherein said XMC interface is implemented as a type seikaga JM7200XMC interface card.

5. The domestic CPU-based high performance server architecture of claim 1, wherein said SATA expansion chip is of type 88SE9235, and said SATA expansion chip is connected to the domestic processor and the PCI-E switching chip through 1-way PCI-ex 2 signal.

6. The domestic CPU-based high performance server architecture of claim 5, wherein said PCI-E switch chip employs a PEX8748 chip.