CN216357502U - Nationwide VPX 3U-structured computing mainboard - Google Patents

Abstract

The utility model discloses a nationwide VPX 3U-structured computing mainboard, which comprises a mainboard and a VPX connector, wherein the mainboard comprises a main board body and a plurality of VPX connectors; the main board is integrated with a FT-2000/4 processor, a first Ethernet PHY controller, a second Ethernet PHY controller, a network communication technology WX1860AL network card, a main board clock SM9FG108, an M.2NVMe solid-state disk, a complex programmable logic device GWIN-LV9PG256I5, on-board DDR4 memory particles and a detection circuit. The utility model adopts a domestic FT-2000/4 processor and a domestic network communication science WX1860AL network card to provide 6 paths of 1000base-T interfaces, 1 path of PCIe 2.0x8, 1 path of PCIe 2.0x4, 2 paths of independent IPMI buses, 2 paths of RS232 serial ports and 8 paths of 3.3V level GPIOs through a VPX interface.

Description

Nationwide VPX 3U-structured computing mainboard

Technical Field

The utility model relates to the technical field of domestic autonomous control, in particular to a nationwide VPX 3U-structured computing mainboard.

Background

With the increasing demand of board card development on localization, the scheme of the computer main control board is synchronously updated to the localization scheme, and autonomous control is achieved. CPU chips commonly used for a VPX3U computing mainboard in the market are imported chips, most of the CPU chips adopt a chip scheme of an Intel platform, but autonomous controllability cannot be achieved, and the CPU chips are short boards; in the scheme of the domestic chip, the system comprehensive performance Unixbench value, the stream access bandwidth and the SpecJVM2008 of the Feiteng CPU chip are chips with the same performance parameters higher than those of a Loongson platform. Compared with other chips, the chip has obvious advantages in energy efficiency (performance power consumption ratio); compared with other domestic chips, the actual measurement performance of the application such as the database is relatively superior, and the system level security and credibility are achieved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a nationwide VPX 3U-structured computing mainboard.

The technical scheme of the utility model is as follows:

a nationwide VPX 3U-structured computing mainboard comprises a mainboard and a VPX connector; the main board is integrated with a FT-2000/4 processor, a first Ethernet PHY controller, a second Ethernet PHY controller, a network communication technology WX1860AL network card, a main board clock SM9FG108, an M.2NVMe solid-state disk, a complex programmable logic device GWIN-LV9PG256I5, onboard DDR4 memory particles and a detection circuit; the VPX connector comprises a PI-VBAT interface, a 3.3V-AUX interface, a DC12V interface, a CFG interface, an RSVD interface, an ETH interface, a PCIE X8 interface, a PCIE X4 interface, a debugging serial port, a communication serial port, a system enabling/resetting interface, a battery destruction signal interface, a power-on synchronous input and output interface, a safety shutdown input and output interface, a GPIO-3P 3-RSVx interface, a Beep interface, a SYS-REST-OUT interface, a PCIE resetting interface, an IPMI interface and a slot address coding interface; the PI-VBAT interface, the 3.3V-AUX interface and the DC12V interface are respectively connected with a signal input end of a mainboard, the Feiteng FT-2000/4 processor, the first Ethernet PHY controller, the second Ethernet PHY controller, the network communication technology WX1860AL network card, the mainboard clock SM9FG108, the M.2NVMe solid-state disk, the complex programmable logic device GWIN-LV9PG256I5, the onboard DDR4 memory particles and the detection circuit are respectively connected with the Feiteng FT-2000/4 processor through signals, the first Ethernet PHY controller is connected with the CFG interface through a first transformer, the second Ethernet PHY controller is connected with the RSVD interface through a second transformer, the network communication technology WX1860AL network card is connected with the ETH interface through a third transformer, the mainboard SM9FG108 is respectively connected with the network communication WX1860AL network card, the M.2VD interface and the VPX connector through signals, and the PCIE 24 FT 8625 processor is respectively connected with the Feiteng FT-2000/4 interface 8 The detection circuit is in signal connection with a complex programmable logic device GWIN-LV9PG256I5, the complex programmable logic device GWIN-LV9PG256I5 is in signal connection with a debugging serial port and a communication serial port through a first MAX3232 serial port communication module and a second MAX3232 serial port communication module respectively, the system enabling/resetting interface is connected with a signal input end of the complex programmable logic device GWIN-LV9PG256I5, the battery destruction signal interface, the Beep interface, the SYS _ REST _ OUT interface and the PCIE resetting interface are connected with a signal output end of the complex programmable logic device GWIN-LV9PG256I5, the complex programmable logic device GWIN-LV9PG256I5 is in signal connection with a power-on synchronous input and output interface, a safe shutdown input and output interface and a GPIO-3P 3_ RSVx interface respectively, and the detection circuit is in signal connection with the complex programmable logic device GWIN-LV9PG256I5, the IPMI interface and a slot address coding interface respectively.

Further, the ETH interfaces are provided with 6.

Furthermore, the number of the IPMI interfaces is 2.

Further, the onboard DDR4 memory particle adopts a dual-channel design.

Further, a BIOS ROM chip is integrated on the mainboard, and the BIOS ROM chip is in signal connection with the FT-2000/4 processor.

Further, the detection circuit comprises a CR2032 lithium manganese battery, a level shifter, a real-time clock SD3068, a first temperature detector, a restart switch, a substrate management controller, a second temperature detector, a voltage current detector and a fan, the Feiteng FT-2000/4 processor is connected with the substrate management controller through the level shifter and the restart switch in sequence, the real-time clock SD3068 and the first temperature detector are connected between the level shifter and the restart switch, the CR2032 lithium manganese battery is connected with the real-time clock SD3068, and the substrate management controller is connected with the second temperature detector, the voltage current detector, the fan, an IPMI interface and a slot position address coding interface respectively.

Compared with the prior art, the utility model has the beneficial effects that: the utility model adopts a domestic FT-2000/4 processor and a domestic network communication science WX1860AL network card to provide 6 paths of 1000base-T interfaces, 1 path of PCIe 2.0x8, 1 path of PCIe 2.0x4, 2 paths of independent IPMI buses, 2 paths of RS232 serial ports and 8 paths of 3.3V level GPIOs through a VPX interface. From the research and development design perspective, the integration level is high, the design and debugging difficulty is reduced, and the periphery is simple; from the cost perspective, a large number of devices are obviously reduced, and the cost can be saved; from the localization perspective, a VPX3U localization calculation main board with low cost can be realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a block diagram of the circuit of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

In order to explain the technical means of the present invention, the following description will be given by way of specific examples.

Examples

The embodiment of the utility model provides a nationwide VPX3U architecture calculation mainboard, which is a nationwide VPX3U cold guide board card with the quantity ratio, the species ratio and the cost ratio of 100 percent, meets the VPX3U standard, adopts a board pasting mode for an internal memory, increases the reliability, well controls the volume, and is particularly suitable for various compatible industrial personal computers and calculation processing centers of reinforced computers.

Referring to fig. 1, the computing motherboard includes a motherboard and a VPX connector, the motherboard is integrated with a FT-2000/4 processor, a first ethernet PHY controller, a second ethernet PHY controller, a network WX1860AL network card, a motherboard clock SM9FG108, an m.2nvme solid-state disk, a complex programmable logic device GWIN-LV9PG256I5, a dual-channel on-board DDR4 memory granule, a BIOS ROM chip, and a detection circuit, the VPX connector comprises a PI-VBAT interface, a 3.3V-AUX interface, a DC12V interface, a CFG interface, an RSVD interface, 6 ETH interfaces, a PCIE X8 interface, a PCIE X4 interface, a debugging serial port, a communication serial port, a system enabling/resetting interface, a battery destruction signal interface, a power-on synchronous input and output interface, a safety shutdown input and output interface, a GPIO-3P 3-RSVx interface, a Beep interface, a SYS-REST-OUT interface, a PCIE resetting interface, 2 IPMI interfaces and a slot address coding interface.

The PI-VBAT interface, the 3.3V-AUX interface and the DC12V interface are respectively connected with a signal input end of a mainboard, the FT-2000/4 processor, the first Ethernet PHY controller, the second Ethernet PHY controller, the network communication technology WX1860AL network card, a mainboard clock SM9FG108, the M.2NVMe solid-state disk, the complex programmable logic device GWIN-LV9PG256I5, the onboard DDR4 memory particles, the BIOS ROM chip and the detection circuit are respectively connected with the FT-2000/4 processor through signals, the first Ethernet PHY controller is connected with a CFG interface signal through a first transformer, the second Ethernet PHY controller is connected with an RSVD interface signal through a second transformer, the network communication technology WX1860AL network card is connected with an ETH interface signal through a third transformer, the mainboard clock SM9FG108 is respectively connected with a network communication technology WX1860, M.2NvMe, an M.2NVX connector and a VPX connector through signals, the PCIE-3526-FT 8 interface is respectively connected with a FexFT 3668 processor through signals, PCIE X4 interface signal connection, complex programmable logic device GWIN-LV9PG256I5 is respectively connected with debugging serial port and communication serial port signal through first MAX3232 serial port communication module and second MAX3232 serial port communication module, system enable/reset interface is connected with signal input end of complex programmable logic device GWIN-LV9PG256I5, battery destruction signal interface, Beep interface, SYS _ REST _ OUT interface and PCIE reset interface are connected with signal output end of complex programmable logic device GWIN-LV9PG256I5, complex programmable logic device GWIN-LV9PG256I5 is respectively connected with power-on synchronous input and output interface, safe shutdown input and output interface, GPIO-3P 3_ RSVx interface signal connection, UART serial port, buzzer and panel state indicator lamp are all realized after complex programmable logic device GWIN-LV-9 PG256I5 logic processing and pin mapping, detection circuit is respectively connected with complex programmable logic device GWIN-LV-9 PG256I5, The IPMI interface and the slot address coding interface are connected through signals.

The Feiteng FT-2000/4 processor integrates 4 64-bit high-performance cores, the main frequency is 2.2-2.6 GHz, the power consumption of the processor is only about 15W, the PCIe interface of the Feiteng FT-2000/4 processor is divided into two paths of PEU0 and PEU1 interfaces, each path of PEU supports the PCIe3.0 specification, the two paths of PEU share 34Lanes, each path is provided with one X16 and one X1, the X16 CAN be divided into two X8 interfaces, the Ethernet integrated with 2 RGMII interfaces supports the HDAudio controller, the 3 CAN2.0 interface, the 4 UART interface, the 4 GPIO 2C interface, the 2 SPI interface for use, the 1 QSPI interface and the 32-bit interface. The M.2NVMe solid-state disk is connected with a network communication technology WX1860AL network card through a mainboard clock SM9FG108, the network communication technology WX1860AL network card is adopted, a network communication gigabit Ethernet controller chip supports a four-port and double-end □ gigabit Ethernet design, and the M.2NVMe solid-state disk is provided with 4 fully integrated gigabit Ethernet Media Access Control (MAC), a physical layer (PHY) module and 4 RGMII interfaces which can be connected to an external PHY.

Further, the detection circuit comprises a CR2032 lithium manganese battery, a level shifter, a real-time clock SD3068, a first temperature detector, a restart switch, a substrate management controller, a second temperature detector, a voltage current detector and a fan, wherein the FT-2000/4 processor is connected with the substrate management controller through the level shifter and the restart switch in sequence, the real-time clock SD3068 and the first temperature detector are connected between the level shifter and the restart switch, the CR2032 lithium manganese battery is connected with the real-time clock SD3068, and the substrate management controller is respectively connected with the second temperature detector, the voltage current detector, the fan, an IPMI interface and a slot position address coding interface. The substrate management controller realizes voltage and current detection, board CPU temperature detection, fan detection control function, RTC function and IPMI function interface.

The computing main board supports wide-voltage power supply of 8-14V, the nationality rate of material types and quantity meets 100%, dual-channel memory particles are carried on board, 1 path of PCIE X8 and 1 path of PCIE X4 are supported, and 6 paths of 1000base-T Ethernet are supported; the size of 2 independent IPMI buses (power supply voltage, current, temperature monitoring and the like), 2 RS232 serial ports, 8 3.3V level GPIO interfaces and a storage interface NVME M.2 compatible with 2242 and 2280 supports the Galois system. Typical power consumption: 25W, and the maximum power consumption is less than or equal to 30W.

To sum up, the computing main board provides 6 paths of 1000base-T interfaces, 1 path of PCIe 2.0x8, 1 path of PCIe 2.0x4, 2 paths of independent IPMI buses, 2 paths of RS232 serial ports and 8 paths of 3.3V level GPIO through a VPX interface by adopting a domestic Feiteng FT-2000/4 processor and a domestic network communication science WX1860AL network card. From the research and development design perspective, the integration level is high, the design and debugging difficulty is reduced, and the periphery is simple; from the cost perspective, a large number of devices are obviously reduced, and the cost can be saved; from the localization perspective, a VPX3U localization calculation main board with low cost can be realized.

The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A nationwide VPX 3U-structured computing mainboard is characterized in that: the VPX connector comprises a mainboard and a VPX connector;

the main board is integrated with a FT-2000/4 processor, a first Ethernet PHY controller, a second Ethernet PHY controller, a network communication technology WX1860AL network card, a main board clock SM9FG108, an M.2NVMe solid-state disk, a complex programmable logic device GWIN-LV9PG256I5, onboard DDR4 memory particles and a detection circuit;

the VPX connector comprises a PI-VBAT interface, a 3.3V-AUX interface, a DC12V interface, a CFG interface, an RSVD interface, an ETH interface, a PCIE X8 interface, a PCIE X4 interface, a debugging serial port, a communication serial port, a system enabling/resetting interface, a battery destruction signal interface, a power-on synchronous input and output interface, a safety shutdown input and output interface, a GPIO-3P 3-RSVx interface, a Beep interface, a SYS-REST-OUT interface, a PCIE resetting interface, an IPMI interface and a slot address coding interface;

the PI-VBAT interface, the 3.3V-AUX interface and the DC12V interface are respectively connected with a signal input end of a mainboard, the Feiteng FT-2000/4 processor, the first Ethernet PHY controller, the second Ethernet PHY controller, the network communication technology WX1860AL network card, the mainboard clock SM9FG108, the M.2NVMe solid-state disk, the complex programmable logic device GWIN-LV9PG256I5, the onboard DDR4 memory particles and the detection circuit are respectively connected with the Feiteng FT-2000/4 processor through signals, the first Ethernet PHY controller is connected with the CFG interface through a first transformer, the second Ethernet PHY controller is connected with the RSVD interface through a second transformer, the network communication technology WX1860AL network card is connected with the ETH interface through a third transformer, the mainboard SM9FG108 is respectively connected with the network communication WX1860AL network card, the M.2VD interface and the VPX connector through signals, and the PCIE 24 FT 8625 processor is respectively connected with the Feiteng FT-2000/4 interface 8 The detection circuit is in signal connection with a complex programmable logic device GWIN-LV9PG256I5, the complex programmable logic device GWIN-LV9PG256I5 is in signal connection with a debugging serial port and a communication serial port through a first MAX3232 serial port communication module and a second MAX3232 serial port communication module respectively, the system enabling/resetting interface is connected with a signal input end of the complex programmable logic device GWIN-LV9PG256I5, the battery destruction signal interface, the Beep interface, the SYS _ REST _ OUT interface and the PCIE resetting interface are connected with a signal output end of the complex programmable logic device GWIN-LV9PG256I5, the complex programmable logic device GWIN-LV9PG256I5 is in signal connection with a power-on synchronous input and output interface, a safe shutdown input and output interface and a GPIO-3P 3_ RSVx interface respectively, and the detection circuit is in signal connection with the complex programmable logic device GWIN-LV9PG256I5, the IPMI interface and a slot address coding interface respectively.

2. The nationalized VPX3U architecture computing motherboard of claim 1, wherein: the ETH interfaces are provided with 6.

3. The nationalized VPX3U architecture computing motherboard of claim 1, wherein: the number of the IPMI interfaces is 2.

4. The nationalized VPX3U architecture computing motherboard of claim 1, wherein: the onboard DDR4 memory particle adopts a dual-channel design.

5. The nationalized VPX3U architecture computing motherboard of claim 1, wherein: the main board is also integrated with a BIOS ROM chip, and the BIOS ROM chip is in signal connection with the FT-2000/4 processor.

6. The nationalized VPX3U architecture computing motherboard of claim 1, wherein: the detection circuit comprises a CR2032 lithium manganese battery, a level shifter, a real-time clock SD3068, a first temperature detector, a restart switch, a substrate management controller, a second temperature detector, a voltage current detector and a fan, wherein the Feiteng FT-2000/4 processor is connected with the substrate management controller through the level shifter and the restart switch in sequence, the real-time clock SD3068 and the first temperature detector are connected between the level shifter and the restart switch, the CR2032 lithium manganese battery is connected with the real-time clock SD3068, and the substrate management controller is respectively connected with the second temperature detector, the voltage current detector, the fan, an IPMI interface and a slot address coding interface.

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