CN202736041U

CN202736041U - General core plate of front-end computer and front-end computer

Info

Publication number: CN202736041U
Application number: CN 201220396377
Authority: CN
Inventors: 程万鑫; 涂万杰; 王平; 赵永刚; 周钢
Original assignee: WUXI AEROSPACE FEILIN MEASUREMENT CONTROL TECHNOLOGY Co Ltd
Current assignee: WUXI AEROSPACE FEILIN MEASUREMENT CONTROL TECHNOLOGY Co Ltd
Priority date: 2012-08-10
Filing date: 2012-08-10
Publication date: 2013-02-13
Anticipated expiration: 2022-08-10

Abstract

The utility model discloses a general core plate of a front-end computer and the front-end computer, wherein the general core plate of the front-end computer comprises a processor and a standard interface. The standard interface is selectively connected with a port of the processor and the standard interface applies to at least two types of processors in a certain application field. The general core plate of the front-end computer further comprises a clock circuit, a power management, a FLASH memorizer and a Double Data Rate (DDR) memorizer and the clock circuit, the power management, the FLASH memorizer and the DDR are respectively connected with the processor. The general core plate of a front-end computer and the front-end computer has the advantages of achieving standardization utilization of various types of processors in the same certain application field by selectively leading a specific port to an external standard port, and solving the problem that that products need to be updated frequently due to bad compatibility caused by the plurality of ports arising with the changes of the processor.

Description

A kind of general purpose core core and FEP thereof of FEP

Technical field

The utility model relates to the integrated circuit (IC) design technical field, relates in particular to a kind of general purpose core core and FEP thereof of FEP.

Background technology

In the present electronic product hardware development, more and more used the core of processor as circuit, more and more higher based on the flush bonding processor cost performance of MIPS and ARM.Simultaneously, market is more and more faster to the cycle request of product design, and the quality of product will be got well, and cost is low, and product category is many.

At present, middle and high end flush bonding processor is higher with the designing requirement of peripheral high-speed memory circuit, the design proposal of 6 layers of general employings and 8 laminates, design and production, proving period are very long, mostly adopt 6 layers during design---8 layers blind, buried via hole technological design, PCB manufacturer is had relatively high expectations; In the production phase, the quality of manual pasting can't guarantee, and the quantity that SMT requires to produce wants many; From cost, this part has accounted for the cost of 30-70% often, effectively reduces simultaneously the difficulty of buying and the risk of research and development.

In the standard interface design of core board, the realization of the market overwhelming majority is: all draw for the external interface that the processor of particular series is all as far as possible; Along with the variation of processor can produce a lot of Interface design schemes, the poor compatibility of product; And the industrial control field the life cycle of the product can be longer, ceaselessly upgrading hardware and Software for Design.

The utility model content

The purpose of this utility model is to propose a kind of general purpose core core and FEP thereof of FEP, adopt modular mentality of designing, the core components such as processor, internal memory, clock and part power management are integrated, the operational system that forms a minimum, can realize the core board isolated operation, separately debugging; Processor draws at a standard interface by external pin the support of other peripheral hardwares to be realized.

For reaching this purpose, the utility model proposes a kind of general purpose core core of FEP, comprise processor and standard interface, described standard interface optionally is connected with the interface of described processor, and described standard interface adapts to the processor of at least two kinds of models in the use of specific application area.

Further, the general purpose core core of described FEP also comprises clock circuit, power management, FLASH storer and DDR storer, and described clock circuit, power management, FLASH storer and DDR storer are connected with described processor and are connected.

Further, described standard interface comprises SD/MMC interface, USB HOST HS, USB OTG HS, SPI interface, JGAG interface, audio interface, power interface, serial line interface, Ethernet interface, CAN interface, digital-quantity input interface, digital-quantity output interface and analog input and output interface.

Further, the interface mode of described standard interface is pinned, cassette, contact or stitch.

Further, the main body of the general purpose core core of described external pin and described FEP is perpendicular, described external pin is evenly distributed on two pin sockets, each described pin sockets length is not less than 51 centimetres and be not more than 51.6 centimetres, and each described pin sockets width is not less than 2.95 centimetres and be not more than 3.25 centimetres.

The utility model has also proposed a kind of FEP, comprises base plate and such as the general purpose core core of the described FEP of one of claim 1 to 5, the function of described base plate is included as described general purpose core core the interface support is provided.

Further, the function of described base plate also comprises: be used for providing the support of SD interface; Be used for providing USBhost and USB device to support; Be used for providing 2G network, 3G network or WIFI to support; Be used for providing the support of Ethernet interface; Be used for providing the hummer support; Be used for one road RS232, four road RS232/RS485 and one tunnel debugging UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver ﹠ dispensing device) are supported; Be used for providing the support to JTAG (Joint Test Action Group, joint test behavior tissue) debug port; Be used for providing the support to eight tunnel inputs, eight tunnel outputs and analog input and output; Be used for providing the power management function support.

The utility model is by optionally being drawn out to external standard interface with the special interface of processor, the processor of realizing different model uses in the standardization of same specific application area, avoided producing along with the variation of processor a lot of interfaces, the poor compatibility of product need to not stopped the problems such as upgrading.

Description of drawings

Fig. 1 is the utility model embodiment one described general purpose core core structural representation;

Fig. 2 is the standard interface block diagram of the utility model embodiment one described general purpose core core;

Fig. 3 is the pin interface block diagram (A pin sockets) of the pin sockets of the utility model embodiment one described general purpose core core;

Fig. 4 is the pin interface block diagram (B pin sockets) of the pin sockets of the utility model embodiment one described general purpose core core;

Fig. 5 (a) is the vertical view of the utility model embodiment one described general purpose core core pin sockets;

Fig. 5 (b) is the front elevation of the utility model embodiment one described general purpose core core pin sockets;

Fig. 5 (c) is the side view of the utility model embodiment one described general purpose core core pin sockets;

Fig. 5 (d) is the upward view of the utility model embodiment one described general purpose core core pin sockets;

Fig. 6 is the interface framework of the utility model embodiment one described processor and DDR2 storer;

Fig. 7 is the hardware block diagram of the utility model embodiment two described FEPs;

Fig. 8 is SD interface framework among the utility model embodiment two.

Embodiment

Further specify the technical solution of the utility model below in conjunction with accompanying drawing and by embodiment.

Embodiment one

Fig. 1 is the described general purpose core core of the present embodiment structural representation, as shown in Figure 1, the general purpose core core of the described FEP of the present embodiment comprises processor 101 and standard interface 102, described standard interface 102 optionally is connected with the interface of described processor 101, the processor 101 that described standard interface 101 adapts to Multiple Types uses in the standardization of same specific application area, supports simultaneously the IMX28 serial application of Aml186/88, Freescale of AMD in this specific application area of Internet of Things FEP such as this standard interface.

According to modular mentality of designing, the core components such as processor, internal memory, clock and part power management are integrated, the operational system that forms a minimum, can realize the isolated operation of described general purpose core core, separately debugging, therefore, described general purpose core core also can comprise built-in clock circuit 104, power management 103, FLASH storer 106 and DDR storer 105.

The present embodiment is for the specific application of Internet of Things FEP, draw drawing at a standard interface realization special interface by external pin, do not lock the standard interface that specific processor designs core board, so, processor 101 is to draw at a general standard interface by external pin to realize drawing of special interface to the support of other peripheral hardwares, can avoid producing a lot of interfaces along with the variation of processor, the poor compatibility of product need to not stopped the problems such as upgrading.

Fig. 2 is the standard interface block diagram of the utility model embodiment one described general purpose core core, as shown in Figure 2, described standard interface comprises SD/MMC interface, USB HOST HS, USB OTG HS, SPI interface, JGAG interface, audio interface, power interface, serial line interface, Ethernet interface, CAN interface, digital-quantity input interface, digital-quantity output interface and analog input and output interface.

Described standard interface has 160, the interface mode of standard interface can be pinned, cassette, contact or stitch, for easy to use, the external pin of the described general purpose core core of the present embodiment is evenly distributed on the stitch socket of two 80PIN, each described stitch socket lays respectively at the both sides of described general purpose core core, and described stitch and described chip body are perpendicular.

Particularly, Fig. 3 is the pin interface block diagram (A pin sockets) of the pin sockets of the described general purpose core core of the present embodiment, and Fig. 4 is the pin interface block diagram (B pin sockets) of the pin sockets of the described general purpose core core of the present embodiment, as described in Fig. 3 and Fig. 4.Wherein, the stitch interface on the A stitch socket is as shown in the table.

Pin interface on the B pin sockets is as shown in the table.

Above pinout only is a most preferred embodiment of the present utility model; can certainly be from different pin open numberings; perhaps adopt the always numbering of different countings; these all variations and change do not break away from the justice that should have of the present utility model; do not give unnecessary details one by one at this, described variation and change are all within protection domain of the present utility model.

Fig. 5 (a) is the vertical view of the described general purpose core core of the present embodiment pin sockets, and shown in Fig. 5 (a), laterally distance is 1.27 ± 0.1 centimetres between each adjacent described external pin; Vertically distance is 1.27 ± 0.1 centimetres also between each adjacent described external pin; Described pin sockets is long to be 1.27*40+0.5 ± 0.3 centimetre; Fig. 5 (b) is the front elevation of the described general purpose core core of the present embodiment pin sockets, shown in Fig. 5 (b), described external pin length is 2.45 ± 0.25 centimetres, described external leg diameter is about 0.50, described external pin divides two rows evenly to arrange along the long limit of described pin sockets, and two row's pins are 0.96 centimetre to the distance on the long limit of pin sockets; Fig. 5 (c) is the side view of the described general purpose core core of the present embodiment pin sockets; Fig. 5 (d) is the upward view of the described general purpose core core of the present embodiment pin sockets.

In the present embodiment on the general purpose core core of processor and FEP the connected mode of miscellaneous part be connected for conventional, there is no special character.The processor of different model and different model DDR storer connecting circuit figure slightly have any different, but its ultimate principle is identical.The present embodiment is take the DDR storer of the processor chips of the IMX28 series of Freescale and hynix H5PS1G63EFR 1Gb (64Mx16) DDR2 SDRAM as example, and its interface circuit figure as shown in Figure 6.

Wherein, because the dynamic memory interface (DMI) that processor carries is supported the storer of DDR2 and MDDR type, it is not strict especially that power consumption is required, so hynix H5PS1G63EFR 1Gb (64Mx 16) DDR2 SDRAM memory grain is preferred DDR type of memory.

Therefore not to repeat here with the connecting circuit figure of power management 103, clock circuit 104, FLASH storer 106 respectively for processor 101.

Embodiment two

The invention also discloses a kind of FEP, described FEP comprises the general purpose core core of base plate and embodiment one described FEP, and the function of described base plate is included as described general purpose core core the interface support is provided.

Fig. 7 is the hardware block diagram of the utility model embodiment two described FEPs, and as shown in Figure 7, the function that base plate is mainly realized also comprises:

(1) the SD interface is supported, as among Fig. 7 707;

(2) support of the mobile communication such as 2G/3G/WIFI is as among Fig. 7 703;

(3) to remote I/O and access support, as among Fig. 7 710;

(4) Ethernet Ethernet interface is supported, as among Fig. 7 704 and 705;

(5) hummer support is as among Fig. 7 706;

(6) the fieldbus port is supported, as among Fig. 7 711;

(7) to the support 709 of JTAG debug port;

(8) to eight tunnel inputs/eight tunnel output and supports of analog input and output, as among Fig. 7 712,713 and 714;

(9) power management function is as among Fig. 7 708.

Wherein, the SD interface framework is referring to Fig. 8; Alarms when hummer mainly is used in System self-test and unit exception etc. are by the digital output pin control of processor; Ethernet Ethernet interface is supported, because the Internet of Things FEP has the effect of part gateway, so, must support two network interfaces, the present embodiment network interface chip (MAC/PHY transceiver) is take the LAN8270A chip of SMSC as example, and the LAN8270A chip is supported the 10/100M self-adaptation and supported the functions such as cross spider Auto-Sensing and switching; For USB interface, a USB interface is drawn, use when doing debugging, support simultaneously External memory equipment, another interface transfers the mini-PCIE interface to, supports external WIFI/2G/3G module, in actual use, the present embodiment is supported respectively WCDMA and CDMA and GPRS take the EM770W of Huawei Company and EM660 module as example.

The general purpose core core of the described FEP of the present embodiment is the processor outside have been encapsulated the standardized shell of one deck use, make the more specialized and standardization of application, solve the compatibling problem of dissimilar processor, when processor model changes, only need again the corresponding interface of new processor to be connected on the standard interface of general purpose core core described in the utility model and get final product, FEP need not to do any change.

The above only is preferred embodiment of the present utility model, and is in order to limit the utility model, not all within spirit of the present utility model and principle, any modification of doing, is equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.

Claims

1. the general purpose core core of a FEP, it is characterized in that, comprise processor and standard interface, described standard interface optionally is connected with the interface of described processor, and described standard interface adapts to the processor of at least two kinds of models in the use of same specific application area.

2. the general purpose core core of FEP as claimed in claim 1, it is characterized in that, the general purpose core core of described FEP also comprises clock circuit, power management, FLASH storer and DDR storer, and described clock circuit, power management, FLASH storer and DDR storer are connected with described processor and are connected.

3. the general purpose core core of FEP as claimed in claim 1 or 2, it is characterized in that, described standard interface comprises SD/MMC interface, USB HOST HS, USB OTG HS, SPI interface, JGAG interface, audio interface, power interface, serial line interface, Ethernet interface, CAN interface, digital-quantity input interface, digital-quantity output interface and analog input and output interface.

4. the general purpose core core of FEP as claimed in claim 3 is characterized in that, the interface shape of described standard interface is pinned, cassette, contact or stitch.

5. the general purpose core core of FEP as claimed in claim 4, it is characterized in that, described standard is perpendicular with the main body of the general purpose core core of described FEP by mouth, described external pin is evenly distributed on two pin sockets, each described pin sockets length is not less than 51 centimetres and be not more than 51.6 centimetres, and each described pin sockets width is not less than 2.95 centimetres and be not more than 3.25 centimetres.

6. a FEP is characterized in that, comprises base plate and such as the general purpose core core of the described FEP of one of claim 1 to 5, described base plate is used to described general purpose core core that the interface support is provided.

7. FEP as claimed in claim 6 is characterized in that, described base plate also is used for: be used for providing the support of SD interface; Be used for providing USB host and USB device to support; Be used for providing 2G network, 3G network or WIFI to support; Be used for providing the support of Ethernet interface; Be used for providing the hummer support; Be used for one road RS232, four road RS232/RS485 and one tunnel debugging UART are supported; Be used for providing the support to the JTAG debug port; Be used for providing the support to eight tunnel inputs, eight tunnel outputs and analog input and output; Be used for providing the power management function support.