CN210924548U

CN210924548U - Single-board computer on-board memory circuit of Intel processor platform

Info

Publication number: CN210924548U
Application number: CN202020134265.1U
Authority: CN
Inventors: 谢文广; 程加钢; 柳星
Original assignee: Shenzhen Jhctech Development Co ltd
Current assignee: Shenzhen Jhctech Development Co ltd
Priority date: 2020-01-19
Filing date: 2020-01-19
Publication date: 2020-07-03
Anticipated expiration: 2030-01-19

Abstract

The utility model provides an intel treater platform veneer computer board carries memory circuit belongs to treater circuit field. The utility model discloses a power module, level conversion module, sequential control module and a plurality of memory granule, the quantity of memory granule is decided jointly by the bit width of memory granule, the interface bit width between CPU and the memory, wherein, power module links to each other with memory granule electrical property, provides the power for the memory granule, sequential control module links to each other with power module, control on the memory, sequential control module passes through the level conversion module and links to each other with the CPU of intel treater platform, the memory granule still with CPU signal connection for communication between memory and the CPU. The utility model has the advantages that: the design of compatible multiple capacity, the stable performance.

Description

Single-board computer on-board memory circuit of Intel processor platform

Technical Field

The utility model relates to a treater circuit structure especially relates to an intel treater platform single board computer board carries memory circuit.

Background

In recent years, intel introduced an industry-leading 14-nm technology, and its Apollo lake platform (intel atom processor E3900 series, intel saint processor N3350, and intel pentium processor N4200 platform) assisted with real-time computing of applications such as digital monitoring, new in-vehicle experience, industrial and office automation progress, retail and medical new solutions, and also has an increasingly wide application in digital monitoring, new in-vehicle industry, industrial and office automation, new retail and medical industry, and an increasingly large number of embedded computers based on the Apollo lake platform. However, the traditional embedded computer generally adopts a form of a memory slot and an external plug-in memory card, the design on hardware is relatively simple, and considering that some industries need products with high stability, especially the industries such as vehicle-mounted and the like, an onboard memory needs to be designed to improve the stability of the whole system to meet the requirements of the industries.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, the utility model provides an intel processor platform single-board computer on-board memory circuit.

The utility model discloses a power module, level conversion module, sequential control module and a plurality of memory granule, the quantity of memory granule is decided jointly by the bit width of memory granule, the interface bit width between CPU and the memory, wherein, power module links to each other with memory granule electrical property, provides the power for the memory granule, sequential control module links to each other with power module, control on the memory, sequential control module passes through the level conversion module and links to each other with the CPU of intel treater platform, the memory granule still with CPU signal connection for communication between memory and the CPU.

The utility model discloses make further improvement, adopt the chain form to walk the line between the memory granule.

The utility model discloses make further improvement, the bit width of memory granule equals, the quantity of memory granule by interface bit width between CPU and the memory decides, the total of memory granule capacity is the capacity of whole memory.

The utility model discloses make further improvement, the memory bit wide of memory granule is X8, the interface bit wide between CPU and the memory is 64bit, the quantity of memory granule is 8.

The utility model discloses do further improvement, the time sequence control module includes control chip U23-2 and switch SW1, control chip U23-2's pin A42 is the power-on control pin on the memory, control chip U23-2's pin A42 links to each other with CPU, control chip U23-2's pin B15 is power module enable pin, through the break-make of switch SW1 control power module power.

The utility model discloses make further improvement, level shift module includes level shift chip U24, level shift chip U24 changes voltage from 1.8V to 3.3V, makes sequential control module and CPU ability normal communication.

The utility model discloses make further improvement, power module includes power supply chip U23-1, power supply chip U23-1 provides power VDDQ and gives the memory granule.

Compared with the prior art, the beneficial effects of the utility model are that: the design of various capacities is compatible, and the requirements of various capacities are met; the performance is stable, and the method can be applied to industries with certain requirements on the earthquake resistance; the cost of the onboard memory particles of the mass production is lower than that of the externally-inserted memory, and cost control of enterprises is facilitated to a certain extent.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a schematic diagram of a memory particle trace;

FIG. 3 is a schematic circuit diagram of the power supply module, the level shift module, and the timing control module of the present invention;

fig. 4 is a schematic diagram of two of the memory granule circuits.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 1, the utility model discloses a power module, level conversion module, sequential control module and a plurality of memory granule, the quantity of memory granule is decided jointly by the bit width of memory granule, the interface bit width between CPU and the memory, wherein, power module links to each other with memory granule electrical property, provides the power for the memory granule, sequential control module links to each other with power module, controls power on the memory, sequential control module passes through the level conversion module and links to each other with the CPU of intel's treater platform, the memory granule still with CPU signal connection for communication between memory and the CPU.

In this embodiment, it is preferable that all the memory granules have the same bit width, the number of the memory granules is determined by the bit width of the interface between the CPU and the memory, and the sum of the capacities of the memory granules is the capacity of the whole memory. At the beginning of design of an onboard memory, the capacity of the onboard memory is well defined by combining product specifications, various capacity compatible designs are made as far as possible, memory particles are selected, and under the condition that space allows, the memory bit width is X8 specification, and X8 capacity is compatible with larger capacity. Of course, other bit widths of memory grains may be used.

The bit width of the interface between the CPU and the memory is 64 bits, so 8 grains are needed, the capacity of each grain can be selected in various ways, and if the capacity of each grain is 256MB/512MB/1G, the memory with the capacity of 2G/4G/8G and the like is correspondingly formed.

The BIOS of this example integrates the information needed for memory into the same ROM. Thereby effectively reducing the cost. In addition, in this embodiment, by setting the memory granules, the memory information configuration is easier, and specifically, the normal extrapolation memory bank is: the BIOS reads the eprom content (the content is SPD) on the memory bank, and the BIOS performs settings such as initialization according to the SPD information. Because SPD information is inconsistent due to different capacities, each content capacity needs to be configured separately, and 2G, 4G and 8G need to be configured separately.

However, as long as the bit width (X8) of the memory granule is determined, and the number of the memory granules is 8, which means that the memory granules are fixed, the SPD information is fixed, and the BIOS does not need to read eeprom only by assigning the SPD information to the BIOS, and the SPD information of the memory is directly configured. The configuration process is greatly simplified.

As shown in fig. 2, in the case of the LAYOUT lines, since the lines of the onboard memory are placed on the board, the difficulty of the lines is increased, this example optimizes the prior art, and for 8 memory particles, it is preferable to adopt chain-shaped lines among the memory particles. The lengths of the wires are equal, and the internal memory wire specifications are met. Reasonable overall arrangement and walk the line, make the utility model discloses an onboard memory is walked the line more easily, and the performance is more stable. The shock resistance of the product is improved, and the requirements of strong shock scenes of vehicle-mounted products and the like are met.

As shown in fig. 3, the timing control module of this embodiment includes a control chip U23-2 and a switch SW1, a pin a42 of the control chip U23-2 is a power-on control pin for the memory, a pin a42 of the control chip U23-2 is connected to the CPU, a pin B15 of the control chip U23-2 is a power supply module enable pin, and the power supply of the power supply module is controlled by the switch SW1 to be turned on or off.

The level shift module of this example includes a level shift chip U24, and the level shift chip U24 shifts the voltage from 1.8V to 3.3V, so that the timing control module and the CPU can communicate normally.

The power supply module of this example includes a power supply chip U23-1, and this example supplies power to the memory through a power supply chip U23-1, where VDDQ is 1.35V, and a power supply VDDQ _ VTT, which is half of VDDQ.

As shown in fig. 4, the power pin of the memory particles in this embodiment is connected to the power supply module, and power is supplied through the power supply chip U23-1, and this embodiment further has a pin communicating with the CPU.

Compared with other products of the Intel Apollo Lake platform external plug-in memory strip in the market, the technical scheme of the CPU board-carried memory particle has obvious advantages and can be applied to industries with certain requirements on shock resistance, such as vehicle-mounted industries; simultaneously, the cost of the onboard memory particles of the mass production is lower than that of the extrapolated memory, cost control of enterprises is facilitated to a certain extent, once the technology is mature, the technology can be transplanted to other platforms of Intel, and more stable products are pushed to the market. The technical scheme can meet wider market demands, is more suitable for the development of the product in new vehicle-mounted, new retail and medical industries, and has good market competitiveness.

The above-mentioned embodiments are the preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-mentioned embodiments, and the scope of the present invention includes and is not limited to the above-mentioned embodiments, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. An intel processor platform single board computer on-board memory circuit, characterized in that: comprises a power supply module, a level conversion module, a time sequence control module and a plurality of memory granules, wherein the number of the memory granules is determined by the bit width of the memory granules and the bit width of an interface between a CPU and a memory, wherein,

the power supply module is electrically connected with the memory particles to provide power for the memory particles,

the time sequence control module is connected with the power supply module and controls the memory to be powered on,

the time sequence control module is connected with a CPU of the Intel processor platform through a level conversion module,

the memory grain is also in signal connection with the CPU and is used for communication between the memory and the CPU.

2. The intel processor platform single board computer on-board memory circuit of claim 1, wherein: chain-shaped routing is adopted among the memory particles.

3. The intel processor platform single board computer on-board memory circuit of claim 1 or 2, wherein: the bit widths of the memory granules are equal, the number of the memory granules is determined by the bit width of an interface between the CPU and the memory, and the sum of the capacities of the memory granules is the capacity of the whole memory.

4. The intel processor platform single board computer on-board memory circuit of claim 3, wherein: the memory bit width of the memory granules is X8, the interface bit width between the CPU and the memory is 64 bits, and the number of the memory granules is 8.

5. The intel processor platform single board computer on-board memory circuit of claim 1 or 2, wherein: the timing control module comprises a control chip U23-2 and a switch SW1, a pin A42 of the control chip U23-2 is a power-on control pin of a memory, a pin A42 of the control chip U23-2 is connected with a CPU, a pin B15 of the control chip U23-2 is a power supply module enabling pin, and the power supply of the power supply module is controlled to be switched on and off through the switch SW 1.

6. The intel processor platform single board computer on-board memory circuit of claim 5, wherein: the level conversion module comprises a level conversion chip U24, and the level conversion chip U24 converts the voltage from 1.8V to 3.3V, so that the timing control module and the CPU can normally communicate.

7. The intel processor platform single board computer on-board memory circuit of claim 5, wherein: the power supply module comprises a power supply chip U23-1, and the power supply chip U23-1 supplies power VDDQ to the memory particles.