CN210835151U - Chip testing system - Google Patents
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- CN210835151U CN210835151U CN201921666029.8U CN201921666029U CN210835151U CN 210835151 U CN210835151 U CN 210835151U CN 201921666029 U CN201921666029 U CN 201921666029U CN 210835151 U CN210835151 U CN 210835151U
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Abstract
The utility model relates to a chip test system can satisfy growing chip test demand. Wherein, chip test system includes: the test mainboard is used for configuring the physical interface unit and the memory controller according to the type of the chip to be tested; the test daughter board is provided with a chip type discriminator and a mounting position, wherein the chip type discriminator is used for discriminating the type of the chip to be tested, and the mounting position is used for mounting the chip to be tested; the test mainboard is electrically connected with the test daughter board.
Description
Technical Field
The utility model relates to a chip test field, concretely relates to chip test system.
Background
With the development of science and technology, the demand of chip testing in the computer industry is gradually increasing. The variety of chips is increasing, and different kinds of chips have different test requirements for chip testing. For example, for SDRAM (synchronous dynamic Random Access Memory), the SDRAM types may include DDR SDRAM (Double Data Rate SDRAM, Double-Rate SDRAM) and LPDDR SDRAM (Low Power Double Data Rate SDRAM, Double-Rate SDRAM with Low Power consumption), and DDR SDRAM and LPDDR SDRAM are also in continuous update iteration, and the operating voltage, interface I/O type, and package pin distribution between different DDR SDRAMs and LPDDR SDRAM are different.
In the design and production processes of chips, a verification platform is required to test the functions and performances of the chips to be tested. However, in the prior art, one verification platform can only test one chip, and in order to meet the test requirements of different types of chips, different verification platforms are required to test different chips, so that the chip test efficiency is low.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a chip test system can satisfy growing chip test demand.
In order to solve the above technical problem, the following provides a chip testing system, including: the test mainboard is used for configuring the physical interface unit and the memory controller according to the type of the chip to be tested; the test daughter board is provided with a chip type discriminator and a mounting position, wherein the chip type discriminator is used for discriminating the type of the chip to be tested, and the mounting position is used for mounting the chip to be tested; the test mainboard is electrically connected with the test daughter board.
Optionally, the test motherboard further includes: a first connector connected to the physical interface unit; the test daughter board further includes: a second connector connected to the chip type discriminator and the mounting site, and electrically connected to the first connector; the first connector and the second connector are used for establishing interaction between the test main board and the test sub-board.
Optionally, the test motherboard includes: the physical interface unit and the memory controller are arranged in the control chip, and the control chip is used for configuring the physical interface unit and the memory controller so that the physical interface unit and the memory controller are configured correspondingly to different types of chips to be tested; the control chip is connected with the first connector through the physical interface unit.
Optionally, the test motherboard further includes: and the power management unit is electrically connected to the first connector and the control chip and is used for respectively outputting voltage to the control chip and the first connector according to the type of the chip to be tested.
Optionally, the chip type discriminator includes: the type switch is used for generating a corresponding chip identification code according to the type of the chip to be tested installed on the installation position; the test daughter board is further configured to send the chip identification code to the test motherboard, and the test motherboard is configured to configure the physical interface unit and the memory controller according to the chip identification code.
Optionally, the type switch includes a plurality of dial switches, the number of the dial switches is the same as the number of bits of the chip identification code, and the switching status of each dial switch corresponds to the value of one bit of the chip identification code.
Optionally, the number of the dial switches is 3, so as to generate 8 different three-bit chip identification codes, and each kind of chip to be tested corresponds to at least one chip identification code.
Optionally, the mounting position is provided with a pin connection position, and each pin connection position corresponds to a pin of the chip to be tested one to one.
Optionally, the test daughter board is detachably connected to the test motherboard.
Optionally, the first connector comprises at least one of a DDR4 SO-DIMM connector or a PCIe connector, and the second connector comprises at least one of a DDR4 SO-DIMM connector or a PCIe connector.
The utility model discloses a chip test system uses different interface agreement to different kinds of chips. When testing different types of chips, only the test daughter board with different pin connectors needs to be replaced to adapt to the chips with different pins, so that the test daughter board is very simple and convenient, and the cost is low.
Drawings
Fig. 1 is a schematic diagram of a connection relationship of a chip testing system according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a dial switch according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a dial switch according to an embodiment of the present invention.
Fig. 4 is a schematic step diagram of a chip testing method according to an embodiment of the present invention.
Detailed Description
Research shows that, because the types of chips are many, and the operating voltages, interface types, and signal pins of different types of chips are different, when testing different types of chips, verification needs to be performed on a certain specific chip, for example, the verification of LPDDR4 may use an Intel apolo lake platform, and the verification of DDR4 may use an Intel pure platform. Therefore, in order to meet the verification requirements of different types of chips, different verification platforms need to be used, the investment in manpower and material resources is large, and when different types of chips are tested in a switching manner, verification machines need to be switched, so that the detection speed of the chips is greatly limited.
The following describes a chip testing system according to the present invention in detail with reference to the accompanying drawings and the following detailed description.
Fig. 1 is a schematic diagram of a connection relationship of a chip testing system according to an embodiment of the present invention.
In this embodiment, a chip test system is provided, comprising: the test system comprises a test mainboard 101 and a memory controller 105, wherein the test mainboard 101 is provided with a physical interface unit 106 and the memory controller 105, and the test mainboard 101 is used for configuring the physical interface unit 106 and the memory controller 105 according to the type of a chip to be tested, namely a chip to be tested, of the chip test system; the test daughter board 102 is provided with a chip type discriminator 103 and a mounting position 104, wherein the chip type discriminator 103 is used for discriminating the type of the chip to be tested, and the mounting position 104 is used for mounting the chip to be tested; the test main board 101 and the test sub board 102 are electrically connected.
In this specific embodiment, the test motherboard 101 can configure the physical interface unit 106 and the memory controller 105 according to the type of the chip to be tested, and therefore, the test motherboard can be used for chip testing, different interface protocols are used for different types of chips, and when the chips using different interface protocols are tested, only one set of chip testing system needs to be used, so that the material cost required for testing various chips is reduced, and when the chips of different types are switched to be tested, the test motherboard is very simple and convenient, and the detection speed of the chips is increased.
In a specific embodiment, the test motherboard 101 includes a control chip 109, the control chip 109 supports multiple interface protocols, the physical interface unit 106 and the memory controller 105 are disposed in the control chip 109, the control chip 109 is configured to configure the physical interface unit 106 and the memory controller 105, so that the physical interface unit 106 and the memory controller 105 are configured to correspond to different types of chips, and the control chip 109 is connected to the first connector 107 through the physical interface unit 106.
In one embodiment, the chip test system may be used for testing SDRAM chips, and since the kinds of SDRAM chips may include at least DDR1, DDR2, DDR3 and DDR4 series, the control chip may include at least DDR interface protocols corresponding to DDR1, DDR2, DDR3 and DDR4 series.
In one embodiment, the control chip 109 may be a System On Chip (SOC), such as an UltraScale + MPSOC chip of Xilinx corporation, usa, a RK3399 chip of fukurui microelectronics, or a50 chip of zhhai zhi science, wherein the UltraScale + MPSOC chip supports DDR interface protocols corresponding to DDR4, LPDDR4, DDR3, DDR3L, and LPDDR3, the RK3399 chip of fukurui microelectronics supports DDR interface protocols corresponding to DDR3, DDR3L, LPDDR3, and LPDDR4, and the a50 chip of zhhai zhi supports DDR interface protocols corresponding to DDR4, LPDDR4, DDR3, DDR3L, and LPDDR 3.
In fact, the specific model of the control chip 109 can be selected according to the requirement.
In a specific embodiment, the test motherboard 101 further includes: a first connector 107 connected to the physical interface unit 106; the test daughter board 102 further includes: a second connector 108 connected to the chip type discriminator 103 and the mounting site 104 and electrically connected to the first connector 107; the first connector 107 and the second connector 108 are used to establish power and data interaction between the test motherboard 101 and the test daughter board 102.
In one embodiment, the first connector 107 may be a DDR4 SO-DIMM connector or a PCIe connector, etc.; the second connector 108 may be a DDR4 SO-DIMM connector, a PCIe connector, or the like.
The DDR4 SO-DIMM connector is used for connecting DDR4 SO-DIMM (Small Outline Dual inline Memory Module), and can support higher data transmission rate. In one embodiment, the first connector 107 may be a DDR4 sodim connector or a PCIe connector from fujikang, anfeinuo, etc. The first connector 107 transmits a signal of the physical interface unit 106 to the test daughter board 102, and is used to acquire the kind of the chip to be tested mounted on the test daughter board 102.
The PCIe connector is a high-speed connector complying with a high-speed serial computer expansion bus standard, so that data interaction between the test motherboard 101 and the test daughter board 102 is high-speed data interaction.
In fact, the specific types of the first connector 107 and the second connector 108 can be selected according to the requirement, such as the second connector 108 is configured as a standard interface, and is not limited to the DDR4 SO-DIMM connector and the PCIe connector.
In one embodiment, the chip type discriminator 103 comprises: and the type switch is used for generating a corresponding chip identification code according to the type of the chip mounted on the mounting position 104. The test daughter board 102 sends a chip identification code to the test motherboard 101 through the second connector 108, and the test motherboard 101 configures the physical interface unit 106 and the memory controller 105 according to the chip identification code.
Please refer to fig. 2, which is a schematic structural diagram of a type switch according to an embodiment of the present invention.
In this embodiment, the type switch includes a plurality of dial switches, the number of the dial switches is the same as the number of bits of the chip identification code, one switch may correspond to two values, i.e., power or ground, i.e., high or low voltage, respectively, and the switching status of each dial switch corresponds to the value of one chip identification code.
In one embodiment, the number of the dial switches is 3, such as S0, S1 and S2 shown in fig. 2, the number of bits corresponding to the chip identification code is 3, and each dial switch corresponds to one code bit of the chip identification code. Because each code bit can produce two kinds of values, the type change-over switch containing 3 dial switches can produce 8 different chip identification codes, and each kind of chip can at least correspond to one identification code.
In this embodiment, the chip identification code is binary coded, and is represented by 0 and 1, and corresponds to a low level and a high level, respectively, and the number of bits of the identification code is 3, so that 8 different combinations of identification codes can be provided. For example, 0 may correspond to a low level, 1 corresponds to a high level, when the chip identification code is generated, if the code bit of the chip identification code is 1, the dial switch corresponding to the code bit is toggled to a first position and connected to a first voltage VCC, and the output terminal corresponding to the code bit in the dial switch outputs a high level; and if the code bit of the chip identification code is 0, the dial switch corresponding to the code bit is shifted to a second position and is connected to a second voltage VSS, and the output end corresponding to the code bit in the dial switch outputs a low level. If the code bit of the chip identification code is 0, the dial switch corresponding to the code bit is shifted to a first position and connected to a first voltage VCC, and the output end corresponding to the code bit in the dial switch outputs a high level; if the code bit of the chip identification code is 1, the dial switch corresponding to the code bit is shifted to a second position and connected to a second voltage VSS, and the output end corresponding to the code bit in the dial switch outputs a low level.
Specifically, when a chip identification code 001 needs to be generated, the dial switch of the first code bit is shifted to the second position and connected to VSS, the output end Brd-ID [0] corresponding to the first code bit outputs a low level, the dial switch of the second code bit is shifted to the second position and connected to VSS, the output end Brd-ID [1] corresponding to the second code bit outputs a low level, the dial switch of the third code bit is shifted to the first position and connected to VCC, and the output end Brd-ID [2] corresponding to the third code bit outputs a high level.
In this embodiment, the chip type corresponding to each chip identification code is specified in advance. In the testing process, the test motherboard 101 only needs to correspond the received chip identification code to a specific chip type.
As shown in tables 1 and 2:
| Brd-ID[2] | Brd-ID[1] | Brd-ID[0] | |
| 0 | 0 | 0 | |
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 0 | 1 | 1 | DDR4 |
Table 1 shows the correlation between Brd-ID and chip (1)
| Brd-ID[2] | Brd-ID[1] | Brd-ID[0] | |
| 1 | 0 | 0 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | |
| 1 | 1 | 1 | LPDDR4 |
Table 2 shows the correlation between Brd-ID and chip (2)
The chip identification code Brd _ ID [2:0] comprises Brd-ID [2], Brd-ID [1] and Brd-ID [0], and Brd-ID [2], Brd-ID [1] and Brd-ID [0] in the table 1 and the table 2 respectively correspond to three code bits of the chip identification code Brd _ ID [2:0 ]. The number of code bits of the chip identification code is not limited to this, and may be 4 bits, 5 bits, or the like.
Please refer to fig. 3, which is a schematic structural diagram of a type switch according to an embodiment of the present invention. In this specific embodiment, the input terminals corresponding to the three code bits are fixedly connected to the power VCC or the ground VSS to form a group corresponding to a specific chip identification code. Therefore, in this embodiment, different groups need to be gated for the test daughter boards of different kinds of chips to generate corresponding chip identification codes.
The type switch in fig. 2 is more flexible to use, while the type switch in fig. 3 needs to determine the allocation rule of the chip identification code at the beginning of the design and is not changeable during the use process. In the actual use process, the selection can be carried out according to the requirement.
In this embodiment, when the test daughter board 102 is connected to the test motherboard 101, the test motherboard 101 can obtain the chip identification code generated by the type switch through the first connector 107. In this way, the test motherboard 101 can know which kind of chip is currently connected to, so the control chip 109 can configure the physical interface unit 106 and the memory controller 105 on the test motherboard 101 based on the type of the chip to be tested, select the drivers of the physical interface unit 106 and the memory controller 105, and configure the physical interface unit 106 and the memory controller 105 to be suitable for the kind of chip, which is simple and convenient.
The test motherboard 101 selects the drivers for the DDR controller and physical interface unit 106 based on the value of Brd _ ID [2:0 ]. For example, when Brd _ ID [2:0] is 010 or 011, the chip type is DDR4, and the test board 101 configures the memory controller 105 and the physical interface unit 106 into the DDR4 interface mode by the corresponding driver; when Brd _ ID [2:0] ═ 110 or 111, the chip type is LPDDR4, and the test motherboard 101 configures the memory controller 105 and the physical interface unit 106 into the LPDDR4 interface mode by the corresponding drivers.
In one embodiment, the mounting locations 104 are provided with pin connection locations, which correspond to pins of a chip to be tested one to one. Since different kinds of chips have different package pins, the number of the test daughter boards 102 may be multiple, and different pin connection locations are disposed on the mounting locations 104 of each test daughter board 102 to adapt to different kinds of chips.
In a specific embodiment, the test sub-board 102 is detachably connected to the test main board 101, so that different test sub-boards 102 are used to connect to the test main board 101 when different types of chips are tested, and the test sub-board 102 or the test main board 101 can be replaced when damaged, thereby reducing the maintenance cost.
In a specific embodiment, the test motherboard 101 further includes: and a power management unit 110 electrically connected to the first connector 107 and the control chip 109, for supplying power to the control chip 109 and the first connector 107 according to the kind of the chip to be tested, so as to supply power to the second connector 108 connected to the first connector 107, and the chip kind discriminator 103 and the mounting location 104 connected to the second connector 108.
In this embodiment, since different kinds of chips to be tested have different operating voltages, different voltages need to be provided when testing different kinds of chips. In this embodiment, the power management unit 110 can provide different operating voltages for different kinds of chips to be tested.
Specifically, a DDR4 chip is mounted on the test daughter board 102, and when the test of the DDR4 chip is performed, since the operating voltage of the DDR4 chip is 2.5V, the power management unit 110 outputs 2.5V to supply power to the DDR4 chip. When the test daughter board 102 is mounted with the LPDDR4 chip and the LPDDR4 chip is tested, the power management unit 110 outputs 1.8V to power the LPDDR4 chip because the working voltage of the LPDDR4 chip is 1.8V.
In the embodiments corresponding to tables 1 and 2, if Brd _ ID [2:0] is 010 or 011, the chip type is DDR4, the power management unit 110 needs to output three supply paths, i.e., VPP (i.e., active power supply of DDR 4), VDDQ (i.e., data input/output (DQ I/O) power supply of DDR 4), and VTT (i.e., monitor termination voltage for comparing with reference power VRef and determining whether each pin is low), which are 2.5V, 1.2V, and 0.6V, respectively.
In one embodiment, the power management unit 110 is implemented by a Power Management Integrated Circuit (PMIC). In some embodiments, the power management unit 110 may be implemented using a chip having a power management integrated circuit, such as a LP8732 chip from TI corporation, a P8800 chip from IDT corporation, or the like.
In this embodiment, the chip to be tested may be soldered on the mounting site 104, or may be fixed to the test daughter board 102 through a Socket (Socket).
In one embodiment, the chips to be tested mounted to the mounting sites 104 may be chip-shaped chips or chip memory banks. The memory bank puts a plurality of memory chips together to form a universal standard module, adds a management signal into the universal standard module, and then leads out from a standard interface.
In this specific embodiment, the type switch is toggled according to different types of chips to generate different chip identification codes for the test daughter board 102 and the test motherboard 101 to identify. In one embodiment, the mounting sites 104 of the test daughter board 102 include at least one chip, which may be of various types, such as DDR3, DDR3L, DDR4, LPDDR3, LPDDR4, and the like.
Please refer to fig. 4, which is a schematic step diagram of a chip testing method according to an embodiment of the present invention.
In this embodiment, a chip testing method is provided, comprising the steps of: s41, distinguishing the type of the chip to be tested through a chip type distinguisher in the test daughter board, wherein the chip to be tested is installed in an installation position in the test daughter board; s42, the test mainboard configures a physical interface unit and a memory controller according to the type of the chip to be tested, so that the physical interface unit and the memory controller support an interface protocol corresponding to the type of the chip to be tested; s43, the chip to be tested is tested by the physical interface unit and the memory controller configured with the interface protocol.
In one embodiment, the distinguishing the types of the chips to be tested by the chip type discriminator 103 in the test sub-board 102 includes: generating a corresponding chip identification code through a type selector switch according to the type of the chip to be tested mounted on the mounting position 104; the test motherboard 101 configures the physical interface unit 106 and the memory controller 105 according to the type of the chip to be tested, and includes: the test daughter board 102 sends the chip identification code to the test motherboard 101; the control chip 109 in the test motherboard 101 configures the physical interface unit 106 and the memory controller 105 according to the chip identification code.
In one embodiment, the type switch includes a plurality of dial switches, the number of the dial switches is the same as the number of bits of the chip identification code, and the switching status of each dial switch corresponds to the value of one bit of the chip identification code, and the corresponding chip identification code is generated by the type switch, including the following steps: and connecting the dial switch corresponding to each chip identification code to the first voltage or the second voltage to generate a first signal or a second signal to form the chip identification code.
In one specific embodiment, the chip identification code is composed of 0 and 1, which correspond to a low level and a high level respectively and are determined by the access voltage conditions of a plurality of dial switches. In a specific embodiment, the number of the dial switches is the same as the number of the code bits of the chip identification code.
In one embodiment, the number of the toggle switches is at least 3, and each toggle switch corresponds to one code bit of the chip id, so that at least three toggle switches can be used to generate at least 8 different chip ids, and each chip corresponds to at least one chip id.
Specifically, when the figure of dial switch is 3, when needs produced an identification code 001, the dial switch of first code position shifted the second position, is connected to VSS, exports a low level, and the dial switch of second code position shifts the second position, is connected to VSS, exports a low level, and the dial switch of third code position shifts the first position, is connected to VCC, exports a high level.
In this embodiment, the chip type corresponding to each chip identification code is specified in advance. In the testing process, the test motherboard 101 only needs to correspond the received identification code to a specific chip type.
In one embodiment, after the testing of the types of the chips to be tested by the chip type discriminator 103 in the sub-board 102, the method further includes the following steps: transmitting the chip identification code to the first connector 107 in the test main board 101 through the second connector 108 in the test sub board 102; the power management unit 110 in the test motherboard 101 acquires the chip identification code from the first connector 107, and respectively outputs voltages to the control chip 109 and the first connector 107 according to the chip identification code; the first connector 107 provides power to the test daughter board 102 by interacting with the second connector 108.
In a specific embodiment, the chip testing the chip to be tested through the physical interface unit and the memory controller configured with the interface protocol includes the following steps: the memory controller 105 configured with the interface protocol sends an initialization instruction to the test daughter board 102 through the physical interface unit 106; the test daughter board 102 initializes the chip to be tested based on the initialization instruction; the memory controller 105 sends test data to the initialized chip to be tested to perform chip testing on the chip to be tested.
In one embodiment, the method further comprises the following steps: and providing a power supply for the physical interface unit 106, the memory controller 105 and the chip according to the chip identification code, wherein the power of the power supply corresponds to the type of the chip.
In this embodiment, different operating voltages are provided for different kinds of chips by the power management unit 110. Specifically, when testing the DDR4 chip, the power management unit 110 outputs 2.5V to power the DDR4 chip because the operating voltage of the DDR4 chip is 2.5V, and when testing the LPDDR4 chip, the power management unit 110 outputs 1.8V to power the LPDDR4 chip because the operating voltage of the LPDDR4 chip is 1.8V.
When the chip testing method is applied to the actual use process, the following embodiments are provided:
(1) under the state that the power supply of the chip testing system is closed, the testing daughter board 102 and the testing mainboard 101 are connected through the connector 107;
(2) setting the type switch, namely the value of Brd _ ID [2:0], according to the type of the chip to be tested installed on the test daughter board 102 and the predefined corresponding relation;
(3) powering on a chip test system;
(4) the power management unit 110 adjusts the output level according to the value of the type switch on the test daughter board; for example, when the chip corresponding to the value of the type switch output is the DDR4 type, the output VPP is 2.5V, VDDQ is 1.2V, and VTT is 0.6V; when the chip corresponding to the value output by the type switch is of the LPDDR4 type, the output VDD1 is 1.8V, VDD2 is 1.1V, and VDDQ is 1.1V;
(5) the control chip 109 of the test motherboard 101 configures parameters of the memory controller 105 and the physical interface unit 106 according to the value output by the type switch; for example; when the chip corresponding to the value output by the type switch is the DDR3 type, the memory controller 105 and the physical interface unit 106 are configured in the DDR3 mode; when the chip corresponding to the value outputted from the type switcher is LPDDR4, the memory controller 105 and the physical interface unit 106 are configured in the LPDDR4 mode;
(6) the control chip 109 of the test motherboard 101 performs initialization operation, starts DDR training (DDR training), performs functional test, and the like;
(7) the control chip 109 of the test mainboard 101 verifies the function and performance of the chip;
(8) and (4) powering off the chip testing system, replacing the chip to be tested and the corresponding testing daughter board 102, and repeating the steps (1) to (7).
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A chip test system, comprising:
the test mainboard is used for configuring the physical interface unit and the memory controller according to the type of the chip to be tested;
the test daughter board is provided with a chip type discriminator and a mounting position, wherein the chip type discriminator is used for discriminating the type of the chip to be tested, and the mounting position is used for mounting the chip to be tested;
the test mainboard is electrically connected with the test daughter board.
2. The chip test system according to claim 1, wherein the test motherboard further comprises: a first connector connected to the physical interface unit; the test daughter board further includes: a second connector connected to the chip type discriminator and the mounting site, and electrically connected to the first connector; the first connector and the second connector are used for establishing interaction between the test main board and the test sub-board.
3. The chip test system according to claim 2, wherein the test motherboard comprises: the physical interface unit and the memory controller are arranged in the control chip, and the control chip is used for configuring the physical interface unit and the memory controller so that the physical interface unit and the memory controller are configured correspondingly to different types of chips to be tested;
the control chip is connected with the first connector through the physical interface unit.
4. The chip test system according to claim 3, wherein the test motherboard further comprises: and the power management unit is electrically connected to the first connector and the control chip and is used for respectively outputting voltage to the control chip and the first connector according to the type of the chip to be tested.
5. The chip test system according to claim 1, wherein the chip kind discriminator comprises:
the type switch is used for generating a corresponding chip identification code according to the type of the chip to be tested installed on the installation position;
the test daughter board is further configured to send the chip identification code to the test motherboard, and the test motherboard is configured to configure the physical interface unit and the memory controller according to the chip identification code.
6. The chip test system according to claim 5, wherein the type switch comprises a plurality of dial switches, the number of the dial switches is the same as the number of bits of the chip identification code, and the switch status of each dial switch corresponds to the value of one-bit chip identification code.
7. The chip testing system of claim 6, wherein the number of the dial switches is 3 to generate 8 different three-bit chip identification codes, and each kind of chip to be tested corresponds to at least one chip identification code.
8. The chip testing system according to claim 1, wherein the mounting locations are provided with pin connection locations, and each of the pin connection locations corresponds to a pin of the chip to be tested.
9. The chip test system according to any one of claims 1 to 8, wherein the test daughter board is detachably connected to the test motherboard.
10. The chip test system of claim 2, wherein the first connector comprises at least one of a DDR4 SO-DIMM connector or a PCIe connector, and the second connector comprises at least one of a DDR4 SO-DIMM connector or a PCIe connector.
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| CN112562778A (en) * | 2020-12-21 | 2021-03-26 | 合肥悦芯半导体科技有限公司 | Test circuit and test system |
| CN113009316A (en) * | 2021-02-20 | 2021-06-22 | 上海燧原科技有限公司 | Interface conversion circuit, multi-chip interconnection system and test method thereof |
| CN114089162A (en) * | 2021-11-22 | 2022-02-25 | 惠州视维新技术有限公司 | TCON chip testing method and device and storage medium |
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| CN112562778A (en) * | 2020-12-21 | 2021-03-26 | 合肥悦芯半导体科技有限公司 | Test circuit and test system |
| CN112505467A (en) * | 2021-01-29 | 2021-03-16 | 北京智芯微电子科技有限公司 | Testing device and testing method for chip electromagnetic interference test |
| CN113009316A (en) * | 2021-02-20 | 2021-06-22 | 上海燧原科技有限公司 | Interface conversion circuit, multi-chip interconnection system and test method thereof |
| CN114089162A (en) * | 2021-11-22 | 2022-02-25 | 惠州视维新技术有限公司 | TCON chip testing method and device and storage medium |
| CN114089162B (en) * | 2021-11-22 | 2023-12-05 | 惠州视维新技术有限公司 | TCON chip test method, device and storage medium |
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