CN207008593U - A kind of server isomery memory device - Google Patents

Abstract

The utility model provides a kind of server isomery memory device, including 2000T fpga chips, 690T fpga chips and High speed rear panel connector；The quantity of the 2000T fpga chips is at least one, and the ratio of number of the 2000T fpga chips, 690T fpga chips and High speed rear panel connector is 1：1：2；Described 2000T fpga chips connect the High speed rear panel connector described in two each via bus；Described 2000T fpga chips are connected each via NI buses with the 690T fpga chips described in one；Described 690T fpga chips are each connected with nonvolatile memory NVM.The utility model improves the memory rate of isomery internal memory, and also has non-volatile.

Description

A kind of server isomery memory device

Technical field

Multipath server field is the utility model is related to, specifically a kind of server isomery memory device.

Background technology

With the continuous development of computer technology, processing speed is continuously increased, and the requirement to internal memory is also more and more higher, different Structure internal memory arises at the historic moment.

And existing isomery internal memory is realized in a manner of DRAM and flash mixing internal memories more, power-off data are volatile and data are deposited Take speed relatively slow.

Therefore, the utility model proposes a kind of new hardware implementations of isomery internal memory, for preventing data from powering off Lose, and for improving the data access rate of isomery internal memory.

Utility model content

Technical problem to be solved in the utility model is, for problems of the prior art, there is provided one kind service Device isomery memory device, for preventing data power-off from losing, and for improving the access rate of isomery internal memory.

In order to solve the above technical problems, the utility model provides a kind of server isomery memory device, including 2000T Fpga chip, 690T fpga chips, High speed rear panel connector and a CPLD chips；

The quantity of the 2000T fpga chips is at least one, the 2000T fpga chips, 690T fpga chips and The ratio of number of High speed rear panel connector is 1：1：2；

The High speed rear panel that described 2000T fpga chips connect described in two each via QPI buses or UPI buses connects Connect device；Described 2000T fpga chips are connected each via NI buses with the 690T fpga chips described in one；

The described connection of CPLD chips each described 2000T fpga chips and 690T fpga chips；

Described 690T fpga chips are each connected with nonvolatile memory NVM.

Wherein, each described 2000T fpga chips, be each connected with an asynchronous receiving-transmitting transmitter UART, two RDIMM memory modules and a FLASH chip for being used to store its configuration parameter.

Wherein, each described 690T fpga chips, be each connected with an asynchronous receiving-transmitting transmitter UART, one SODIMM memory modules and a FLASH chip for being used to store its configuration parameter.

Wherein, the quantity of the 2000T fpga chips, 690T fpga chips and High speed rear panel connector is followed successively by：2 It is individual, 2 and 4.

Each described 2000T fpga chips are connected by two NI buses with corresponding 690T fpga chips respectively.

Described 2000T fpga chips, 690T fpga chips, High speed rear panel connector, CPLD chips and non-volatile Memory NVM, it is integrated on same circuit board.

Compared with prior art, the utility model has the advantage of：

The utility model provides a kind of new server isomery memory device, have it is non-volatile, and can be certain The data access rate of isomery internal memory is improved in degree.

As can be seen here, the utility model compared with prior art, has substantive distinguishing features and progress, its beneficial effect implemented Fruit is also obvious.

Brief description of the drawings

Fig. 1 is the circuit diagram of server isomery memory device described in the utility model.

Fig. 2 uses wiring schematic diagram for server isomery memory device described in the utility model.

Wherein：1- circuit boards.

Embodiment

To make the technical solution of the utility model and advantage clearer, below in conjunction with accompanying drawing, to of the present utility model Technical scheme is clearly and completely described.

Fig. 1 is a kind of embodiment of server isomery memory device described in the utility model.In this specific implementation In mode, described server isomery memory device, including two 2000T fpga chips, two 690T fpga chips and four Individual High speed rear panel connector.High speed rear panel connector described in 4, two-by-two each via QPI buses and same described 2000T Fpga chip is connected.2000T fpga chips described in two and the 690T fpga chips described in two correspond, each 2000T fpga chips are connected by two NI buses with corresponding 690T fpga chips respectively.Described 690T fpga chips Each it is connected with nonvolatile memory NVM.Book server isomery memory device also includes a CPLD chips, CPLD chips connection Above-mentioned two 2000T fpga chips and two 690T fpga chips, for control above-mentioned two 2000T fpga chips and The sequential of two 690T fpga chips.

Wherein, in this embodiment, each described 2000T fpga chips, are each connected with an asynchronous receiving-transmitting Transmitter UART, two RDIMM memory modules and one are used for the FLASH chip for storing its configuration parameter.

Wherein, in this embodiment, each described 690T fpga chips, are each connected with an asynchronous receiving-transmitting Transmitter UART, a SODIMM memory modules and one are used for the FLASH chip for storing its configuration parameter.

Wherein, in the present embodiment, described 2000T fpga chips, 690T fpga chips, High speed rear panel connection Device, CPLD chips and nonvolatile memory NVM, it is integrated on same circuit board 1.

Wherein, as shown in Figure 1, 2, each FLASH chip corresponds to it and connects the configuration parameter memory space of fpga chip, After upper electricity, configuration information is loaded to corresponding fpga chip for corresponding, carries out the initialization of corresponding fpga chip；UART is corresponded to It connects the debugging interface of fpga chip, and SODIMM, RDIMM are small in-line memory modules, register straight cutting respectively Formula memory modules, the operating space to should be used as corresponding FPGA.

Wherein, 2000T fpga chips involved in the utility model are Virtex-7 2000T fpga chips, institute The 690T fpga chips being related to are Virtex-7 690T fpga chips.In addition, the High speed rear panel described in present embodiment Connector uses XCede back panel connectors.

Before use, the High speed rear panel connector described in aforementioned four is first connected to CPU BOARD by backboard BP （CPU board）, the connection of the High speed rear panel connector and 4 road CPU on CPU board described in aforementioned four is realized, wherein on CPU board Each CPU is connected with two MEMORY respectively（That is memory）, as shown in Figure 2.After power down, 4 road CPU interconnect path by 8 by QPI Data in individual MEMORY internal memories are sent into 2000T fpga chips, and carrying out data format through described 2000T fpga chips turns Change, afterwards by the MEMORY data after form is changed, 690T fpga chips are transmitted to by NI buses, through 690T FPGA cores In piece deposit nonvolatile memory NVM；After power up, data are passed back described from nonvolatile memory NVM In MEMORY, state when making the server return to power down, so as to which prestissimo works on again.It can be seen that use the utility model Described server isomery memory device, it is ensured that data it is non-volatile, also improve the data read rates of isomery internal memory.

Embodiment of above is only to illustrate the technical solution of the utility model, rather than its limitations；Although with reference to foregoing The utility model is described in detail embodiment, it will be understood by those within the art that：It still can be with Technical scheme described in foregoing each embodiment is modified, or equivalent substitution is carried out to which part technical characteristic； And these modifications or replacement, the essence of appropriate technical solution is departed from each embodiment technical scheme of the utility model Scope.

Claims (6)

1. A kind of 1. server isomery memory device, it is characterised in that：

   Including 2000T fpga chips, 690T fpga chips, High speed rear panel connector and a CPLD chips；

   The quantity of the 2000T fpga chips is at least one, the 2000T fpga chips, 690T fpga chips and high speed The ratio of number of back panel connector is 1：1：2；

   Described 2000T fpga chips connect the High speed rear panel connector described in two each via QPI buses or UPI buses； Described 2000T fpga chips are connected each via NI buses with the 690T fpga chips described in one；

   The described connection of CPLD chips each described 2000T fpga chips and 690T fpga chips；

   Described 690T fpga chips are each connected with nonvolatile memory NVM.
2. 2. server isomery memory device according to claim 1, it is characterised in that：

   Each described 2000T fpga chips, are each connected with an asynchronous receiving-transmitting transmitter UART, two RDIMM memory modules With a FLASH chip for being used to store its configuration parameter.
3. 3. server isomery memory device according to claim 1 or 2, it is characterised in that：

   Each described 690T fpga chips, are each connected with an asynchronous receiving-transmitting transmitter UART, a SODIMM memory modules With a FLASH chip for being used to store its configuration parameter.
4. 4. server isomery memory device according to claim 1 or 2, it is characterised in that：

   The quantity of the 2000T fpga chips, 690T fpga chips and High speed rear panel connector is followed successively by：2,2 and 4 It is individual.
5. 5. server isomery memory device according to claim 1 or 2, it is characterised in that：

   Each described 2000T fpga chips are connected by two NI buses with corresponding 690T fpga chips respectively.
6. 6. server isomery memory device according to claim 1 or 2, it is characterised in that：

   Described 2000T fpga chips, 690T fpga chips, High speed rear panel connector, CPLD chips and non-volatile memories Device NVM, it is integrated in same circuit board（1）On.