WO2019052061A1 - Low-power consumption dual in-line memory, and enhanced driving method therefor - Google Patents

Low-power consumption dual in-line memory, and enhanced driving method therefor Download PDF

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Publication number
WO2019052061A1
WO2019052061A1 PCT/CN2017/116580 CN2017116580W WO2019052061A1 WO 2019052061 A1 WO2019052061 A1 WO 2019052061A1 CN 2017116580 W CN2017116580 W CN 2017116580W WO 2019052061 A1 WO2019052061 A1 WO 2019052061A1
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WIPO (PCT)
Prior art keywords
memory
line
pin
power supply
dual
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PCT/CN2017/116580
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French (fr)
Chinese (zh)
Inventor
肖浩
李志雄
邓恩华
吴方
卢浩
龙红卫
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深圳市江波龙电子有限公司
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Publication of WO2019052061A1 publication Critical patent/WO2019052061A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • This application belongs to the field of electronics, and in particular, to a low power dual in-line memory and an enhanced driving method thereof.
  • DRAM Dynamic Random Access Memory
  • the purpose of the embodiments of the present application is to provide a low-power dual in-line memory, which is intended to solve the problem that the existing memory interface specifications are not unified, and the compatibility of the low-power storage device cannot be realized, and the master control Support for large-capacity, plug-and-play upgrade requirements under the premise of support.
  • the embodiment of the present application is implemented as follows, a low power dual in-line memory, the memory is a pluggable dual in-line structure, compatible with a DDR memory interface, and the memory is based on low power consumption.
  • the D DR4 SO-DIMM interface of the memory chip is based on signal integrity and power integrity as follows:
  • the power supply pin and the grounding pin of the memory pass through a data line to the DDR4 SO-DIMM interface
  • the two ends of the control line and the address line are newly allocated, so that the routing, data lines, control lines, and address lines are separated by the power pin and the ground pin;
  • the power supply pin I and the grounding pin I of the memory are allocated in a certain ratio.
  • Another object of the present application is to provide an enhanced driving method based on the above-described low power dual in-line memory, characterized in that the method comprises the following steps:
  • control line, the address line, and the I/O port are respectively pulled up on the PCB of the platform and the low power dual in-line memory, and the termination voltage is obtained by dividing the reference voltage.
  • the LDM in the embodiment of the present application utilizes the existing notebook memory interface specification DDR4.
  • SO-DIMM (260 pin), which defines LPDDR2/3/4 on this interface specification, realizes the low power consumption, large capacity and plug-and-play requirements that current users should have for memory.
  • FIG. 1 is a structural diagram of a low power dual in-line memory provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a control line, an address line, and a pull-up structure of an I/O port of a low power dual in-line memory according to an embodiment of the present application;
  • FIG 3 is a schematic diagram of a pull-up structure of a data line of a low power dual in-line memory according to an embodiment of the present application.
  • the embodiment of the present application utilizes the existing notebook memory interface specification DDR4 SO-DIMM (260 pin)
  • LPDDR2/3/4 is defined on this interface specification to achieve low power consumption, large capacity and plug and play requirements.
  • FIG. 1 shows a structure of a low power dual in-line memory provided by an embodiment of the present application, for convenience. The only parts related to the present application are shown.
  • the low power dual in-line memory (LDM, Low Power)
  • Dual-Inline-Memory-Modules for pluggable dual in-line architecture, compatible with DDR memory interface, memory based on low power memory chip (LPDDR series) DDR4 SO-DIMM interface for signal integrity and power integrity Do the following pin assignments for the principle:
  • the power supply pin and the grounding pin of the memory pass through the data line (DQn, n is a natural number representative serial number), the control line and the address line (CAn, n is a natural number representative serial number) of the DDR4 SO-DIMM interface. Obtained from the new distribution, so that the routing data lines, control lines, and address lines are isolated from the power pins and ground pins.
  • the power supply pin and the grounding pin of the memory are allocated in a certain ratio to ensure the integrity of the memory power supply.
  • the design is based on the DDR4 SO-DIMM interface of the low power consumption memory chip (LPDDR series), and the design parameters are as shown in Table 1:
  • the DDR4 SO-DIMM interface of the low-power memory chip is pin-distributed on the principle of maintaining signal integrity and power integrity.
  • the power supply pin of the low-power dual in-line memory includes the first power supply. Pin VDD1, second power pin VDD2, and third power pin VSS.
  • the first power pin VDD1, the second power pin VDD2, the third power pin VSS, and the ground pin are evenly distributed on the data line (DQn) and the control line and the address line (Can), so that the wiring ⁇ data line and The control line and the address line are isolated by power and ground, and the signal integrity is optimal.
  • the power pin and the ground pin are allocated according to a certain ratio, which can ensure sufficient power integrity of the memory module.
  • Low power consumption The memory chip (LPDDR series) is extracted according to the above principles through the standard DDR4 SO-DIMM interface, and the interface compatible with the DDR memory module can be plugged and unplugged.
  • the chip select pins such as CS0_n, CS1_n, CS2_n, etc. of the low power chip control the capacity of the memory module, and one CS signal represents a specific storage unit. The more the signal, the larger the capacity. Online upgrade can be achieved by drawing more CS signal memory modules.
  • the PCB terminal pin of the memory is obtained by pulling up the control line, the address line, and the I/O port of the DDR4 SO-DIMM interface, and the termination voltage is obtained by dividing the voltage by the reference voltage.
  • the clock pin I of the low power dual in-line memory can transmit the Cloc k (clock clock) signal through the packet signal line, thereby reducing interference and improving the accuracy of the cuckoo clock.
  • the length of the connection between the corresponding memory pin and the main board after the multiplexed control line/address line is allocated is greater than the length of the data line, thereby ensuring that data reading and writing is sufficiently established and maintained.
  • the LPDDR series is mainly used in low-power consumer electronic products, the driving capability of the I/O port itself is limited, and the control and address lines are long in the layout process, and the signal attenuation is severe.
  • control line, the address line, and the I/O port are pulled up on the PCB board designed on the platform and the LDM, and are pulled up by the pull-up resistors R94-R109, where CKE0 and CKE1 are both Cuckoo clock enable line
  • CKE0 and CKE1 are high level, activate the internal clock circuit, input buffer and output drive, and low level to turn off the corresponding circuit. Enter or exit the power saving mode by flipping the CKE0 and CKE1 signals.
  • the E0 and CKE1 signals are part of the instruction code, and each channel has a corresponding CKE signal.
  • the number of pull-up resistors corresponds to the number of selectable pull-up control lines, address lines, and I/O ports, wherein the termination voltage VTT_CA is obtained by dividing the voltage by the associated reference voltage VCORE_1.2.
  • the specific components of the voltage divider circuit include:
  • resistor R110 resistor Rl l l, capacitor C276, capacitor C277, capacitor C278;
  • the resistor Rl l l, the capacitor C276, the capacitor C277, the capacitor C278 are connected in parallel, a common terminal grounded in parallel, and the other common terminal is a terminal voltage VTT_CA output terminal is connected with one end of the resistor R110, the resistor R11
  • the other end of 0 is connected to the reference voltage VCORE_l .2.
  • the voltage divider circuit specifically includes:
  • the resistor R113, the capacitor C279, the capacitor C280, the capacitor C281 are connected in parallel, a common terminal is connected in parallel, and the other common terminal is a terminal voltage VTT_DQ output terminal is connected to one end of the resistor R112, the resistor R11
  • the other end of 2 is connected to the reference voltage VCORE_l .2.
  • Another object of the embodiments of the present application is to provide an enhanced driving method based on the low power dual in-line memory in the above embodiment, the method comprising the following steps:
  • the method further includes:
  • the method further includes:
  • S103 Set a multiplexed control line/address line to allocate a corresponding length of the memory cable to the motherboard to be greater than a data line length.
  • the LPDDR series is mainly used in low-power consumer electronic products.
  • the driving capability of the I/O port itself is limited.
  • the control and address lines are long in the layout process, and the signal attenuation is severe.
  • control line, the address line, and the I/O port are pulled up on the PCB designed on the platform and the LDM, and the number of pull-up resistors and the selectable pull-up control line, address line, and The number of I/O ports corresponds, wherein the termination voltage VTT_CA is obtained by dividing the voltage by the associated reference voltage VC0RE_1.2, in combination with FIG.
  • the driving ability of the external host and the memory itself is limited, and the line length of the layout data line in the actual application has far exceeded the line length of the public PCB, so the optimization is performed.
  • the data I/O is pulled up at the external host and the LDM end of the memory, and the appropriate termination voltage is obtained by changing the voltage dividing resistor, and the ODT (On-die Termination) is terminated. ) Pull up to VTT_DQ, and change the resistance of the pull-up resistor to get strong drive capability, combined with Figure 3.
  • the embodiment of the present application reasonably allocates the interface definition of LPDDR2/3/4 on the basis of the existing DDR4 SO-DIMM (standard 69.6*30mm size or 69.6*20mm small size) interface specification, so that the LDM can be Maintain signal integrity and power integrity in high-speed work environments. Since JEDEC has SPD support, this technology is mainly a hardware implementation.
  • the embodiment of the present application utilizes the existing notebook memory interface specification DDR4 SO-DIMM (260 pin)
  • LPDDR2/3/4 is defined on this interface specification to achieve low power consumption, large capacity and plug and play requirements.

Abstract

A low-power consumption dual in-line memory, and an enhanced driving method therefor. The memory has a pluggable dual in-line structure and is compatible with a DDR internal memory interface. The memory has the following pin assignment based on a DDR4 SO-DIMM interface of a low-power consumption internal memory chip, and by means of taking signal integrity and power supply integrity as principles: a power supply pin and a grounding pin of the memory are obtained by re-assigning two ends of a data line, a control line and an address line of the DDR4 SO-DIMM interface, so that the data line, the control line and the address line are isolated by means of the power supply pin and the grounding pin during wire arrangement; and the power supply pin and the grounding pin of the memory are assigned according to a certain proportion. The present invention uses an existing notebook internal memory interface specification DDR4SO-DIMM to define an LPDDR 2/3/4 on the interface specification, thereby meeting the requirements of a low power consumption, a large capacity and plug-and-play.

Description

一种氏功耗双列直插式存储器及其增强驱动方法  Power consumption dual in-line memory and enhanced driving method thereof
[0001] [0001]
技术领域  Technical field
[0002] 本申请属于电子领域， 尤其涉及一种低功耗双列直插式存储器及其增强驱动方 法。  [0002] This application belongs to the field of electronics, and in particular, to a low power dual in-line memory and an enhanced driving method thereof.
背景技术  Background technique
[0003] 随着 PC、 手机等消费类电子产品集成度越来越高， 并且向着小型化的方向不断 迈进， 消费者对各类 3C产品中的内存模块提出了更大的容量、 更低的功耗以及 满足即插即用随吋更换的需求。 然而内存从 DRAM (Dynamic Random Access Memory, 移动动态随机存取存储器） 发展到如今主流的 DDR3、 DDR4、 LPDDR 3以及 LPDDR4, 却依然没有一种统一的接口规范来对内存进行随吋更换随吋升 级。  [0003] With the increasing integration of consumer electronic products such as PCs and mobile phones, and moving toward miniaturization, consumers have put forward more capacity and lower memory modules in various 3C products. Power consumption and the need to replace plug-and-play. However, memory has evolved from DRAM (Dynamic Random Access Memory) to today's mainstream DDR3, DDR4, LPDDR 3 and LPDDR4, but there is still no uniform interface specification for subsequent replacement of memory. .
[0004] 目前为止像 PC等消费类电子产品的内存模块 JEDEC已定义了 DDR3 SO-DIMM  [0004] Memory modules like consumer electronics such as PCs have so far defined DDR3 SO-DIMMs.
(Small Outline Dual In-line Memory Module： 小外形双列内存模组） 以及 DDR4 SO-DIMM的接口规范， 且有标准的 SPD (Serial Presence Detect, 模组存在的串 行检测） 进行支持， 而针对低功耗系列的 Mobile DRAM系列却未有相应的内存 模组接口规范支持， 且只定义了 SPD信息。 无法实现低功耗存储设备的兼容性， 以及在主控支持的前提下满足大容量、 即插即用的升级需求。  (Small Outline Dual In-line Memory Module) and DDR4 SO-DIMM interface specifications, and standard SPD (Serial Presence Detect) is supported. The low-power series of Mobile DRAM series does not have the corresponding memory module interface specification support, and only SPD information is defined. The compatibility of low-power storage devices cannot be achieved, and large-capacity, plug-and-play upgrade requirements are met with the support of the main control.
[0005] 发明内容 SUMMARY OF THE INVENTION
[0006] 本申请实施例的目的在于提供一种低功耗双列直插式存储器， 旨在解决现有内 存接口规范不统一导致， 无法实现低功耗存储设备的兼容性， 以及在主控支持 的前提下满足大容量、 即插即用的升级需求的问题。  [0006] The purpose of the embodiments of the present application is to provide a low-power dual in-line memory, which is intended to solve the problem that the existing memory interface specifications are not unified, and the compatibility of the low-power storage device cannot be realized, and the master control Support for large-capacity, plug-and-play upgrade requirements under the premise of support.
[0007] 本申请实施例是这样实现的， 一种低功耗双列直插式存储器， 所述存储器为可 插拔双列直插式结构， 兼容 DDR内存接口， 所述存储器基于低功耗内存芯片的 D DR4 SO-DIMM接口以信号完整性和电源完整性为原则做如下引脚分配：  [0007] The embodiment of the present application is implemented as follows, a low power dual in-line memory, the memory is a pluggable dual in-line structure, compatible with a DDR memory interface, and the memory is based on low power consumption. The D DR4 SO-DIMM interface of the memory chip is based on signal integrity and power integrity as follows:
[0008] 所述存储器的电源引脚和接地弓 I脚通过对所述 DDR4 SO-DIMM接口的数据线 、 控制线和地址线的两端从新分配得到， 使布线吋数据线、 控制线、 地址线通 过电源引脚和接地引脚隔离； [0008] The power supply pin and the grounding pin of the memory pass through a data line to the DDR4 SO-DIMM interface The two ends of the control line and the address line are newly allocated, so that the routing, data lines, control lines, and address lines are separated by the power pin and the ground pin;
[0009] 所述存储器的电源弓 I脚和接地弓 I脚按一定的比例进行分配。  [0009] The power supply pin I and the grounding pin I of the memory are allocated in a certain ratio.
[0010] 本申请实施例的另一目的在于提供一种基于上述的低功耗双列直插式存储器的 增强驱动方法， 其特征在于， 所述方法包括下述步骤：  Another object of the present application is to provide an enhanced driving method based on the above-described low power dual in-line memory, characterized in that the method comprises the following steps:
[0011] 分别在平台和低功耗双列直插式存储器的 PCB板上将控制线、 地址线以及 I/O口 进行上拉处理， 且通过对参考电压进行分压得到端接电压。  [0011] The control line, the address line, and the I/O port are respectively pulled up on the PCB of the platform and the low power dual in-line memory, and the termination voltage is obtained by dividing the reference voltage.
[0012] 本申请实施例中的 LDM利用了现有的笔记本内存接口规格 DDR4  [0012] The LDM in the embodiment of the present application utilizes the existing notebook memory interface specification DDR4.
SO-DIMM (260 pin) ， 将 LPDDR2/3/4定义在此接口规范上， 实现了当前用户对 内存应具有的低功耗、 大容量以及即插即用的需求。  SO-DIMM (260 pin), which defines LPDDR2/3/4 on this interface specification, realizes the low power consumption, large capacity and plug-and-play requirements that current users should have for memory.
[0013]  [0013]
对附图的简要说明 Brief description of the drawing
附图说明  DRAWINGS
[0014] 图 1为本申请实施例提供的低功耗双列直插式存储器的结构图；  1 is a structural diagram of a low power dual in-line memory provided by an embodiment of the present application;
[0015] 图 2为本申请实施例提供的低功耗双列直插式存储器的控制线、 地址线以及 I/O 口的上拉结构示意图；  2 is a schematic diagram of a control line, an address line, and a pull-up structure of an I/O port of a low power dual in-line memory according to an embodiment of the present application;
[0016] 图 3为本申请实施例提供的低功耗双列直插式存储器的数据线的上拉结构示意 图。  3 is a schematic diagram of a pull-up structure of a data line of a low power dual in-line memory according to an embodiment of the present application.
[0017] 具体实施方式  DETAILED DESCRIPTION
[0018] 为了使本申请的目的、 技术方案及优点更加清楚明白， 以下结合附图及实施例 ， 对本申请进行进一步详细说明。 应当理解， 此处所描述的具体实施例仅仅用 以解释本申请， 并不用于限定本申请。 此外， 下面所描述的本申请各个实施方 式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。  [0018] In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting. Further, the technical features referred to in the respective embodiments of the present application described below may be combined with each other as long as they do not constitute a conflict with each other.
[0019] 本申请实施例利用了现有的笔记本内存接口规格 DDR4 SO-DIMM (260 pin) [0019] The embodiment of the present application utilizes the existing notebook memory interface specification DDR4 SO-DIMM (260 pin)
， 将 LPDDR2/3/4定义在此接口规范上， 实现低功耗、 大容量以及即插即用的需 求。 , LPDDR2/3/4 is defined on this interface specification to achieve low power consumption, large capacity and plug and play requirements.
[0020] 图 1示出了本申请实施例提供的低功耗双列直插式存储器的结构， 为了便于说 明， 仅示出了与本申请相关的部分。 [0020] FIG. 1 shows a structure of a low power dual in-line memory provided by an embodiment of the present application, for convenience. The only parts related to the present application are shown.
[0021] 作为本申请一实施例， 该低功耗双列直插式存储器 （LDM， Low Power [0021] As an embodiment of the present application, the low power dual in-line memory (LDM, Low Power)
Dual-Inline-Memory-Modules ) 为可插拔双列直插式结构， 兼容 DDR内存接口， 存储器基于低功耗内存芯片 （LPDDR系列） 的 DDR4 SO-DIMM接口， 以信号完 整性和电源完整性为原则做如下引脚分配：  Dual-Inline-Memory-Modules for pluggable dual in-line architecture, compatible with DDR memory interface, memory based on low power memory chip (LPDDR series) DDR4 SO-DIMM interface for signal integrity and power integrity Do the following pin assignments for the principle:
[0022] 存储器的电源引脚和接地弓 I脚通过对 DDR4 SO-DIMM接口的数据线 （DQn， n 为自然数代表序号） 、 控制线和地址线 （CAn， n为自然数代表序号） 的两端从 新分配得到， 使布线吋数据线、 控制线、 地址线通过电源引脚和接地引脚隔离[0022] The power supply pin and the grounding pin of the memory pass through the data line (DQn, n is a natural number representative serial number), the control line and the address line (CAn, n is a natural number representative serial number) of the DDR4 SO-DIMM interface. Obtained from the new distribution, so that the routing data lines, control lines, and address lines are isolated from the power pins and ground pins.
， 从而保证信号的完整性； To ensure signal integrity;
[0023] 存储器的电源引脚和接地弓 I脚按一定的比例进行分配， 以保证存储器电源的完 整性。 [0023] The power supply pin and the grounding pin of the memory are allocated in a certain ratio to ensure the integrity of the memory power supply.
[0024] 在本申请实施例中， 基于低功耗内存芯片 （LPDDR系列） 的 DDR4 SO-DIMM 接口进行设计， 设计参数如表 1所示：  [0024] In the embodiment of the present application, the design is based on the DDR4 SO-DIMM interface of the low power consumption memory chip (LPDDR series), and the design parameters are as shown in Table 1:
[0025] [表 1] [Table 1]
Figure imgf000005_0001
Figure imgf000005_0001
以保持信号完整性以及电源完整性为原则对低功耗内存芯片 （LPDDR系列） 的 DDR4 SO-DIMM接口进行引脚分配， 低功耗双列直插式存储器的电源引脚包 括第一电源引脚 VDD1、 第二电源引脚 VDD2、 第三电源引脚 VSS。 第一电源引 脚 VDD1、 第二电源引脚 VDD2、 第三电源引脚 VSS以及接地引脚均匀分配在数 据线 （DQn) 和控制线、 地址线 （Can) 两端， 使得布线吋数据线和控制线、 地 址线有电源和地进行隔离， 信号完整性做到最优， 另外电源引脚和接地引脚按 一定的比例进行分配， 可以保证内存模组工作吋有足够的电源完整性。 低功耗 内存芯片 （LPDDR系列） 通过标准的 DDR4 SO-DIMM接口按上述的原则进行引 出， 兼容 DDR内存条的接口， 能够做到随吋插拔。 The DDR4 SO-DIMM interface of the low-power memory chip (LPDDR series) is pin-distributed on the principle of maintaining signal integrity and power integrity. The power supply pin of the low-power dual in-line memory includes the first power supply. Pin VDD1, second power pin VDD2, and third power pin VSS. The first power pin VDD1, the second power pin VDD2, the third power pin VSS, and the ground pin are evenly distributed on the data line (DQn) and the control line and the address line (Can), so that the wiring 吋 data line and The control line and the address line are isolated by power and ground, and the signal integrity is optimal. In addition, the power pin and the ground pin are allocated according to a certain ratio, which can ensure sufficient power integrity of the memory module. Low power consumption The memory chip (LPDDR series) is extracted according to the above principles through the standard DDR4 SO-DIMM interface, and the interface compatible with the DDR memory module can be plugged and unplugged.
[0027] 在本申请实施例中， 低功耗芯片的 CS0_n、 CSl_n、 CS2_n…等片选引脚控制内 存模组的容量， 一个 CS信号代表特定的存储单元， 该信号越多， 容量越大， 通 过引出更多的 CS信号内存模组可以做到在线升级。 [0027] In the embodiment of the present application, the chip select pins such as CS0_n, CS1_n, CS2_n, etc. of the low power chip control the capacity of the memory module, and one CS signal represents a specific storage unit. The more the signal, the larger the capacity. Online upgrade can be achieved by drawing more CS signal memory modules.
[0028] 优选地， 存储器的 PCB端引脚通过对 DDR4 SO-DIMM接口的控制线、 地址线以 及 I/O口上拉得到， 且端接电压通过参考电压进行分压得到。 [0028] Preferably, the PCB terminal pin of the memory is obtained by pulling up the control line, the address line, and the I/O port of the DDR4 SO-DIMM interface, and the termination voltage is obtained by dividing the voltage by the reference voltage.
[0029] 优选地， 可以将低功耗双列直插式存储器的吋钟弓 I脚通过包地信号线传输 Cloc k (吋钟） 信号， 从而减少干扰， 提高吋钟的精确度。 [0029] Preferably, the clock pin I of the low power dual in-line memory can transmit the Cloc k (clock clock) signal through the packet signal line, thereby reducing interference and improving the accuracy of the cuckoo clock.
[0030] 另外， 还可以使复用的控制线 /地址线分配后对应的存储器引脚与主板连接的 走线长度大于数据线长度， 从而保证数据读写吋有足够的建立、 保持吋间。 [0030] In addition, the length of the connection between the corresponding memory pin and the main board after the multiplexed control line/address line is allocated is greater than the length of the data line, thereby ensuring that data reading and writing is sufficiently established and maintained.
[0031] 由于 LPDDR系列主要应用在低功耗的消费类电子产品中， 本身 I/O口的驱动能 力有限， 控制、 地址线在 layout过程中走线比较长， 信号衰减严重， [0031] Since the LPDDR series is mainly used in low-power consumer electronic products, the driving capability of the I/O port itself is limited, and the control and address lines are long in the layout process, and the signal attenuation is severe.
[0032] 为此在设计吋在平台和 LDM的 PCB板上将控制线、 地址线以及 I/O口进行了上 拉处理， 通过上拉电阻 R94-R109进行上拉， 其中 CKE0、 CKE1均为吋钟使能线[0032] For this reason, the control line, the address line, and the I/O port are pulled up on the PCB board designed on the platform and the LDM, and are pulled up by the pull-up resistors R94-R109, where CKE0 and CKE1 are both Cuckoo clock enable line
， CKE0、 CKE1为高电平吋激活内部吋钟电路、 输入缓冲及输出驱动， 低电平 吋则关闭相应电路。 通过 CKE0、 CKE1信号的翻转进入或者退出省电模式。 CKCKE0 and CKE1 are high level, activate the internal clock circuit, input buffer and output drive, and low level to turn off the corresponding circuit. Enter or exit the power saving mode by flipping the CKE0 and CKE1 signals. CK
E0、 CKE1信号是指令码的一部分， 每个通道都有对应的 CKE信号。 The E0 and CKE1 signals are part of the instruction code, and each channel has a corresponding CKE signal.
[0033] 并且， 上拉电阻的数量与可选择上拉的控制线、 地址线以及 I/O口数量对应， 其中端接电压 VTT_CA通过相关的参考电压 VCORE_l .2进行分压得到， 结合图 2[0033] Moreover, the number of pull-up resistors corresponds to the number of selectable pull-up control lines, address lines, and I/O ports, wherein the termination voltage VTT_CA is obtained by dividing the voltage by the associated reference voltage VCORE_1.2.
， 分压电路的具体包括： The specific components of the voltage divider circuit include:
[0034] 电阻 R110、 电阻 Rl l l、 电容 C276、 电容 C277、 电容 C278; [0034] resistor R110, resistor Rl l l, capacitor C276, capacitor C277, capacitor C278;
[0035] 其中， 电阻 Rl l l、 电容 C276、 电容 C277、 电容 C278并联， 并联后的一公共端 接地， 另一公共端为端接电压 VTT_CA输出端与电阻 R110的一端连接， 电阻 R11[0035] wherein, the resistor Rl l l, the capacitor C276, the capacitor C277, the capacitor C278 are connected in parallel, a common terminal grounded in parallel, and the other common terminal is a terminal voltage VTT_CA output terminal is connected with one end of the resistor R110, the resistor R11
0的另一端连接参考电压 VCORE_l .2。 The other end of 0 is connected to the reference voltage VCORE_l .2.
[0036] 并且， 在数据的读写过程中由于存储器外部主控和存储器本身的驱动能力有限[0036] Moreover, in the process of reading and writing data, the driving ability of the external host of the memory and the memory itself is limited.
， 以及实际运用中 layout吋数据线的线长已远远超出公版 PCB的线长， 因此在优 化实施例中， 在存储器外部主控端和 LDM端对数据 I/O进行了上拉处理， 通过上 拉电阻 R59-R80进行上拉， 通过改变分压电阻得到合适的端接电压， 通过将 ODT (On-die Termination, 片上终结） 上拉到 VTT_DQ， 并更改上拉电阻的阻值从而 得到较强的驱动能力， 结合图 3， 分压电路的具体包括： And the line length of the layout data line in actual use has far exceeded the line length of the public PCB. Therefore, in the optimized embodiment, the data I/O is pulled up on the external host and the LDM end of the memory. Through Pull-up resistor R59-R80 is pulled up, and the appropriate termination voltage is obtained by changing the voltage divider resistor. By pulling up ODT (On-die Termination) to VTT_DQ and changing the resistance of the pull-up resistor, it is stronger. The driving capability, combined with Figure 3, the voltage divider circuit specifically includes:
[0037] 电阻 R112、 电阻 R113、 电容 C279、 电容 C280、 电容 C281 ; [0037] resistor R112, resistor R113, capacitor C279, capacitor C280, capacitor C281;
[0038] 其中， 电阻 R113、 电容 C279、 电容 C280、 电容 C281并联， 并联后的一公共端 接地， 另一公共端为端接电压 VTT_DQ输出端与电阻 R112的一端连接， 电阻 R11[0038] wherein, the resistor R113, the capacitor C279, the capacitor C280, the capacitor C281 are connected in parallel, a common terminal is connected in parallel, and the other common terminal is a terminal voltage VTT_DQ output terminal is connected to one end of the resistor R112, the resistor R11
2的另一端连接参考电压 VCORE_l .2。 The other end of 2 is connected to the reference voltage VCORE_l .2.
[0039] 本申请实施例的另一目的在于提供一种基于上述实施例中低功耗双列直插式存 储器的增强驱动方法， 该方法包括下述步骤： Another object of the embodiments of the present application is to provide an enhanced driving method based on the low power dual in-line memory in the above embodiment, the method comprising the following steps:
[0040] S101 , 分别在平台和低功耗双列直插式存储器的 PCB板上将控制线、 地址线以 及 I/O口进行上拉处理， 且通过对参考电压进行分压得到端接电压。 [0040] S101, performing pull-up processing on the control board, the address line, and the I/O port on the PCB of the platform and the low-power dual in-line memory, respectively, and obtaining the termination voltage by dividing the reference voltage .
[0041] 进一步地， 该方法还包括： [0041] Further, the method further includes:
[0042] S102, 将所述存储器的吋钟引脚通过包地信号线传输 Clock (吋钟） 信号。  [0042] S102. The clock pin of the memory is transmitted through a packet signal line to transmit a Clock signal.
[0043] 进一步地， 该方法还包括： [0043] Further, the method further includes:
[0044] S 103， 设置复用的控制线 /地址线分配后对应的所述存储器弓 I脚与主板连接的 走线长度大于数据线长度。  [0044] S103. Set a multiplexed control line/address line to allocate a corresponding length of the memory cable to the motherboard to be greater than a data line length.
[0045] 值得说明的是， 本实施例并不限定步骤 S102和步骤 S103执行的先后顺序。 [0045] It should be noted that the present embodiment does not limit the sequence of steps S102 and S103.
[0046] 在本申请实施例中， 由于 LPDDR系列主要应用在低功耗的消费类电子产品中[0046] In the embodiment of the present application, the LPDDR series is mainly used in low-power consumer electronic products.
， 本身 I/O口的驱动能力有限， 控制、 地址线在 layout过程中走线比较长， 信号衰 减严重， The driving capability of the I/O port itself is limited. The control and address lines are long in the layout process, and the signal attenuation is severe.
[0047] 为此在设计吋在平台和 LDM的 PCB板上将控制线、 地址线以及 I/O口进行了上 拉处理， 上拉电阻的数量与可选择上拉的控制线、 地址线以及 I/O口数量对应， 其中端接电压 VTT_CA通过相关的参考电压 VC0RE_1.2进行分压得到， 结合图 2  [0047] For this reason, the control line, the address line, and the I/O port are pulled up on the PCB designed on the platform and the LDM, and the number of pull-up resistors and the selectable pull-up control line, address line, and The number of I/O ports corresponds, wherein the termination voltage VTT_CA is obtained by dividing the voltage by the associated reference voltage VC0RE_1.2, in combination with FIG.
[0048] 并且， 在数据的读写过程中由于存储器外部主控和存储器本身的驱动能力有限 ， 以及实际运用中 layout吋数据线的线长已远远超出公版 PCB的线长， 因此在优 化实施例中， 在存储器外部主控端和 LDM端对数据 I/O进行了上拉处理， 通过改 变分压电阻得到合适的端接电压， 通过将 ODT (On-die Termination, 片上终结 ) 上拉到 VTT_DQ， 并更改上拉电阻的阻值从而得到较强的驱动能力， 结合图 3 [0048] Moreover, in the process of reading and writing data, the driving ability of the external host and the memory itself is limited, and the line length of the layout data line in the actual application has far exceeded the line length of the public PCB, so the optimization is performed. In the embodiment, the data I/O is pulled up at the external host and the LDM end of the memory, and the appropriate termination voltage is obtained by changing the voltage dividing resistor, and the ODT (On-die Termination) is terminated. ) Pull up to VTT_DQ, and change the resistance of the pull-up resistor to get strong drive capability, combined with Figure 3.
[0049] 本申请实施例在现有 DDR4 SO-DIMM (标准的 69.6*30mm尺寸或 69.6*20mm的 小型尺寸） 接口规范的基础上合理分配了 LPDDR2/3/4的接口定义， 使 LDM可以 在高速工作环境下保持信号完整性以及电源完整性。 由于 JEDEC已有 SPD支持， 此技术主要为硬件实现方案。 [0049] The embodiment of the present application reasonably allocates the interface definition of LPDDR2/3/4 on the basis of the existing DDR4 SO-DIMM (standard 69.6*30mm size or 69.6*20mm small size) interface specification, so that the LDM can be Maintain signal integrity and power integrity in high-speed work environments. Since JEDEC has SPD support, this technology is mainly a hardware implementation.
[0050] 本申请实施例利用了现有的笔记本内存接口规格 DDR4 SO-DIMM (260 pin)[0050] The embodiment of the present application utilizes the existing notebook memory interface specification DDR4 SO-DIMM (260 pin)
， 将 LPDDR2/3/4定义在此接口规范上， 实现低功耗、 大容量以及即插即用的需 求。 , LPDDR2/3/4 is defined on this interface specification to achieve low power consumption, large capacity and plug and play requirements.
[0051] 以上仅为本申请的较佳实施例而已， 并不用以限制本申请， 凡在本申请的精神 和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本申请的保护范 围之内。  The above are only the preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application are included in the present application. Within the scope of protection.

Claims

权利要求书 Claim
[权利要求 1] 一种低功耗双列直插式存储器， 其特征在于， 所述存储器为可插拔双 列直插式结构， 兼容 DDR内存接口， 所述存储器基于低功耗内存芯 片的 DDR4 SO-DIMM接口以信号完整性和电源完整性为原则做如下 引脚分配：  [Claim 1] A low power dual in-line memory, wherein the memory is a pluggable dual in-line structure, compatible with a DDR memory interface, and the memory is based on a low power memory chip. The DDR4 SO-DIMM interface is based on signal integrity and power integrity as follows:
所述存储器的电源引脚和接地弓 I脚通过对所述 DDR4 SO-DIMM接口 的数据线、 控制线和地址线的两端从新分配得到， 使布线吋数据线、 控制线、 地址线通过电源弓 I脚和接地弓 I脚隔离； 所述存储器的电源弓 I脚和接地弓 I脚按一定的比例进行分配。  The power supply pin and the grounding pin of the memory are newly allocated through the two ends of the data line, the control line and the address line of the DDR4 SO-DIMM interface, so that the wiring, the data line, the control line, and the address line pass through the power source. The bow I pin is isolated from the grounding pin I; the power supply bow I and the grounding pin I of the memory are allocated in a certain ratio.
[权利要求 2] 如权利要求 1所述的存储器， 其特征在于， 所述电源引脚包括第一电 源引脚、 第二电源引脚、 第三电源引脚。 [Claim 2] The memory of claim 1, wherein the power supply pin comprises a first power supply pin, a second power supply pin, and a third power supply pin.
[权利要求 3] 如权利要求 1所述的存储器， 其特征在于， 所述存储器的容量与所述 低功耗内存芯片的片选弓 I脚数量具有对应关系。 [Claim 3] The memory according to claim 1, wherein a capacity of the memory has a correspondence relationship with a number of chip select pins of the low power memory chip.
[权利要求 4] 如权利要求 1所述的存储器， 其特征在于， 所述存储器的 PCB端引脚 通过对所述 DDR4 SO-DIMM接口的控制线、 地址线以及 I/O口上拉得 到， 且端接电压通过参考电压进行分压得到。 [Claim 4] The memory according to claim 1, wherein the PCB terminal pin of the memory is obtained by pulling up a control line, an address line, and an I/O port of the DDR4 SO-DIMM interface, and The termination voltage is obtained by dividing the voltage by a reference voltage.
[权利要求 5] 如权利要求 4所述的存储器， 其特征在于， 所述端接电压通过分压电 路对参考电压进行分压得到， 所述分压电路包括： 电阻 R110、 电阻 Rl l l、 电容 C276、 电容 C277、 电容 C278; [Claim 5] The memory according to claim 4, wherein the termination voltage is obtained by dividing a reference voltage by a voltage dividing circuit, and the voltage dividing circuit comprises: a resistor R110, a resistor R111, and a capacitor C276, capacitor C277, capacitor C278;
其中， 所述电阻 Rl l l、 所述电容 C276、 所述电容 C277、 所述电容 C2 The resistor R1 l l, the capacitor C276, the capacitor C277, and the capacitor C2
78并联， 并联后的一公共端接地， 另一公共端为所述端接电压的输出 端与所述电阻 R110的一端连接， 所述电阻 R110的另一端连接参考电 压。 78 is connected in parallel, a common terminal connected in parallel is grounded, and the other end of the common terminal is connected to one end of the resistor R110, and the other end of the resistor R110 is connected to a reference voltage.
[权利要求 6] 如权利要求 1所述的存储器， 其特征在于， 所述存储器的吋钟引脚通 过包地信号线传输吋钟信号。  [Claim 6] The memory according to claim 1, wherein the clock pin of the memory transmits the chirp signal through the packet signal line.
[权利要求 7] 如权利要求 1所述的存储器， 其特征在于， 复用的控制线 /地址线分配 后对应的所述存储器引脚与主板连接的走线长度大于数据线长度。 [Claim 7] The memory according to claim 1, wherein the multiplexed control line/address line is allocated after the corresponding memory pin is connected to the main board by a length longer than the data line length.
[权利要求 8] —种基于如权利要求 1至 3任一项所述的低功耗双列直插式存储器的增 强驱动方法， 其特征在于， 所述方法包括下述步骤： 分别在平台和低功耗双列直插式存储器的 PCB板上将控制线、 地址线 以及 I/O口进行上拉处理， 且通过对参考电压进行分压得到端接电压 [Claim 8] An increase in low power dual in-line memory according to any one of claims 1 to 3 A strong driving method, the method comprising the steps of: pulling up a control line, an address line, and an I/O port on a PCB of a platform and a low power dual in-line memory, respectively, and The termination voltage is obtained by dividing the reference voltage
[权利要求 9] 如权利要求 8所述的方法， 其特征在于， 所述方法还包括： [Claim 9] The method according to claim 8, wherein the method further comprises:
将所述存储器的吋钟引脚通过包地信号线传输吋钟信号。  The clock pin of the memory is transmitted through the packet signal line to transmit the chirp signal.
[权利要求 10] 如权利要求 8所述的方法， 其特征在于， 所述方法还包括：  [Claim 10] The method according to claim 8, wherein the method further comprises:
设置复用的控制线 /地址线分配后对应的所述存储器弓 I脚与主板连接 的走线长度大于数据线长度。  After the multiplexed control line/address line is allocated, the corresponding memory cable I is connected to the main board and the length of the trace is greater than the data line length.
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