CN107507637A - A kind of low power consumption double-row In-line Memory and its enhancing driving method - Google Patents

A kind of low power consumption double-row In-line Memory and its enhancing driving method Download PDF

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Publication number
CN107507637A
CN107507637A CN201710841231.9A CN201710841231A CN107507637A CN 107507637 A CN107507637 A CN 107507637A CN 201710841231 A CN201710841231 A CN 201710841231A CN 107507637 A CN107507637 A CN 107507637A
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memory
power consumption
pin
line
row
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CN107507637B (en
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肖浩
李志雄
邓恩华
吴方
卢浩
龙红卫
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Shenzhen Netcom Electronics Co Ltd
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Shenzhen Netcom Electronics Co Ltd
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Priority to PCT/CN2017/116580 priority patent/WO2019052061A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Abstract

The present invention is applied to electronic applications, provide a kind of low power consumption double-row In-line Memory and its enhancing driving method, the memory is pluggable dual inline type structure, compatible DDR memory interfaces, DDR4 SO DIMM interface of the memory based on low-power consumption RAM chip do following pin assignment using signal integrity and Power Integrity as principle：The power pins and grounding pin of memory are obtained by the both ends to the data wire of DDR4 SO DIMM interfaces, control line and address wire from new distribution, data wire, control line, address wire during wiring is isolated by power pins and grounding pin；The power pins and grounding pin of memory are allocated according to a certain percentage.Present invention utilizes existing notebook memory interface specification DDR4 SO DIMM, by LPDDR2/3/4 definition on this interface specification, realize the demand of low-power consumption, Large Copacity and plug and play.

Description

A kind of low power consumption double-row In-line Memory and its enhancing driving method
Technical field
The invention belongs to electronic applications, more particularly to a kind of low power consumption double-row In-line Memory and its enhancing driving side Method.
Background technology
Constantly stepped with the consumer electronics product integrated level more and more higher such as PC, mobile phone, and towards the direction of miniaturization Enter, consumer proposes bigger capacity, lower power consumption to the memory modules in all kinds of 3C Products and meets plug and play The demand changed at any time.But internal memory is from DRAM that (Dynamic Random Access Memory, movement dynamically arbitrary access are deposited Reservoir) development main flow by now DDR3, DDR4, LPDDR3 and LPDDR4, but still without a kind of unified interface specification Internally to deposit into row and change at any time and upgrade at any time.
So far as the defined DDR3 SO-DIMM (Small of the memory modules JEDEC of the consumer electronics products such as PC Outline Dual In-line Memory Module：Small outline dual memory modules) and DDR4 SO-DIMM interface Specification, and the SPD (Serial Presence Detect, serial sensing existing for module) for having standard is supported, and be directed to The Mobile DRAM series of low-power consumption series does not have but corresponding memory modules interface specification to support, and define only SPD letters Breath.It can not realize the compatibility of low-power consumption storage device, and meet on the premise of master control is supported Large Copacity, plug and play Upgrade requirement.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of low power consumption double-row In-line Memory, it is intended to solves existing internal memory Interface specification disunity causes, and can not realize the compatibility of low-power consumption storage device, and meet on the premise of master control is supported Large Copacity, plug and play upgrade requirement the problem of.
The embodiment of the present invention is achieved in that a kind of low power consumption double-row In-line Memory, and the memory is to insert Dual inline type structure, compatible DDR memory interfaces are pulled out, DDR4SO-DIMM of the memory based on low-power consumption RAM chip connects Mouth does following pin assignment using signal integrity and Power Integrity as principle：
The power pins and grounding pin of the memory pass through the data wire to the DDR4 SO-DIMM interfaces, control The both ends of line and address wire obtain from new distribution, data wire, control line, address wire during wiring is passed through power pins and grounding lead Pin is isolated；
The power pins and grounding pin of the memory are allocated according to a certain percentage.
The another object of the embodiment of the present invention is to provide a kind of based on above-mentioned low power consumption double-row In-line Memory Strengthen driving method, it is characterised in that methods described comprises the steps：
Control line, address wire and I/O mouths are entered on the pcb board of platform and low power consumption double-row In-line Memory respectively The processing of row pull-up, and obtain termination voltage by carrying out partial pressure to reference voltage.
LDM in the embodiment of the present invention make use of existing notebook memory interface specification DDR4 SO-DIMM (260pin), by LPDDR2/3/4 definition on this interface specification, realize low-power consumption that active user should have to internal memory, big The demand of capacity and plug and play.
Brief description of the drawings
Fig. 1 is the structure chart of low power consumption double-row In-line Memory provided in an embodiment of the present invention；
Fig. 2 is control line, address wire and the I/O mouths of low power consumption double-row In-line Memory provided in an embodiment of the present invention Pull-up structural representation；
Fig. 3 is the pull-up structural representation of the data wire of low power consumption double-row In-line Memory provided in an embodiment of the present invention Figure.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below Conflict can is not formed each other to be mutually combined.
The embodiment of the present invention make use of existing notebook memory interface specification DDR4 SO-DIMM (260pin), will LPDDR2/3/4 is defined on this interface specification, realizes the demand of low-power consumption, Large Copacity and plug and play.
Fig. 1 shows the structure of low power consumption double-row In-line Memory provided in an embodiment of the present invention, for convenience of description, It illustrate only part related to the present invention.
As one embodiment of the invention, the low power consumption double-row In-line Memory (LDM, Low Power Dual- Inline-Memory-Modules it is) pluggable dual inline type structure, compatible DDR memory interfaces, memory is based on low-power consumption The DDR4 SO-DIMM interfaces of memory chip (LPDDR series), are done as principle using signal integrity and Power Integrity and drawn as follows Pin distributes：
By the data wire to DDR4 SO-DIMM interfaces, (DQn, n are nature to the power pins and grounding pin of memory Number represents sequence number), the both ends of control line and address wire (CAn, n are that natural number represents sequence number) obtained from new distribution, when making wiring Data wire, control line, address wire are isolated by power pins and grounding pin, so as to ensure the integrality of signal；
The power pins and grounding pin of memory are allocated according to a certain percentage, to ensure the complete of memory power Property.
In embodiments of the present invention, the DDR4 SO-DIMM interfaces based on low-power consumption RAM chip (LPDDR series) are carried out Design, design parameter are as shown in table 1：
To keep the DDR4 of signal integrity and Power Integrity as principle to low-power consumption RAM chip (LPDDR series) SO-DIMM interfaces carry out pin assignment, the power pins of low power consumption double-row In-line Memory include the first power pins VDD1, Second source pin VDD2, the 3rd power pins VSS.First power pins VDD1, second source pin VDD2, the 3rd power supply draw Pin VSS and grounding pin are evenly distributed in data wire (DQn) and control line, address wire (Can) both ends so that data during wiring Line and control line, address wire have power supply and ground to be isolated, and signal integrity accomplishes optimal, power pins and grounding pin in addition It is allocated according to a certain percentage, it is ensured that memory modules there are enough Power Integrities when working.Low-power consumption RAM chip (LPDDR series) is drawn by the DDR4 SO-DIMM interfaces of standard by above-mentioned principle, and compatible DDR memory bars connect Mouthful, it can accomplish to plug at any time.
In embodiments of the present invention, in the control of the chip select pin such as CS0_n, CS1_n, CS2_n of low-power chip The capacity of module is deposited, a CS signal represents specific memory cell, and the signal is more, and capacity is bigger, more by drawing CS signals memory modules can accomplish online upgrading.
Preferably, the PCB ends pin of memory passes through to the control line of DDR4 SO-DIMM interfaces, address wire and I/O Mouth pull-up obtains, and termination voltage carries out partial pressure by reference to voltage and obtained.
Preferably, the clock pins of low power consumption double-row In-line Memory can be transmitted Clock by bag earth signal line (clock) signal, so as to reduce interference, improve the accuracy of clock.
Furthermore it is also possible to make what corresponding memory pin after the control line of multiplexing/address wire distribution was connected with mainboard to walk Line length is more than data line length, has enough foundation, retention time during so as to ensure reading and writing data.
Because LPDDR series is mainly used in the consumer electronics product of low-power consumption, the driving force of I/O mouth itself has Limit, control, address wire cabling during layout are long, and signal attenuation is serious,
Control line, address wire and I/O mouths have been carried out at pull-up on platform and LDM pcb board in design for this Reason, is pulled up, wherein CKE0, CKE1 are that clock makes energy line, and CKE0, CKE1 are high level by pull-up resistor R94-R109 When activate internal clock circuit, input buffering and output driving, then close related circuit during low level.Believed by CKE0, CKE1 Number upset enter or exit battery saving mode.CKE0, CKE1 signal are a parts for instruction code, and each passage has corresponding CKE signal.
Also, the quantity of pull-up resistor is corresponding with control line, address wire and I/O mouth quantity that pull-up may be selected, wherein Termination voltage VTT_CA by correlation reference voltage VCORE_1.2 carry out partial pressure obtain, with reference to Fig. 2, bleeder circuit it is specific Including：
Resistance R110, resistance R111, electric capacity C276, electric capacity C277, electric capacity C278；
Wherein, resistance R111, electric capacity C276, electric capacity C277, electric capacity C278 are in parallel, the common end grounding after parallel connection, separately One common port is that termination voltage VTT_CA output ends are connected with resistance R110 one end, and resistance R110 other end connection is with reference to electricity Press VCORE_1.2.
Also, the driving force due to memory external piloting control and memory in itself during the read-write of data is limited, And in practice during layout the line length of data wire far beyond public version PCB line length, therefore in optimal enforcement example, Pull-up processing has been carried out to data I/O at memory external piloting control end and LDM ends, pulled up by pull-up resistor R59-R80, Suitable termination voltage is obtained by changing divider resistance, by by ODT (On-die Termination, piece on terminate) pull-up To VTT_DQ, and the resistance of pull-up resistor is changed so as to obtain stronger driving force, with reference to Fig. 3, the specific bag of bleeder circuit Include：
Resistance R112, resistance R113, electric capacity C279, electric capacity C280, electric capacity C281；
Wherein, resistance R113, electric capacity C279, electric capacity C280, electric capacity C281 are in parallel, the common end grounding after parallel connection, separately One common port is that termination voltage VTT_DQ output ends are connected with resistance R112 one end, and resistance R112 other end connection is with reference to electricity Press VCORE_1.2.
The another object of the embodiment of the present invention a kind of is being based in above-described embodiment that low power consumption double-row is direct insertion to be deposited in providing The enhancing driving method of reservoir, this method comprise the steps：
S101, respectively by control line, address wire and I/ on the pcb board of platform and low power consumption double-row In-line Memory O mouths carry out pull-up processing, and obtain termination voltage by carrying out partial pressure to reference voltage.
Further, this method also includes：
S102, the clock pins of the memory are transmitted into Clock (clock) signal by bag earth signal line.
Further, this method also includes：
S103, set what the corresponding memory pin after the control line of multiplexing/address wire distribution was connected with mainboard to walk Line length is more than data line length.
What deserves to be explained is the present embodiment does not limit the sequencing that step S102 and step S103 is performed.
In embodiments of the present invention, because LPDDR series is mainly used in the consumer electronics product of low-power consumption, itself The driving force of I/O mouths is limited, and control, address wire cabling during layout are long, and signal attenuation is serious,
Control line, address wire and I/O mouths have been carried out at pull-up on platform and LDM pcb board in design for this Reason, the quantity of pull-up resistor is corresponding with control line, address wire and I/O mouth quantity that pull-up may be selected, wherein termination voltage VTT_CA carries out partial pressure by the reference voltage VCORE_1.2 of correlation and obtained, with reference to Fig. 2.
Also, the driving force due to memory external piloting control and memory in itself during the read-write of data is limited, And in practice during layout the line length of data wire far beyond public version PCB line length, therefore in optimal enforcement example, Pull-up processing has been carried out to data I/O at memory external piloting control end and LDM ends, suitably held by changing divider resistance Voltage is connect, by the way that ODT (On-die Termination, piece on terminate) is pulled upward into VTT_DQ, and changes the resistance of pull-up resistor Value is so as to obtain stronger driving force, with reference to Fig. 3.
The embodiment of the present invention is in existing DDR4SO-DIMM (the 69.6*30mm sizes of standard or 69.6*20mm small-sized chi It is very little) reasonable distribution LPDDR2/3/4 interface definition on the basis of interface specification, LDM is protected under high speed operation environment Hold signal integrity and Power Integrity.Because the existing SPD of JEDEC support that this technology is mainly hardware implementations.
The embodiment of the present invention make use of existing notebook memory interface specification DDR4 SO-DIMM (260pin), will LPDDR2/3/4 is defined on this interface specification, realizes the demand of low-power consumption, Large Copacity and plug and play.
These are only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and All any modification, equivalent and improvement made within principle etc., should be included in the scope of the protection.

Claims (10)

  1. A kind of 1. low power consumption double-row In-line Memory, it is characterised in that the memory is pluggable dual inline type structure, Compatible DDR memory interfaces, the memory is based on the DDR4SO-DIMM interfaces of low-power consumption RAM chip with signal integrity and electricity Source integrality is that principle does following pin assignment：
    The power pins of the memory and grounding pin by the data wire of the DDR4SO-DIMM interfaces, control line and The both ends of address wire obtain from new distribution, data wire when making wiring, control line, address wire by power pins and grounding pin every From；
    The power pins and grounding pin of the memory are allocated according to a certain percentage.
  2. 2. memory as claimed in claim 1, it is characterised in that the power pins include the first power pins, the second electricity Source pin, the 3rd power pins.
  3. 3. memory as claimed in claim 1, it is characterised in that the capacity of the memory and the low-power consumption RAM chip Chip select pin quantity there is corresponding relation.
  4. 4. memory as claimed in claim 1, it is characterised in that the PCB ends pin of the memory passes through to described Control line, address wire and the I/O mouths of DDR4SO-DIMM interfaces are pulled up to obtain, and termination voltage is divided by reference to voltage Pressure obtains.
  5. 5. memory as claimed in claim 4, it is characterised in that the termination voltage is entered by bleeder circuit to reference voltage Row partial pressure obtains, and the bleeder circuit includes：
    Resistance R110, resistance R111, electric capacity C276, electric capacity C277, electric capacity C278；
    Wherein, the resistance R111, the electric capacity C276, the electric capacity C277, the electric capacity C278 are in parallel, and one after parallel connection is public End ground connection altogether, another common port are connected for the output end of the termination voltage with one end of the resistance R110, the resistance R110 other end connection reference voltage.
  6. 6. memory as claimed in claim 1, it is characterised in that the clock pins of the memory are passed by bag earth signal line Defeated clock signal.
  7. 7. memory as claimed in claim 1, it is characterised in that corresponding described after the control line of multiplexing/address wire distribution The track lengths that memory pin is connected with mainboard are more than data line length.
  8. 8. a kind of enhancing driving method of the low power consumption double-row In-line Memory based on as described in any one of claims 1 to 3, Characterized in that, methods described comprises the steps：
    Control line, address wire and I/O mouths are carried out on the pcb board of platform and low power consumption double-row In-line Memory respectively Drawing is handled, and obtains termination voltage by carrying out partial pressure to reference voltage.
  9. 9. method as claimed in claim 8, it is characterised in that methods described also includes：
    The clock pins of the memory are transmitted into clock signal by bag earth signal line.
  10. 10. method as claimed in claim 8, it is characterised in that methods described also includes：
    The track lengths that the corresponding memory pin is connected with mainboard after the control line of setting multiplexing/address wire distribution are more than Data line length.
CN201710841231.9A 2017-09-18 2017-09-18 Low-power-consumption dual-in-line memory and enhanced driving method thereof Active CN107507637B (en)

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PCT/CN2017/116580 WO2019052061A1 (en) 2017-09-18 2017-12-15 Low-power consumption dual in-line memory, and enhanced driving method therefor

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108665916A (en) * 2018-04-09 2018-10-16 烽火通信科技股份有限公司 A kind of memory modules and its implementation of Android embedded devices
CN111341367A (en) * 2018-12-18 2020-06-26 深圳市江波龙电子股份有限公司 Control method of storage device, storage device and electronic device

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621754B1 (en) * 2002-07-10 2003-09-16 Micro-Star Int'l Co., Ltd. Memory interface control circuit
CN1728073A (en) * 2004-07-30 2006-02-01 国际商业机器公司 Double lined and directly inserted memory module and computer memory system
US20060039205A1 (en) * 2004-08-23 2006-02-23 Cornelius William P Reducing the number of power and ground pins required to drive address signals to memory modules
CN1768330A (en) * 2003-04-14 2006-05-03 国际商业机器公司 A high reliability memory module with a fault tolerant address and command bus
US20080002493A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Dual in-line memory module, memory test system, and method for operating the dual in-line memory module
US20080094808A1 (en) * 2006-10-23 2008-04-24 Ruban Kanapathippillai Methods and apparatus of dual inline memory modules for flash memory
US20100135097A1 (en) * 2008-12-03 2010-06-03 Dell Products, Lp System and Method for Supporting Standard and Voltage Optimized DIMMs
CN102622330A (en) * 2012-02-24 2012-08-01 北京海尔集成电路设计有限公司 Control chip compatible with different dynamic random access memories (DRAMs) and method thereof
CN105900039A (en) * 2014-02-19 2016-08-24 英特尔公司 Apparatus, system and method to provide platform support for multiple memory technologies
US20160370998A1 (en) * 2015-06-18 2016-12-22 Mediatek Inc. Processor Memory Architecture
US20170249991A1 (en) * 2016-02-26 2017-08-31 Intel Corporation Supporting multiple memory types in a memory slot
US20170255575A1 (en) * 2016-03-03 2017-09-07 Samsung Electronics Co., Ltd. Asynchronous communication protocol compatible with synchronous ddr protocol
JP2017157214A (en) * 2016-03-03 2017-09-07 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Memory module executing in-module function
CN207319696U (en) * 2017-09-18 2018-05-04 深圳市江波龙电子有限公司 A kind of low power consumption double-row In-line Memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10310547B2 (en) * 2016-03-05 2019-06-04 Intel Corporation Techniques to mirror a command/address or interpret command/address logic at a memory device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621754B1 (en) * 2002-07-10 2003-09-16 Micro-Star Int'l Co., Ltd. Memory interface control circuit
CN1768330A (en) * 2003-04-14 2006-05-03 国际商业机器公司 A high reliability memory module with a fault tolerant address and command bus
CN1728073A (en) * 2004-07-30 2006-02-01 国际商业机器公司 Double lined and directly inserted memory module and computer memory system
US20060039205A1 (en) * 2004-08-23 2006-02-23 Cornelius William P Reducing the number of power and ground pins required to drive address signals to memory modules
US20080002493A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Dual in-line memory module, memory test system, and method for operating the dual in-line memory module
US20080094808A1 (en) * 2006-10-23 2008-04-24 Ruban Kanapathippillai Methods and apparatus of dual inline memory modules for flash memory
US20100135097A1 (en) * 2008-12-03 2010-06-03 Dell Products, Lp System and Method for Supporting Standard and Voltage Optimized DIMMs
CN102622330A (en) * 2012-02-24 2012-08-01 北京海尔集成电路设计有限公司 Control chip compatible with different dynamic random access memories (DRAMs) and method thereof
CN105900039A (en) * 2014-02-19 2016-08-24 英特尔公司 Apparatus, system and method to provide platform support for multiple memory technologies
US20160370998A1 (en) * 2015-06-18 2016-12-22 Mediatek Inc. Processor Memory Architecture
US20170249991A1 (en) * 2016-02-26 2017-08-31 Intel Corporation Supporting multiple memory types in a memory slot
US20170255575A1 (en) * 2016-03-03 2017-09-07 Samsung Electronics Co., Ltd. Asynchronous communication protocol compatible with synchronous ddr protocol
JP2017157214A (en) * 2016-03-03 2017-09-07 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Memory module executing in-module function
CN107153625A (en) * 2016-03-03 2017-09-12 三星电子株式会社 With the synchronous compatible asynchronous communications protocol of DDR agreements
CN207319696U (en) * 2017-09-18 2018-05-04 深圳市江波龙电子有限公司 A kind of low power consumption double-row In-line Memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RAVI KOLLIPARA等: "Characterization of a Low-Power 6.4 Gbps DDR DIMM Memory Interface System", 《2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE》, pages 1362 - 1371 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108665916A (en) * 2018-04-09 2018-10-16 烽火通信科技股份有限公司 A kind of memory modules and its implementation of Android embedded devices
CN111341367A (en) * 2018-12-18 2020-06-26 深圳市江波龙电子股份有限公司 Control method of storage device, storage device and electronic device

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