CN202976061U

CN202976061U - Nested watchdog circuit

Info

Publication number: CN202976061U
Application number: CN 201220625518
Authority: CN
Inventors: 杨龙龙; 李寒
Original assignee: XI'AN LANKUN ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: XI'AN LANKUN ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2012-11-23
Filing date: 2012-11-23
Publication date: 2013-06-05
Anticipated expiration: 2022-11-23

Abstract

The utility model relates to a nested watchdog circuit, which is characterized by comprising a core processor and n+1 processors, wherein the first processor is the core processor and is connected with a next processor through two communication lines; a last processor is connected with a watchdog chip through two communication lines; every two processors of the n processors between the core processor and the watchdog chip are connected through two communication lines, wherein one I/O (input/output) of one processor is connected with one I/O of the other processor through one communication line, and an I/O port of the processor i+1 is connected with a reset pin of the processor i through the other one communication line; and a reset state of the I/O pin responsible for sending reset signals in each processor is set into high level output. The watchdog circuit is nested layer by layer in sequence, and a nested watchdog circuit system is realized. The nested watchdog circuit has good system stability, and simultaneously has strong applicability, practicability and economy.

Description

A kind of watchdog circuit of realizing nested type

Technical field

The invention belongs to that multiprocessor intercoms mutually and the circuit field of principal and subordinate's operation, be specifically related to a kind of watchdog circuit of realizing nested type.

Background technology

In the practical application of existing industry control electron trade, may there be a plurality of processor work compounds in a system.Still there is hidden danger in stability for the processor program operation, the imperfection of writing due to processor program, always there is the phenomenon of program fleet or deadlock in the process of program operation, the deviser can enable the inside house dog of each processor for this reason, but inner house dog easily is subjected to the impact of program operational failure.In this case, in order to ensure the stability of system works, the deviser tends to design independent outer watchdog for processor.Outer watchdog has an independently clock source, and higher reliability can be provided; Through suitably configuration, the impact that outer watchdog was not lost efficacy by program can.But in the system of a multiprocessor, if be equipped with the house dog of an outside for each processor, following several problem will appear simultaneously:

At first, be exactly the most directly Cost Problems, comprise mainly that here chip cost and the PCB layout area that causes due to the components and parts increase increase cost rising etc.; Secondly, because the wiring complexity of the increase PCB of house dog has improved, and after the pcb board area requirements is determined, increased the control difficulty of the area that connects up; At last, will directly cause the increase of system power dissipation due to the increase of outer watchdog, against the requirement of energy-conserving and environment-protective, also increase unnecessary waste like this.

Summary of the invention

The technical matters that solves

For fear of the deficiencies in the prior art part, the present invention proposes a kind of watchdog circuit of realizing nested type, utilizes self function of each processor, for other processors are done outer watchdog, realize that house dog is nested, guaranteed simultaneously the communication quality between processor.

Technical scheme

A kind of watchdog circuit of realizing nested type is characterized in that comprising a core processor and n+1 processor; First processor is core processor, links with two order wires and next stage processor; The afterbody processor is connected with watchdog chip with two order wires; N between a core processor and watchdog chip processor adopts two order wires to link between any two; Wherein one of described two order wires is the I/O interconnection separately of these two processors, and another is that the I/O mouth of processor i+1 is connected with the reset pin of processor i; The reset mode of I/O pin in this processor that described each processor is responsible for sending reset signal is set to high level output.

Beneficial effect

A kind of watchdog circuit of realizing nested type that the present invention proposes, nested layer by layer successively, realize the nested type watchdog system.Whole system is in the middle of the process of operation, and in all processors, if there is a processor program operation troubles to occur, the processor of its next stage will be given its reset signal so.Therefore, the present invention has good system stability, has simultaneously very strong applicability, practicality and economy.

Description of drawings

Fig. 1: the watchdog circuit schematic diagram of realizing nested type; Core processor is to be responsible for the data processing unit that major function and core data are processed in system, and processor 1～N is the data processing unit with the mutual collaborative work of core processor; The special hardware circuit house dog is a kind of special external watchdog circuit or chip.

Embodiment

Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:

Embodiment is attached sees Fig. 1 nested type watchdog circuit accompanying drawing, and the span of described i is i=1,2 ..., N-1.

By accompanying drawing as seen, processor 1 is done the outer watchdog of core processor, core processor under the state to system's each function normal operation, by external I/O mouth to processor 1 timed sending feeding-dog signal.' regularly ' herein refers to receive the ability in the feeding-dog signal time interval and fixing or variable time period of coordinating to set according to needed time of core processor program operation and processor 1, the dirigibility of this time period is larger, fully can be by core processor and the common consult to decide of processor of serving as house dog.During processor 1 each function normal operation, after receiving feeding-dog signal, the state of setting is not done homing action to core processor according to self programming.When processor 1 when in setting time is not received the feeding-dog signal of core processor, it will send reset signal to core processor, the duration of this signal is to be enough to time that core processor is resetted, is determined by the model of concrete time core processor.

The 1st of intergrade can be described as to the relation between the N processor: i+1 processor serves as the outer watchdog of i processor.Setting about the timing of feeding-dog signal is also to coordinate setting according to the situation of i processor program operation and the receiving ability of i+1 processor, can fix also variablely, and dirigibility is larger.I+1 the processor that serves as house dog sends the length of reset signal duration to i processor and also determined required reset time by i processor when not receiving feeding-dog signal, this duration is to guarantee that i processor is to reset receiving reset signal.

Afterbody is specialized hardware watchdog circuit or chip, and it has special reset signal output terminal and feeding-dog signal input end; It gives its timed sending feeding-dog signal as the outer watchdog of processor N by processor N, and it monitors the program ruuning situation of N processor.Herein time interval of sending of feeding-dog signal by the specialized hardware watchdog chip choose or the design of this circuit relevant, also to coordinate the program ruuning situation of processor N simultaneously.

For processor and serve as processor and the outermost layer special hardware circuit house dog of this processor outer watchdog, its method of operation is:

1, i+1 processor done the outer watchdog of i processor, i processor is under the state of each function normal operation, send feeding-dog signal for the i+1 processor by external I/O mouth, this feeding-dog signal can be equally spaced positive pulse or negative pulse, can be also unequal interval, the concrete time has these two processors to coordinate to determine.

2, when the time interval that feeding-dog signal consults according to two processors sends to i+1 the corresponding I/O mouth of processor that serves as house dog, this processor carries out programmed process with the signal that receives, make it not send reset signal to its upper level processor, these two processors all work at this moment, and outside function is all normal.

3, when time interval that i processor not do not provide according to it and i+1 processor during to i+1 processor transmission feeding-dog signal, i+1 the processor that serves as house dog will send reset signal to i processor according to the time that it and i processor consult, and makes i processor reset.

4, after i processor reset, got back to again the 1st kind of situation.I processor and i+1 processor carrying out judgement separately and continuing execution the 2nd and the 3rd kind of situation, make in this way each processor of whole system be monitored, and are the equal normal operations of each function of system afterwards.

The problem that should be noted that have following some:

1, processor i and serve as between the processor i+1 of this processor and only have two order wires.Article one, be the I/O interconnection separately of these two processors, i sends feeding-dog signal to processor i+1 with the cause processor; Another is that the I/O mouth of processor i+1 is connected with the reset pin of processor i, and i+1 sends reset signal to processor i with the cause processor.

2, the communication between processor i and processor i+1 comprises the send and receive of feeding-dog signal and the send and receive of reset signal, only with these two processors, relation is arranged, with other processor in system without any relation.And the time interval of communication and time length are according to the program ruuning situation of these two processors and the resource of himself and concrete the setting is irrelevant with other extraneous factors.

3, in order not affect the work of other processors, the reset mode of I/O pin in this processor that in system, each processor is responsible for sending reset signal should be set to high level output.Guarantee that this pin only is controlled by the feeding-dog signal that this processor receives.

Claims

1. a watchdog circuit of realizing nested type, is characterized in that comprising a core processor and n+1 processor; First processor is core processor, links with two order wires and next stage processor; The afterbody processor is connected with watchdog chip with two order wires; N between a core processor and watchdog chip processor adopts two order wires to link between any two; Wherein one of described two order wires is the I/O interconnection separately of these two processors, and another is that the I/O mouth of processor i+1 is connected with the reset pin of processor i; The reset mode of I/O pin in this processor that described each processor is responsible for sending reset signal is set to high level output.