SU1285592A1 - Decade counter for seven-segments indicators - Google Patents

Description

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aj 0 020203 c) ,, ati

nineteen

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 285wa to consider the indications by ensuring the issuance of information on the indicator in units of the parameter being measured, when the weight of one pulse is equal to three, and an increase in speed. To achieve this goal in

The invention relates to a pulse technique and can be used in digital transducers and digital measuring devices with access to a seminal display in units of the parameter being measured.

The purpose of the invention is to improve the readability of indications by ensuring the issuance of information on the display in units of the measured parameter with a pulse weight of three, and an increase in speed.

FIG. I presents the functional diagram of the proposed device; in fig. 2 diagram of the operation of the device; in fig. 3 is a diagram of a seven-segment indicator.

The device contains the first 1, second 2, third 3, fourth 4, IK- triggers, first 5, second 6, third 7, fourth 8, fifth 9, sixth 10, seventh 11, eighth 12, ninth 13 elements And, first 14, second 15, third 16, fourth 17, fifth 18 elements OR, clock bus 19, which receives input clock (counted) pulses, bus 20, reset transfer bus 21, used as input bus for the next decade outputs 22 ( c), 23 (b), 24 (a), 25 (d) 26 (e), 27 (f), 28 (q) to control the illumination of the same a, b, c, d, e, q indicator segments.

The operation of the proposed device is described by the logical equations for the I: - and K-inputs of the triggers.

i, Q ,; ,; i, Q4; 14 Qo

K, Q ,; ,; K, Q ,; K, Q.

The decoder for the proposed scheme is constructed in accordance with the logical equations:

.Q4; e d,,; , Q4; f Q4 (Q2V Q,);

device introduced elements OR 16, 17, 18; In addition, the device contains 1 + K-triggers 1,2, 3, 4, elements AND 5, 6, 7, 8, 9, 10, 11, 12, 13, elements OR 14, 15. 3 silt, 2 tab.

ten

15

0

five

thirty

five

0

five

, Q2Q3Q; 4 Q (Q4V Q7) V fQ ,.

 V Q3Q4;

The device works in the following way.

On a reset signal on bus 20, all triggers are reset, with: Q, Oj Qj-O ;: Q, 0; Q 0; Q, l; 5 Q 1, a at the output of the decoder signals a 0 are generated; B 0; with 0; d 0; e 0; f 0; q 1, therefore, the digit O is displayed on the indicator (unit 1 | and indicates the non-luminous element of the seven-segment indicator).

Since the 1K-trigger when and does not change its state, when I 1 and K O switches to the state of a logical one, when I 1 and K 1 switches to the opposite state and when I O and K 1 switches to the state of logical zero , then when the first counted pulse arrives in the circuit, since 1, 1, 1 0; 14 1; K, 0; K 0; K5 1; To 1, triggers 1 and 4 switch to the state of a logical unit, at the outputs of which logical units are formed, and triggers 2 and 3 remain in a state of logical zero. The state of the outputs is equal to Q G; 0, 0; Q, 0; Q4 1; Q, 0; one; Q G; . | 0. The state of the trigger inputs is the following: I, 1; eleven; eleven; 14 0; K, 0; Kg 1; K, 0; K G. At the outputs of the decoder, the signals a 0 appear; L 0; with 0; d. 0; e 1; f, under the action of which the number 3 is displayed on the indicator (FIG. 2, with i 1).

When the second read pulse arrives at the input, the state of flip-flops 2 and 3 change their state.

which are switched to the state of a logical unit, and. trigger 4, which has switched to the logical zero state, while trigger 1 remains in the same state. Consequently, the states of the inputs and outputs of the device are equal (Fig. 2, at):

, one; QrOiQ r °

0.3 0; Q4 1;

I, K, 0;

Sequence of input pulses

A decimal digit is displayed.

DC 3 3 9

Transfer momentum

The remaining values of the signals (logic functions at the trigger

0o I

1II

1 000

Io I

11 o

0I o

1I I

1 about 10 about 1 1 about I I 00011

I

about

10 o o

Claims (1)

Claims 50 55 A decade counter for seven-segment indicators, containing four LC-triggers and a decimator, having nine AND elements, two OR elements, the decoder outputs are device outputs, the first output of the first trigger is connected to the 3- and K-inputs of the second trig a 0; , a 6 is displayed on the indicator. The display of numbers on the indicator and the appearance of a transfer pulse in the next decade occur when pulses enter the input in accordance with Table. one. Table 1 0123 8 9 ten four 0011 ABOUT f etc. ditch and decoder (figure 2) are summarized in table. 2 Table 2 0 o 00 I 1 o 1 o oh oh oh oh oh I oh oh oh oh oh about oI oo oI oo oI oh oh one oh oh about ) t I 1 1 o one 000 I oh oh oh oh 1 about 1 i about 3 6 9 2 5 8 1 4 7 o the first and second inputs of the first and second elements I, the direct output of the second trigger is connected to the first input of the third element I, the direct output of the third trigger is connected to the first inputs of the fourth and fifth elements And, the direct output of the fourth trigger is connected to the first input the sixth element And the inverse output of the first trigger is connected to the first input the seventh And element, the output of which is connected to the C-output of the decoder, the clock inputs of the triggers are connected to the clock input of the device, and R - the inputs of the triggers are connected to the device reset bus, characterized in that, in order to increase the readability of the readings by providing information on the indication in units of the measured parameter with a pulse weight equal to three, and speeding up, three OR elements are entered into it, the inverse output of the first trigger is connected to the K-INPUT of the third trigger and 3 - the fourth trigger, the inverse output of the second trigger is connected to the K input of the fourth trigger, the second inputs of the second and seventh elements AND, the first input of the first OR element and the second input of the fifth AND element whose output is connected to the rfepBbiM input of the second OR element, the first input of the third OR element is connected to direct output of the second trigger, and the first input of the fifth element AND with the first input of the eighth element AND, the output of which is connected to the first input of the fourth element OR, the inverse of the third trigger is connected to the 3rd input of the first trigger, the third Valid emu seventh AND gate, a first input of a ninth AND gate and a second input of the first , fO 15 285592 - 6 the OR element, the output of which is connected to the second input of the sixth element AND, the output of which is connected to the i - output of the decoder and the second input of the fourth element And, the direct output of the fourth trigger is connected to L - the input of the third trigger, the second input of the eighth element And the fourth input of the seventh of the AND element and second fy to the input of the third element AND, the output of the ijoor is connected to the second input of the fourth element OR and the output of the decoder, the output of the fourth element OR is connected to the a output of the decoder and the second input of the second element OR, and the output the second element OR is connected to the e-output of the decoder, the inverse output of the fourth trigger is connected to the second input of the third element OR and the second input of the first element AND whose output is connected to the b output of the decoder, the output of the second element AND is connected to the third input of the second element OR, and the output of the third element 1-SHI is connected to the second input of the ninth element AND, the output of which is connected to the first input of the fifth element OR, the second input of the fifth element OR is connected to the output of the fourth element AND, and the output is connected to cj -out Ode to the decoder, the transfer bus is connected to the forward output of the third trigger. 20 25 thirty FIG. 2 but and j