SU1279062A1 - Decimal forward-backward counter with digital indication - Google Patents

Abstract

The invention relates to automation and computing, in particular to reversible meters with digital indication, and can be used in counting and command devices with visual display. The purpose of the invention is to increase the reliability of the operation. To achieve this goal, Dtriggers 18, 19 and the elements OR 7, 12, 17, 21 are entered into the counter. The counter also contains counting triggers 1, 6, 11, 16, decoder 2, elements OR 5,10,15, elements AND 3, 4, 8, 9, 13, 14, digital display unit 20. The use of the invention ensures the reliability of the counter in operation and allows you to eliminate errors in the counting of pulses and forms (About the world of control commands. 1 ill. (L 1 tab. J vj) about O5 y

Description

"1 The invention relates to automation and computing, in particular, to reversible counters with digital indication, and can be used in computing devices. The purpose of the invention is to increase the reliability of the operation. The drawing shows a block diagram of a decimal counter. The ten-meter reversible counter with digital indication contains the counting trigger 1, the counting input of which is connected to the input of the device, and the outputs - with the inputs sc., Ck of the decoder 2 and with the inputs of the elements 3 and 4 outputs & through the element OR 5 are connected to the counting input of the trigger 6, the reset input of which is connected to the output of the element OR 7. The outputs of the trigger 6 are connected to the inputs 6, B of the decoder 2 and to the inputs of the elements AND 8 and 9, the outputs of which through the element OR 10 are connected to the counting the trigger input 115 whose reset input is connected to the output of the element OR 12, the trigger trigger outputs 11 are connected to the inputs from and to the decoder 2 and to the inputs of the elements 13 and 14, whose outputs are connected to the counting input of the trigger 16 through the reset input 16 which is connected to the output of the element OR 17. In The outputs, trigger 16 are connected to inputs c1 and d of the decoder2. Bus Reset is connected to the reset input of trigger 1 and to the inputs of the elements OR 7, 12 and 17, Bus Addition is connected to other inputs of the elements AND 4, 9 and 14 and to the reset input B of the trigger 18 .. The subtraction bus is connected to other inputs of the elements FROM 8 and 13 to the reset input of the D-flip-flop 19. The clock inputs of the D-flip-flops 18 and 19 are connected to the input of the device. D) - D input of trigger 18 is connected to the zero output of decoder 2, and D input of p-trigger 19 is connected to output nine of decoder 2, the outputs of which are connected to digital display unit 20. Direct output of D flip-flop 19 is connected to other inputs of the elements OR. 7, 12 and 17 and to the first input of the OR element 21. Forward, output B of the trigger 18 is connected to other inputs of the elements OR 7 and 12, to the second input of the OR 21 element and to the input of the trigger setup 16. The output of the OR 21 2 element can be connected to the input of the next decade of the counter. The device works as follows. When adding to the bus, Addition is given a signal of a logical unit, and on the Bus Subtraction, a signal of a logical zero, while the logical one is fed to the reset input of trigger 18 and the trigger is set to zero. Elements 4, 9 and 14 are ready for operation, and elements 3, 8 and 13 are closed. In normal counting mode (up to nine), the decade operates as a regular binary counter. After the ninth pulse arrives at the inputs a, 5, c d D of the encoder 2, a code 1001 is set, and at the output of the ninth state of the decoder 2 the signal of the logical unit is fed to the D input of the D flip-flop 19. With the arrival In the counter of the tenth pulse, the D flip-flop 19 is set to one state, i.e. at its direct output, a logical unit signal is set and at the reset inputs of the flip-flops 6, 11 and 16, OR 7, 12 and 17 elements, respectively, receive a logical unit signal, set these triggers to the zero state, flip-flop 1 itself is shifted to the zero state the tenth input pulse. The signal of the logical unit from the output of the D-flip-flop 19 simultaneously enters the input element. OR 21 and from its release - to record in the next decade. Thus, upon receiving the tenth pulse at the device input, a code 0000 was recorded in the counter, and for the next decade a recording pulse arrived. After that, on the D-input of the Dtrigger 19, the logical zero signal is turned on and with the arrival of the 11th pulse at the input of the device, the trigger 1 is set to one state again, and the B-trigger 19 is set to zero and, thus, on the inputs resetting the flip-flops 6, 11, and 16 establishes a logical zero signal, allowing further normal counter operation. When subtracting to the bus, the Subtraction is given a signal of a logical unit, and on the bus Addition - a signal of logical zero, while the reset input of the D-flip-flop 19 is given a signal of 31

A logical unit holding the trigger in the zero state, a logical zero signal arrives at the input of the reset of the D-trigger 18, enabling the trigger to operate. Elements 4, 9, and 14 are closed, and elements IZ, 8, and 13 are ready for use.

Assume that in the subtraction mode in the lower decade the number 9 is written, then in the normal counter mode (up to 0) the decade works as a normal subtractive counter. With the arrival of the device of the ninth pulse, a code 0000 is written in the counter and the output of the zero state of the decoder 2 turns on the signal of a logical unit that arrives at the D input of the D flip-flop 18. When the device arrives at the 10th pulse 10, the trigger 1 set to one. At the same time, the D-flip-flop 18 is also set to one. The signal of the logical unit of the output of this flip-flop installs the flip-flop 16, and through the OR 7 and 12 elements the flip-flop 6 and 11. The same signal through the OR 21 element is fed to the input next decade.

Thus, with the arrival of the 10th pulse, the code 1001 corresponding to the number 9 is again recorded in the counter. At the same time, a DU flip-flop signal is set to the D input of D 18 and a D-flip-flop 18 is set to zero with the arrival of the 11th pulse and at the reset inputs of the flip-flops 6 and 11 a logical zero signal is set, which permits further operation of the counter in the normal counting mode.

The operation of the counter is described by the following state table.

Table continuation

Thus, when a decimal reversing counter is in operation, with the arrival of the tenth pulse, the outputs of the decade bits do not appear false

code.

Claims (1)

Invention Formula i The decimal reversive counter with digital indication containing four calculating triggers, the decoder, three the OR element and six AND elements, the counting input of the counter is connected to the counting input of the first counting trigger, the direct and inverse outputs of which are connected to the first inputs of the first and second AND elements, the outputs of which are connected to the inputs of the first OR element, the output of which is connected to the counting input the second counting trigger, the direct and inverse outputs of which are connected to the first inputs of the third and fourth AND elements, the outputs of which are connected to the inputs of the second OR element, the output of which is connected to the counting inputs ter of its counting trigger, the direct and inverse outputs of which are connected to the first inputs 1and the fifth and sixth elements AND, the outputs of which are connected to the inputs of the third element OR, the output of which is connected to the counting input of the fourth counting trigger, the second inputs of the first, third and fifth elements And connected to the subtraction bus, the second inputs of the second, fourth and sixth elements And connected to the folding bus, the reset input of the first counting trigger is connected to the reset bus the counter, and the trigger outputs are connected to the decoder inputs, characterized in that, in order to increase the reliability of operation, the first and second D-triggers and four OR elements are introduced into it, the addition bus is connected to the reset input of the first D-trigger, whose clock input is connected with countable the counter input connected to the clock input of the second D-flip-flop, .. whose reset input is connected to the subtraction bus, the reset bus is connected to the first inputs of the fourth, the fifth and sixth OR elements, the direct output of the first D-flip-flop is connected to the second inputs of the fourth, the fifth and the first input of the seventh OR-elements and to the installation input of the fourth counting trigger, the reset input of which is connected to the output of the sixth OR element, the second input of which connected to the direct output of the second D-flip-flop, the second input of the seventh and third inputs of the fourth and fifth OR elements, the outputs of the decoder, corresponding to states 0, are connected to the B-inputs of the first and second D-triggers, respectively.