SU1298898A1 - Counting device with checking - Google Patents

Abstract

The invention relates to automation and computer technology and can be used for tactful monitoring of binary counters. The purpose of the invention is to increase the reliability of the device. The device contains a binary counter 1, a comparison block 2, a memory block 3. To achieve this goal, a multiplexer 6, control counter 7, AND-NE element 8, OR element 9, RS flip-flop 10, AND P.1 element are entered into the device. f-ly. 2 Il. go with 00 CX) with 00

Description

The invention relates to automation and computer technology and can be used for tactful monitoring of binary counters.

The purpose of the invention is to increase the reliability of the device.

Figure 1 shows a diagram of the counting device with the control; Fig. 2 shows an embodiment of the comparison block. The device (Fig. 1) contains a binary counter 1, a comparison block 2, a memory block 3, an input bus 4, a reset bus 5, a multiplexer 6, a control counter 7, AND-HE element 8, an OR element 9, an RS flip-flop 10 , Element 11, clock frequency bus 12, output 13 of the first discharge of the control counter 7, inverse output 14 of the second discharge of the control counter 7, gate input 15 of the comparison unit 2, input 16 of the comparison unit 2, the first 17 and the second 18 the inputs of the comparison unit 2, the output bus 19, the inverted overflow output 20 of the control counter.

The counting input of the binary counter I is connected to the input bus 4 and to the input of the input element OR 9, the output of which is connected to the reset input of the counter 7 and to the reset input 16 of the comparison unit 2, the zero input of the counter 1 is connected to the second input of the element OR 9, to the input RS -trigger 10 and with reset bus 5, outputs of binary counter 1 are connected respectively to information inputs of multiplexer 6, the output of which is connected to the data input of memory block 3 and to the first input 17 of comparison block 2. The address inputs of memory block 3 are connected to the address inputs of multiplexer 6 and c. the outputs of the higher bits of the control counter 7, the output 13 of the first discharge of which is connected to the gate input of the memory block 3 and to the first input of the AND-NAND element the inverse output 14 of the second discharge of the counter 7 is connected to the control input of the memory block 3 and the second input of the element IS-NE 8, the output of which is connected to the gate input 15 of the comparator unit 2, the third input of the element NE-NE 8 is connected to the direct output of the RS flip-flop 10. The second input 18 of the unit 2 is connected to the output of the memory block 3, the output of the comparison unit 2 is connected to the output bus 19, the inverted output 20 ne epolneni counter

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7 is connected to the input S of the RS-flip-flop 10 and to the first input of the element I 51, the output of which is connected to the counting input of the control counter 7, and the second input to the bus 12 of the clock frequency.

Comparison unit 2 in (Fig. 2) contains the first D-flip-flop 21, the second D-flip-flop 22, half-adder 23, the element EXCLUSIVE OR 24, the element NOT 25, the output 26 of the element EXCLUSIVE OR 24.

The gate inputs of the first 21 and second 22 D-flip-flops are connected to the gate 15 of the comparison unit 2, the input 16 of which is connected to the input of the HE element 25. The input S of the first D-flip-flop 21 is connected to the input R of the second D-flip-flop 22 and connected to the output element 25. The D-input of the first D-flip-flop 21 is connected to the transfer output of half-adder 23, and the output is connected to one of the inputs of half-adder 23, the other input of which is connected to the second input 18 of the comparison unit 2, and the sum output - one of the inputs of the EXCLUSIVE element OR 24, another input is connected to input 17, 26 output member 24 connected to the input D of the second D-flip-flop 22. The output of the second D-flip-flop 22 is connected to output line I9.

The device works as follows.

At each cycle of operation, the input pulse on bus 4 zeroes the control counter 7 and the back differential. sets binary counter 1 to the next state. From this moment on, the generation of address codes at the output of control counter 7 begins, and the outputs of binary counter 1 are alternately connected via multiplexer 6 to the input 17 of the comparison unit 2 and to the data input of the memory block 3. At each address code, the first pulse at output 13 reads information from the corresponding cell of memory 3 to input 18, adds up with information at the output of D-flip-flop 21 and compares the received amount with input status 17. The second pulse at output 13 the information from input 17 is copied to this cell of memory block 3 and at the end of the pulse the address code is modified, and the inputs of the comparison block 2 receive the information of the counter I and the memory block 3.

Thus, a one-by-one comparison of the state of the counter in this cycle with the state of the previous cycle recorded in memory block 3 occurs.

The unit is added to the low-order code of the previous state, the transfer is memorized, and the transfer is added to the contents of the next cell of memory block 3 by a D-trigger 21 and a half-adder 23. The end of the pulse at input I5 records the result of the comparison into D-trig 22 and transfer to the next bit in D-flip-flop 21. After polling the higher bit of binary counter 1, the control counter 7 is self-blocked by the signal from the overflow output 20 until the next counting pulse arrives at the input bus 4. At the same time, in block 3 na whith the current state recorded audio code. RS flip-flop 10 is required so that when resetting counter 1 and subsequent rewriting of the initial state to memory block 3, errors in the D-flip-flop 22 are not recorded. The comparison lock is released i after the recording of the initial state is terminated by a signal from output 20 overflow.

To control a reversible binary counter, you need to enter a switch that switches inputs 17 and 18 at the beginning of the first impulse at the subtractive input of binary counter 1, and at the beginning of the first impulse - at the summing input that leads to inputs 17 and 18 .

In this case, the shift register can be used as a memory block.

Claims (2)

Invention Formula I. A control device containing a binary counter, the counting input of which is connected to the input bus, and the zeroing input - to the reset bus, the comparison unit and the memory unit, the data input and output of which are connected respectively to the first and second inputs of the comparison unit, the output which is connected to the output bus, characterized in that, in order to increase the reliability of the device, the tact bus is introduced into it five ABOUT five -five 0 frequency, control counter RS-trigger, element AND, element C-NOT, element OR and multiplexer, the output of which is connected to the data input of the memory block, information inputs of the multiplexer are connected to the outputs of the binary counter, and address inputs are the inputs of the memory block and the outputs of the higher bits of the control counter, the output of the first bit of which is connected to the sample input of the memory block and the first input of the NAND element, the inverse output of the second bit of the control counter is connected to the control input of the block memory and wto The third input of the NAND element, the third input of which is connected to the direct output of the RS flip-flop, the output of the NAND element is connected to the gate input of the comparison unit connected to the reset input of the control counter and the output of the IPI element first the input of which is connected to the input bus, and the second to the reset bus and to the input R of the RS flip-flop connected by input S to the inverted overflow output of the control counter and to the first input of the And element whose output is connected to the counting input of the controlling counter, and the second input - to the bus bars Oh frequency. 2. The device according to claim 1, of which the comparison block contains the element NOT, the first D-flip-flop, the half-adder, the EXCLUSIVE-OR element and the second D-flip-flop, the output of which is connected to the output of the comparator, gating input of the second D-flip-flop. connected to the gate input of the first D-flip-flop and the gate input of the comparison unit. The D input of the second D flip-flop is connected to the output of the EXTENDER OR element, the first input of which is connected to the first input of the comparison unit, and the second input to the output of the sum of half-adder connected by the first input to the second input of the comparison unit, and the second input to the output of the first D -trigger, the input D of which is connected to the transfer output of the half-adder, the installation input S of the first D-flip-flop is connected to the reset input of the second D-flip-flop and to the output of the NOT element whose input is connected to the reset input of the comparison unit. 18 15 Y g 17 HzId yy nineteen s W Editor A. Kozoriz Compiled by Ranov Tehred M.Hodanich Order 898/59 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. d. D / 5 Production and printing company, Uzhgorod, Projecto st., A FIG. 2 Proofreader L. Patay