SU1115236A1 - Device for trouble-free counting of pulses - Google Patents

Abstract

1. DEVICE OF UNINTERRUPTED PULSE ACCOUNT containing input bus, control bus, register, trigger and multi-digit counter, transfer output of each bit of which is connected to the clock input of the subsequent counter discharge of the counter, connected to the clock input of the first counter of the counter, outputs bits of which are connected to the information inputs of the register, characterized in that, in order to increase the reliability of reading the contents of the counter, the IL element and the NAND element are entered into it, the first, second inputs and the output of which o are connected respectively to the control bus, the inverse trigger output and the register control input, the input bus and the transfer outputs of the meter bits are connected to the inputs of the OR element, whose output is connected to the information input and input (L settings in the O trigger, the clock input is connected with bus control.

Description

2. The device according to claim 1, wherein the register contains triggers and groups of elements AND by the number of bits of the counter, the first inputs of the groups of elements AND are connected to the control input of the register, whose information outputs are connected respectively to the second inputs of groups of elements AND , the outputs of which are connected to the input of the record corresponding to the CIG triggers.

The invention relates to a pulse technique and automation and can be used in devices where meter readings are required during its operation. An uninterrupted pulse counting device is known, comprising a control unit, a counter consisting of a group of low-order bits and a group of high-order bits. counter, decoder and element The disadvantage of this device is its relative complexity. It is also known a device containing an input bus, a control bus register, three triggers, an element NOT and a multi-bit counter, the transfer output of each bit of which is connected to a clock input of the next bit, the input bus is connected to the clock input of the first bit of the counter, such as the input of the first trigger, the input of the element NOT, the output of which is connected to the clock input of the second trigger, the information input of which is connected to the information input of the first trigger and the control bus; the outputs of the counter bits — with the information of the MaipiOHHbiMH register inputs, the control input of which is connected to the output of the second trigger, information and The inputs of the third trigger are connected respectively to the inverse code of the second and direct output of the first trigger C2l. At the same time, the duration of the readout time must be longer than the period of incoming pulses, but less than one and a half periods of input pulses. However, for a known device, there is a lack of accuracy in reading the contents of the counter in the event that pulses are received on the input bus, the minimum possible period — which is many times less than the time required for reading into external devices. The purpose of the invention is to increase the reliability of reading the contents of the counter. The goal set is achieved by the fact that an uninterrupted pulse counting device containing an input bus, a control bus, a register, a trigger and a multi-digit counter, the transfer output of each bit of which is connected to the clock input of the next bit counter, is connected to the clock the input of the first digit of the counter, the outputs of the bits of which are connected to the information inputs of the register, the element OR and the element NAND are entered, the first, second inputs and the output of which are connected respectively to the control bus, to the inverse The trigger output and the register control input, the input bus and the carry outputs of the counter bits are connected to the inputs of the OR element, the output of which is connected to the information input and the set input on the trigger, whose clock input is connected to the control bus. In addition, the register contains triggers and groups of elements AND by the number of bits of the counter, the first inputs of the groups of elements AND are connected to the control input of the register, the information inputs of which are connected respectively to the second inputs of the groups of elements And whose outputs are connected to the recording inputs of the corresponding triggers. The drawing shows the scheme of the proposed uninterrupted pulse account. The device contains a multi-bit counter 1, bits of a large 3 counter 1, register 2 groups of elements AND, triggers, element OR 5, trigger 6, element AND-NOT 7, control bus 8 and input bus 9. The outputs of bit transfers and are connected respectively, with these input inputs of bits and, input bus 9 - with a clock input of counter 1, the outputs of which bits are connected to the information inputs of register 2, the first, second inputs and output of the AND-NOT element 7 are connected respectively to the control bus 8 , inverse trigger output 6 and control input of the register 2, the input bus 9 and the transfer outputs of the bits of the counter 1 - with the inputs of the element OR 5, the output of which is connected to the information input and the input of the installation in O of the trigger 6, the clock input of which is connected to the bus 8 of the control, the first inputs of the groups of elements And are connected with the control input of the register 2, the information inputs of which are connected respectively to the second inputs of the groups of elements AND, whose outputs are connected to the recording inputs of the corresponding triggers. I. The device works as follows. Counter 1 counts the pulses coming through the input bus 9. The output state of the bits of counter 1 during the counting process is continuously transferred to register 2 through the groups of AND elements available in register 2 to triggers. On the control input of register 2 from the output of the element, the permissive potential arrives all the time. To remove information from the outputs of register 2, a signal is sent to bus 8, which, via trigger 6, AND-NE element 7 removes the enable potential from the control input of register 2. At this time, information access to register 2 is stopped. However, it is possible to stop accessing information from counter 1 to register 2 after the end of transients (transfer) in all bits of counter 1. Otherwise, the information may be recorded in the buffer register with errors. In order to eliminate these errors, the inputs of the element 64 OR 5 have feedbacks from all the outputs of the counter transfers. Prior to the beginning of transfer processes, the output of the element OR 5 is established by a logical O, which sets the trigger 6 to the state O on the reset input. At the inverse output of the trigger 6, logical 1 is set, fed to the first input of the element AND-HE 7, but before the read signal arrives the second input element AND-NOT 7 signal has the potential of logical O, therefore at the output of the element AND-NOT 7 there is a logical 1, i.e. resolving potential, supplied control register input 2. In case the read signal on bus 8 arrives at MOMCTIT, when the transients in the bits of counter 1 are not completed, the output of the element OR 5 is logical 1 and the read positive front bus signal 8, the trigger 6 is set to one state and the zero potential from the inverse output of the trigger 6 blocks the signal from passing through them. Not through the NAND element 7. After the transient processes in the counter 1, the output of the OR 5 element appears With a log O, trigger 6 returns to its original state and the signal on bus 8 passes through the NAND 7 element, access of information from the bits of counter 1 to register 2 is terminated, and from the outputs of trigger register 2, information is readable. If at the moment of the arrival of the readout signal in the counter 1 a transient occurs, the counter readings are fixed in the register 2 and read from the outputs of the register 2 only after its completion, which ensures the correctness of the readout. Thus, for the time of reading the information from register 2, the code of the number of pulses counted by counter 1 at the time of arrival of the read signal on bus 8 remains fixed, while counter 1 continues to count incoming pulses and the input information is not lost. After the end of reading, the group of elements AND is opened and the register 2 assumes the state corresponding to the current state of the counter 1.

51115236

Thus, the introduction of a new opportunity to realize the weight-constructive signs of a favorable interrupted counting of pulses without

distinguishes the proposed read time limiter device

from the famous, as by ownership.

Claims (2)

1. DEVICE FOR AN UNINTERRUPTED PULSE ACCOUNT containing an input bus, a control bus, a register, a trigger, and a multi-bit counter, the transfer output of each bit of which is connected to the clock input of the next bit of the counter, the input bus is connected to the clock input of the first bit of the counter, the outputs of which bits are connected to the information bits of which register inputs, characterized in that, in order to increase the reliability of reading the contents of the counter, an OR element and an NAND element are entered into it, the first, second inputs and output of which are connected inens, respectively, with the control bus, the inverse trigger output and the register control input, the input bus and carry outputs of times of the meter rows are connected to the inputs of the OR element, the output of which is connected to the information input and the setting input to the trigger 'O' *, clock whose input is connected to the control bus. 2. The device according to claim 1, characterized in that the register contains triggers and groups of elements AND by the number of bits of the counter, the first inputs of the groups of elements AND are connected to the control input of the register, the information outputs of which are connected respectively to the second inputs of the groups of elements AND whose outputs are connected to the recording inputs of the corresponding triggers.