SU1185394A1 - Storage - Google Patents

Abstract

The MHALL EE DEVICE ALARM, which contains the address registers, the number register, the switch, the decoders, the encoder, the AND group of elements, the OR group of elements, and the drive consisting of the main memory cells whose address inputs are connected to the outputs of the first address register, and the binary inputs and the outputs are connected respectively to one of the outputs of the number register and to the first inputs of the AND elements of the first group, the outputs of which are connected to the first inputs of the OR elements, the second inputs of which are connected to the outputs of the AND elements of the second group, and the outputs to the inputs of the switch, the outputs of which are connected to the first inputs of the elements of the third group and one of the inputs of the number register, the outputs of the second address register are connected to the inputs of the first decoder, the outputs of which are connected to the control inputs of the switch, the outputs of the second decoder are connected to the inputs of the encoder, the first inputs And the second group of elements and the outputs of the elements of the third group are respectively one of the information inputs and outputs of the device, the second inputs of the elements of the first and third groups are combined and are the first control input of the device, the second control input of which is the second inputs of the AND elements of the second group, characterized in that, in order to increase the information capacity of the device, AND elements, OR elements, HE elements and additional memory cells whose address inputs are connected (L to the outputs of the first address register, and the bit inputs and outputs respectively to the other outputs of the number register and to one of the inputs of the second decoder, the other inputs of which are connected to the outputs of the second address register, and the synchronization input is connected to the output of the first element, and the output of the first element AND is connected to the input of the second: about the NO element, the output of which is connected to the first control inputs of the main memory cells, the second control inputs which are connected to the outputs of the encoder, the output of the second element I is connected to the input of the third element NOT, the output of which is connected to the first control inputs of the additional memory cells, the second control inputs of which are connected to the output of the third element I, the first input d is connected to the output of the first OR gate and the first input of the fourth AND gate, whose output

Description

connected to the input of the first element is NOT, the second input of the third element is AND connected to the output of the second element OR, the second input of the fourth element AND is connected to the output of the third element OR, the first input of the first element OR is connected to the second inputs of the AND elements of the first group, the first input of the first element AND and the second input of the first element OR is connected to the second inputs of the AND elements of the second group, (The first input of the second element AND is the third control input of the device, the fourth control input of which is the control input the address registers, the first input of the second element OR, and the control input of the number register are the fifth control input of the device, the sixth control input of which is the second input of the second and first input of the third OR element, and the seventh control input is the third input of the second element And, the second input of the third element OR and the second inputs of the first and second elements I.

The invention relates to computer technology and can be used in the construction of processing devices for variable-length data, as well as in computer numerical control systems built on microcomputers for storing programs and arrays of short words. The aim of the invention is to increase the information capacity of the device. FIG. 1 shows the functional scheme of the device; in fig. 2 - the same, the most preferred option for the implementation of the switch; in fig. 3, too, of the most preferred embodiments of the second decoder and encoder; in fig. 4 - possible to arrange the placement of words in the accumulator cell; in fig. 5 is a timing diagram explaining the operation of the device in read, write, and initial fill modes. The device contains a memory 1, consisting of the main cells 2 of the memory intended for storing the information part of the word, and additional cells 3 of the memory intended for storing the pointer of the format of the group of words, the first register 4 of the address, the register 5 of the number, the first group of elements And 6 , the group of elements OR 7, the switch 8, the second 9 and the third 10 groups of elements AND, one of the 11 inputs of the register 5 numbers, information inputs and outputs 12 of the device, the other inputs 13 of the register 5 numbers. The device also contains the second address register 14, the first 15 and second 16 decoders, the encoder 17, the first element is NOT 18, the first control inputs 19 and 20 respectively of the main 2 and additional 3 memory cells, the first element And 21, the second 22 and third 23 the elements are NOT, the second is 24 and the third is 25 elements AND, controls the inputs 26-28 from the first to the third and the address inputs 29 of the device. The device also contains the fourth element AND 30, the first 31, the second 32 and the third 33 OR elements, the control inputs (from the fourth to the seventh) of the device. Switch 8 (Fig. 2) contains k groups of two-input elements And 35, intended for switching a word with a shift by (i-1) ra bits, where i is the number of a group of elements And 35, ha is the byte width, and k is the maximum the number of bytes in the cell of accumulator 1 (in the example of FIG. 2 and four); inputs and control inputs 37, elements SHSh 38, groups of outputs 39. FIG. 3, synchronization input 40, inputs 41 and 42 of the decoder 16 are indicated. Shfrator 17 contains AND-HE elements 43 with outputs 44. FIG. 4 shows the combinations of word groups in cell 1 of the accumulator for the maximum number of bytes placed in the cell of accumulator 1, for example, four, the byte address width equal to two, and the format pointer width equal to two, while the number of combinations of the word group in The storage cell 1 is limited to four options.

In the first column in FIG. 5, a format pointer value is placed. The Z value of the format indicator is defined by the number, size and placement of the layers in the cell. For the example in FIG. 3 and 4, when in the cell, Pit 1 has one word of 4t, the address of the low byte, coming from register 14,, 00

When in a cell, two words of m are located with addresses of lower bytes and.

When in a cell, two words with a size of 3 m are located with both the address and the digit S and with the address.

When in a cell, words are located in order of digitization with the addresses 00, 01, 10, 1.1.

FIG. Figure 5 shows three cycles of operation of the device corresponding to the three modes: samples (Tvj), records (b) and initial filling (T,).

FIG. 4 denotes the clock signals C1-C4 cycles from the first to the fourth, arriving at the inputs, respectively, signals Uj, 1) 27 at the inputs 26, 27 and 28 respectively, the signals Y25,, Y, Y. at the outputs of the elements And 25, And 30, registers 4 and 14, respectively, signals i4, respectively, at inputs 20 and at the outputs of element I24, signals Y at inputs of memory cells 3, equal to the Z value of the format indicator, signals 2.1, respectively at inputs 19 and at the output of element 21, signals Yj and respectively at the outputs of the cells 2 and elements And 10.

As cells 2 and 3, memory in the device can be used, for example, microcircuits of the type K565RU1. As the decoder 16 can be used, for example, chip K155VDZ.

The operation of the device is based on the following principle.

Let k be the maximum number of bytes that can be placed in the cell of accumulator 1. The number of ways in which the words of this set can be located in the cell of accumulator 1 (Fig. 1) is equal to the number

ways in which you can represent the positive integer k as the sum of positive integers. I additional bits are entered into the drive 1, i.e. cells 3 that encode the number of one of the word group combos If the location of this group of words is imposed such a restriction that larger words are always to the left of the smaller words, the combination number Z, recorded in cells 3, is uniquely determined by the byte address em word lengths. For this

UZ6 {l, ... ,, a | 7, logjCptk)

As follows from above, there is no information about the format of operands explicitly in the command. Saving memory is achieved due to the fact that additional bits are used to indicate the format of a group of words located in high-resolution cells 2, and the memory cost per indication of the length of a given word is one-time and does not depend on the number of commands in which the word is used.

For the example of operation of the device in accordance with FIG. 2 and FIG. 3 The maximum number of bytes that can be placed in the cell of drive 1 k is four. Then the byte address width is two. We take the value of the bit size of the format indicator equal to two, then the number of combinations of a group of words in a cell is limited to four options, on (Fig. 4).

Thus, in this example, it is possible to have nine different combinations at the inputs of the decoder 16. Each of them corresponds to a combination at the outputs 44 of the encoder 17, containing as many units as the bytes contains the selected (recorded) word. The location of these units must correspond to the location of the word being chosen (recorded), i.e. blocks 16 and 17 implement the following code conversion:

code on the input of the decoder 16

0000

0100 01 10 10 00

1001

1100 11 01

11 10 11 11

code on the output of the decoder 17 1111 0011 1100 0001 1110 0001 0010 0100 1000

The formation of such combinations is provided by connecting the outputs of the block 16 and the inputs of the elements 43, as shown in FIG. 3

The required timing diagram (Fig. 5) is provided with the aid of the elements OR 32 and 33, as well as the four-stroke sequence of clock pulses, arriving at the inputs 34, -34.

From the inputs 29 to the inputs of the register 4 enters the address of the word, and to the inputs of the register 14 - the address of the byte in this word.

By signal C1, address codes from inputs 29 are recorded in registers 4 and 14. In each second cycle, by signal C2, codes 5 are written to register 5 from inputs 11 - the information part of a word, from inputs 13 - the value of the format indicator. I

At zero values at the inputs 26-28, the device is in the information storage mode. at input 26 and O at inputs 27 and 28, the device is in the sampling mode of FIG. 5 cycle T. As indicated above, in the first clock cycle on the outputs of registers 4 and 14, the word and byte address signals are set. The address of the word is also set on the address inputs of all cells 2 and 3 of the drive. The byte address is fed to the inputs of the decoders 15 and 16. In the same cycle, the byte address converted by the decoder 15 to code 1 of k is set at the inputs 37 of the switch 8.

Since the inputs 27 and 28 are zeros, then the inputs 19 and 20 are units and checks 2 and 3 are in read mode.

The elements AND 25, OR 31 and 32 implement the function

,, ay ,, (u, vu ,,) a

A (C2VC3VC4).

where Y is the signal value at the output of the And 25, OR 31 and ShII 32 elements, respectively, i.e. when U 1, the signal Ug 1 is present at the inputs of 20 cells 3 during the second, third and fourth cycles.

During this time, the format pointer moves from the outputs of the cells 3 to the inputs of the decoder 16 to tO.

Elements 18, 31, 30, and 33 implement the function

1 (,) A (C3VC4), i.e. A zero signal is set at the input 40 of the decoder 16-15 during the third and fourth cycles (Fig. 5). During this time, information about the length of the selected word is converted by the decoder 16 into code 0 1 from M, where is the byte address width (in the considered example), and is fed to the inputs of the encoder 17. At the outputs of the encoder 17, a mask code corresponding to 5 appears. the length of the selected word and its location in the cell, according to the code conversion table in blocks 16 and 17 above.

As a result, the masking word 0 enters the inputs of 19 cells 2. This ensures reading of information from the necessary bits of drive 1 at the address received from register 4. Signals at inputs of 19 cells 2 5 are present during the third and fourth clock cycles. Readable information during the third cycle

installed at the outputs of cells 2 and at the outputs of the elements And 6.

0 „

According to the byte address,

received from the register 14, the signal from the output of the decoder 15, arriving at one of the inputs 37 of the switch 8, elements 35 of one of the groups of block 8 are unlocked in the first clock. For example, this will be (n + 1) - the group, where n is the byte address , then the word shifted by nm bits is fed to the inputs of the AND 10 elements, corresponding to 11 MCH lower bits of the inputs and outputs 12. After the transitions to the beginning of the fourth clock cycle are completed, the signals corresponding to the selected code are set to the lower bits of the inputs 12, and the signals for the rest bit dah inputs and The outputs 12 are equal to zero, when the end of the fourth cycle ends, the signals at inputs 19 and 20 of cells 2 and 3 are zeroed out, and the sampling operation ends. Device operation in read and write modes. For example, let the spruce located in the positions of the third and fourth bytes of the cell having (Fig. 4) be read. The contents of register 14 is 10, i.e. During the second, third and fourth cycles, the inputs of the decoder 16 are given a combination of 0110, which provides a combination of 1100 at the outputs of the encoder 17. Therefore, only signals of the two high bytes will be present at the inputs of 19 cells 2. there. At the outputs of the excited cells 2 in the TC signals corresponding to the read word. At the outputs of the other cells 2, zero signals are stored. At the inputs of decipher1 15 in this example, code 10 is present, which provides a single signal value at the third (out of four) output of the decoder 15, i.e. the third one, counting from the left, the input 37 of the switch 8 (Fig. 2) will be excited. The third group of elements I 35, opened by a signal from input 37, will commute signals that correspond to the selected word, from inputs 36 and 36 to outputs ZUa and ZU ,. The inputs 36 and 3b2 from the outputs of cells 2 receive two high-order bytes, which from outputs 39 and 3 of the storage unit 4 and elements 10 go to the lower bits of the inputs 12. TaKiiM, as a result of switching, the read bytes are shifted to the right and placed there are them in the lower bits of the outputs 12. At 1, the device is in recording mode. In this mode, the word from the lower bits of the inputs 12 must be written into the information part of accumulator 1 in accordance with the word address and byte address, and the contents of the remaining bits of the cell should be saved. For this, a mask must be formed in the same way as when performing the sampling operation, i.e. depending on the byte address and format pointer at the word address. Thus, when recording the cells 2, the corresponding information part of the accumulator 1 is in the recording mode, and the cells 3 corresponding to the format indicator are in the read mode, the mask is formed as described above (Fig. 5), namely ; in the third cycle, at the inputs 19 of those cells 2, into which the input word is to be written, single signals are received coming from the outputs of the encoder 17. Since 1, through the open elements AND Y, elements OR 7, one of the groups of elements And 35, the open signal from the decoder 15 in the first cycle, the signals corresponding to the input word, are fed to the inputs 11 and the signal C2 is written to the register 5. And the signal C4 unlocks the element 21, and in the fourth cycle forms the zero signal at the output of the elements NOT. This ensures that the contents of the corresponding bits of register 5 are written to the selected cells 2, and the contents of the remaining bits of it are irrelevant. This completes the write cycle. The entry or change of the format indicator in the cells 3 is performed in the initial filling mode, which can be performed once before the start of solving a complex of tasks or by the program before solving the next task that requires reconfiguring the device for storing data of a different format. To record the format indicator, inputs 1, 0, 0 are set at inputs 26 through 28, respectively. In the first cycle, the address of the word is written to register 4 and set at the address inputs of the drive. In the second clock cycle, a new value of the format indicator from the corresponding bits of the inputs 12 to the inputs 13 is written into the bits of the register 5, corresponding to the format indicator. In the second, third, and fourth cycles, the signals UgK, 1 of FIG. 5 cycle Tj. By signal C4, element 24 is unlocked, and in the fourth cycle a zero signal is formed at inputs 20, which ensures that the format indicator is written in the micro cells 3. In FIG. 5 (lyiKn T,) shows an example of the organization of the initial filling mode, when during recording the format indicator only the cells 3 are working, whose states can

9

change. The information recorded in the cells 3 can come from any bits of the inputs 12 which are connected to the inputs 13 of the register 5.

Thus, the indication of the word length is carried out for a group of words, and the pointer is located directly in the cell and accumulate 39410

l 1 storing a group of words. Specifically, the word length is determined by the result of the joint analysis of the format indicator and the address of the low byte of the selected word, which leads to memory savings, especially in the case of multicast commands and the use of operands of different lengths in one command.

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Claims (1)

A MEMORY DEVICE containing address registers, a number register, a switch, decoders, an encoder, an AND element group, an OR element group and a drive consisting of main memory cells whose address inputs are connected to the outputs of the first address register, and the bit inputs and outputs are connected respectively to one of the outputs of the number register and to the first inputs of AND elements of the first group, the outputs of which are connected to the first inputs of the OR elements of the group, the second inputs of which are connected to the outputs of the AND elements of the second group, and the outputs to the inputs I will give a switch, the outputs of which are connected to the first inputs of AND elements of the third group and one of the inputs of the number register, the outputs of the second address register being connected to the inputs of the first decoder, the outputs of which are connected to the control inputs of the switch, the outputs of the second decoder are connected to the inputs of the encoder, the first inputs of Comrade And the second group and the outputs of the elements And the third group are respectively one of the information inputs and outputs of the device, the second inputs of the elements And the first and third groups are combined and are the first control input of the device, the second control input of which is the second inputs of AND elements of the second group, characterized in that, in order to increase the information capacity of the device, AND elements, OR elements, NOT elements and additional memory cells are introduced into it, § address inputs which are connected to the outputs of the first address register, and the bit inputs and outputs, respectively, to the other outputs of the number register and to one of the inputs of the second decoder, the other inputs of which are connected to the outputs of the second address register, and the synchronization input is connected to the output of the first element NOT, moreover, the output of the first element AND is connected to the input of the second element NOT, the output of which is connected to the first control inputs of the main memory cells, the second control inputs of which are connected to the outputs of the encoder, the output of the second element AND is connected to the input of the third element NOT, the output of which is connected to the first control inputs of additional memory cells, the second control inputs of which are connected to the output of the third element And, the first input of which is connected to the output of the first OR element and the first input of the fourth AND element, the output of which is connected to the input of the first NOT element, the second input of the third AND element is connected to the output of the second OR element, the second input of the fourth AND element is connected to the output of the third OR element, the first input of the first OR element is connected to the second the inputs of the AND elements of the first group, the first input of the first AND element and the second input of the first OR element are connected to the second inputs of the AND elements of the second group, <the first input of the second AND element is the third control input of the device, the fourth control input of which is the control inputs of the address registers, the first input of the second OR element and the control input of the number register are the fifth control input of the device, the sixth control input of which is the second input of the second and first input of the third OR element, and the seventh control input is the third input of the second element And, the second input of the third OR element and the second inputs of the first and second elements I.