SU1334140A1 - Data input device - Google Patents

Abstract

The invention relates to automation and computer technology and is intended to manually enter information into a computer. The aim of the invention is to simplify and improve the speed of the device, including the keyboard 1, the chatter protection unit 2, the unit 3 control and control unit, the registers 4, the first display unit 5, the trigger 6, the first and second elements H-7 and 8, counter 9 , the decoder 10, the switching element 12, the second block 11 of the display. The device allows you to perform new functions that are implemented with relatively less hardware costs: writing characters (Face) an indication of the bit into which the next input character is written. 1 il. (L

Description

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The invention relates to automatic storage and computing and can be used to manually enter information into a computer.

The purpose of the invention is to simplify and increase the speed of the device. The drawing shows a diagram of the proposed device.

The device consists of a keyboard 1, chatter protection unit 2, encryption and control unit 3, registers 4, first indication unit 5, trigger 6, first 7 and second 8 IG-NE elements, counter 9, decoder 10, second indication unit 11 and switching element 12.

The device works as follows.

The operator dials the message by successively pressing the corresponding keys of the keyboard 1. Information from the keyboard 1 through the bounce protection unit 2 enters the encryption and control unit 3, which performs the encoding of the entered information with a binary-decimal code,

In addition, block 3 determines the reliability of the encoded information. If no error is detected, block 3 generates a short unit impulse on the leading edge of the information signals at its shift output. When an error is detected in the input ratio (for example, two adjacent keys are accidentally pressed), the shift pulse at the output of block 3 is absent.

In the initial state (the trigger input mode is in the zero state. The zero potential at its direct output sets the output of the NAND 7 element to the single state, prohibiting the presetting of the counter. The single potential at the inverse trigger output allows the pulses to pass through the AND element -ONE 8. When entering information, the shift pulses from the shift output of block 3 through the IS-NE 8 element are fed inversely to the summing input of the counter, which performs the calculation of the shift pulses. a shift in one of the decoder outputs a potential discontinuity is formed from the zero level in the unit, and a selecting discharge osuschest- is parallel S. 1st entry information with the decoder output information to the selected register.

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The second display unit 11 is a set of LEDs, the number of which is equal to the number M of decimal places. The appearance at one of the outputs of the zero-level potential decoder triggers the corresponding indication element of the 11U block. Each LED is located on the front panel of the device under the corresponding digital indicator of the first block 5. Thus, the ON LED always shows the operator that bit next character entered.

The operator checks on the first block 5 the indicator that the typed message is correct and gives the command to read.

If it is necessary to change the value of a certain bit (correction mode), the operator turns the switching element 12 on and off (button-Enter bit number), as a result, the trigger is set to one, and dials the digit number on the keyboard. At the same time, the inverted shift pulse arrives through the NAND 7 element to the synchronous input of the counter, which pre-sets the counter by the value of the number of the selected digit. At the same time, the zero potential at the inverse of the trigger output maintains the output of the AND-HE element 8 in a single state, which precludes an increase in the counter value by one. At the end of the shift pulse at the output of the NAND 7 element, a potential differential from zero to one level is formed, which is fed back to the forward dynamic trigger trigger input via the feedback circuit, transferring it to the zero state, since the trigger trigger information input is connected to bus logical zero. At the output of the decoder corresponding to the correctable discharge, a potential of zero level is formed, indicated by the corresponding LED of block 11. Then the operator enters the required symbol. At the same time, a shift pulse is generated through the AND-NE element 8 (as in the input mode) to the summing input of counter 9, which causes a change in the corresponding output of the decoder from the zero to one level,

which ensures reliable recording of the character in the selected register 4.

To enter the next character, the operator must switch the device back to the correction mode and dial the number of the first free bit.

To correct the last m of entered characters for the orator, it is not necessary to include switching element 12, and then enter the number of correctable bits and the required characters m times. This operation is performed by pressing gp once on the special key on the Back key, which causes the passage of m pulses from the control: block output. 2 bounce protection to the subtracting input of the counter 9. Then the operator enters a sequence of the required characters.

The proposed device has enhanced functionality, which is realized with relatively lower hardware costs as compared with the known device. It is possible to correct the last m of incorrectly entered characters by applying a face type correction, as a result of which the operator does not need to enter the number of correctable bits m times, which increases the speed of the device in the correction mode. The introduction of the display unit improves the operator's performance, since the probability of errors during input and correction of symbols is reduced, since the included display element always shows the bit into which the next entered symbol will be recorded. The use of an encoder, self-amplifying signal, shift, allows you to write characters in parallel code, resulting in no need to use a code conversion unit, which increases the speed of the device in input mode (because the recording takes place in one rather than four cycles ). The introduction of a counter with presetting of the selected code, as well as forward and reverse counting inputs allows to exclude the registers of symbols and addresses, which allows reducing the hardware

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Order 3963/45.

Random polygons pr-tie, Uzhgorod, st. Project, 4

costs and expand the functionality of the device (correction type slaughter). The arrangement of the LEDs on the front panel of the device under the corresponding digital indicators of the display unit 5 increases the convenience of the operator's work.

Claims (1)

Invention Formula A device for entering information containing a keyboard, a bounce protection unit, an encryption and monitoring unit register, the first display unit, the trigger, the counter, the switching element, the decoder, the keyboard outputs are connected to the inputs of the bounce protection unit, the output group of which is connected to the inputs of the encryption and control unit, the outputs of the registers are connected to the inputs of the first display unit and the outputs of the decoder are connected to the corresponding register synchronization inputs, characterized in that, in order to simplify and increase the speed of the device, the second block display, two elements are introduced into it NAND, information outputs of the block of control and control are connected to information inputs of registers and inputs of pre-installation of the counter, the outputs of which are connected with the inputs of the decoder, the outputs of which are connected to the inputs of the second display unit, the reset input of the registers, the counter, the trigger are the reset input of the device, the installation input to the trigger unit is connected to the logical zero bus via the switching element, the trigger information input is connected to the logical zero bus, the forward trigger output is connected to the first input of the first NAND element, the output of which is connected to the counter and trigger trigger inputs the trigger output is connected to the first input of the second NAND element, the output of which is connected to the summing input of the counter, the second inputs of the NAND elements are connected to the control output of the encryption and control unit, the output of the Bounce protection unit is connected subtraction input of the counter. Circulation 672 Subscription