SU1290358A1 - Device for converting expressions in polish backward notation - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to increase the reliability of operation by ensuring the control of the pairing of the opening and closing brackets, the belonging of the characters / input expression to the set of lexical units of the balance of operators and operations, ensuring the classification of errors and speed. The device contains register 1, deparator 2 lexical units, memory block 3, decoder 4, microprogram control block 5, reversing shift register 6, switch 7, registry 8. 6 Il. nt W cond 00 gjuf.t

Description

fO

15

20

25

The invention relates to computing technology and can be used in automated data processing systems and the production of programs for electronic computers.

The aim of the invention is to increase the reliability of work by ensuring control of the pairing of the opening and closing brackets, the reliability of the characters of the input expression to a set of lexical units, the balance of operators and operations, ensuring the classification of errors and speed performance.

FIG. 1 is a block diagram of the devices in FIG. 2 is a block diagram of the memory block; FIG. 3 is a block diagram of the microprogram control block in FIG. 4 — a scheme of the reversible shift register in FIG. 5 — a scheme of the reversible shift register of the memory block / in FIG. 6 is a block diagram of the microprogram control device.

The device contains register 1, decoder 2 lexical units, memory block 3, decoder 4, firmware control block 5, reversing shift register 6, switch 7, register Sijreversive shift registers 9, programmable logic array AND 10, programmable logic array OR 11, memory node 12, element OR 13, generator 35, 14 clock pulses, trigger 15, delay element 16, element 17, trigger group 18, group 1 9 elements OR, group 20 elements AND, group 21 triggers, group 40 Pu 22 elements OR, group of 23 elements And, element H E 24, Node Record Node 25.

Register 1 is used to store the next lexical unit of the original expression, the decoder of 2 lexical units divides the lexical units into operands, operations, brackets.

Memory block 3 is a memory with the successive addressless writing and reading principle. The decoder 4, together with the memory unit, implements the logical function of generating and comparing priorities.

five

thirty

55

Microprogram control unit 5 organizes the interaction of all elements of the device and its functions.

The configuration is described by a microprogram control block diagram (FIG. 6), where the input signals X, x, x form a decoder 4, cc noxg- decoder 2 lexical units, x ,, x, (,, - control unit 6, micro signals commands from y to y, g forms the firmware control block 5. The meaningful meaning of the input signals and micro-instructions is the following:

1, if the progress of the operation listed in the upper bits of the shift registers of the memory block 3 has a higher priority than the operation code listed in the previous bits of the registers - otherwise.

1o

one.

g

}

if the contents of the higher bits of the shift registers of memory block 3 are equal to the code value Empty symbol O, otherwise.

1, if the contents of the upper digits of the shift registers of memory block 3 are equal to the code value of the opening bracket

O - otherwise

one

I About 1.

if the next lexical unit of the original expression is an opening bracket j

- Otherwise, if the next lexical unit of the original expression is an operand;

-otherwise.

one,

x

x

if the next lexical unit of the original expression is operand O, otherwise.

if the next lexical unit of the original expression is terminating with 0, otherwise.

1, if the next lexical unit of the original expression is the end of the expression j j

Oh, otherwise.

1, if the contents of the third bit of the reversing register of the 6 shift is a unit

Oh, otherwise.

if the contents of the first bit of the reverse register 6 shift is unit5

-otherwise.

, if the contents of the fourth bit of the reverse register 6 shift eqTb unit,

-otherwise,

unlock / lock register 1,

write the contents of register 1 to the N-e (senior) bits of the shift registers of the memory block;

thirty

35

shift the contents of memory block shift registers to the left switch 7 to write from register 1j, set initial values 20 of register 6 (code value 0100) and shift registers of memory block 3 (code value O in (N-1) bits), give a signal errors There is no closing bracket, switch switch 7 to write from (N-1) bits of shift registers of memory block 3 J. shift right by one bit the contents of the shift of memory block 3,

switch switch 7 to write from N bits of shift registers of memory block 3, issue an error signal Missing opening bracket, issue an error signal Lexical unit does not belong to the alphabet of lexical units}

give an error signal The number of operands is equal to the number of operations. Operand J is omitted. Shift the contents of register 6 to the right by one bit, - shift the contents of register 6 to the left by one bits;

increase error signal The number 50 operations is greater than the number of operands. Operand is missing; increase error signal The number of operands exceeds the number of operations by more than one. 55 Omitted operation.

Register 6 checks for the presence and order of lexical items.

V4 V y, y

y

Do, oh ..

45,

/ABOUT

 five

0

five

0

0 5

0

five,

in the original expression and in conjunction with the firmware control unit, it classifies errors, Switch 7 controls the transfer of lexical units, and register 8 is designed to store the next lexical unit in the form of Polish inverse recording. The reversible shift registers of memory block 3, one bit at a time, shift the operation code and, together with the decoder 4, perform a comparison of priorities. The programmable logic matrix AND 10 together with the programmable logic matrix OR 11 and the memory management unit 12 organizes the 3iTOT operation of the microprogram control unit. Element OR 13 generates a Stop device signal. The generator 14 clock pulses together with the trigger 15 and the element And 17 organize the start signals of the device. The delay element 16 is intended for the initial installation of a block memory node before the device is started.

A group of 18 triggers of the control unit forms four bits of the reverse shift register, each of which corresponds to a specific error class of the control unit. Groups of 19 elements OR, together with groups of elements AND, organize the input circuits of the reverse shift register in such a way that the initial installation corresponds to the installation of the second trigger (FIG. 4) in one state and the rest in zero.

A group of 21 triggers of the reverse shift register of the memory block forms bits of the reverse shift register. A group of 22 items of the PWR together with a group of 23 elements AND and an element NOT 24 organize the input circuits of the reversing shift register of the memory block in such a way that the initial installation corresponds to the setting of the bit preceding the oldest (FIG. 5) in O. Herewith the element NOT and the elements associated with it form a register 25 register bit register 1, designed to organize information input reversible; shift register memory block.

The device works as follows.

The lexical units of the original expression are successively entered into

register 1, and then to the decoder 2 and to the high-order bit of the memory block 3, the decoder separates them into allocations, operations, parentheses, closing brackets, and end of the expression;.

If the next lexical unit is an operand, the decoder 2 starts the microprogram control unit 5, the control signals of which (microcommands y, y) switch switch 7 to write the lexical unit from register 1 to register 8, and also shift to the right by one time The contents of register 6. If the content of the fourth bit of register 6 is zero, which means there is no error. The number of operands exceeds the number of operations by more than one, the transition to the analysis of the next lexical unit takes place. the fourth bit of register 6 is one, which corresponds to the presence of an error. The number of operands exceeds the number of operations by more than one. The operation is skipped, the microprogram control unit 5 generates the register 1 micro commands (y.) And the error signal (y, g). The number of the operand exceeds the number of operations by more than one. Omitted operation

register 1 in the higher bits of the shift registers of memory block 3, shift the register 6 to the left by one bit, shift register 6, block register 1. If the contents of the first bit of the shift register 6 are one, the firmware control unit 5 generates an error signal. operands. An operand is missing, Stop is formed, and the translation process is terminated. If the contents of the first bit of shift register 6 is zero, the decoder 4, which receives the contents of the higher and preceding high bits of the shift registers of memory block 3, generates a logical signal of the priority ratio of the current and preceding operations. If the operation code listed in the upper bits of the shift registers of memory block 3 has a higher priority than the operation code recorded in bits preceding the upper bits, the decoder 4 starts the firmware control block 5, the control whose signal shifts to the left by one bit. The contents of the shift register registers of the memory block 3 are then unlocked by register 1, and the process proceeds to the analysis of the next lexical unit. If the operation code is entered into the higher bits of the shift registers of memory block 3,

those are formed Stop, and the transfer process is terminated.

If the next lexical unit 35 is less than or equal to the operation code, then there is an opener bracket, a decoder 2 carried in the preceding ones

bits of shift registers of memory block 3, decoder 4 starts microprogram control block 5, the control signal of which (microinstruction) switches switch 7 to write the contents of the preceding high bits of shift registers of memory 3 to register 8. Then block The 5 microprogram control shifts one bit to the right (micro commands U) the contents of the shift registers of memory block 3. The procedure for enabling switching of switch 7 to a record containing a blocking register 1 is played by the following: elders senior - a transition to the analysis of the next lexical level of the shift registers of unit 3 of the memory unit.S register 8 and resolution of the right shift. , in the contents of the shift registers of the block. If the next lexical unit of the 3 memory is executed until there is an operation, the decoder 2 of the lexical 55 while in the preceding major bits of the units starts the microprogram control unit 5, the control signals of which (microcommand,

The lexical units starts the microprogram control block 5, the control signals of which (microcommands Y, U,) write the opening bracket from register 1 to the upper digits of the shift registers of memory block 3 and block register 1. Then the microprogram control block 5 generates the control signal (the micro-command Ud), shifting to the left, the contents of the shift registers of the memory block 3, and after that the control signal is produced (the micro-command y,), different

y,) record the lexical units of the shift registers of memory block 3

there will be no operation code with priority lower than the priority

current operation.

ten

five

03586

nitsu (in this case, operation) of

register 1 in the higher bits of the shift registers of memory block 3, shift the register 6 to the left by one bit, shift register 6, block register 1. If the contents of the first bit of the shift register 6 are one, the firmware control unit 5 generates an error signal. operands. An operand is missing, Stop is formed, and the translation process is terminated. If the contents of the first bit of shift register 6 is zero, the decoder 4, which receives the contents of the higher and preceding high bits of the shift registers of memory block 3, generates a logical signal of the priority ratio of the current and preceding operations. If the operation code listed in the upper bits of the shift registers of memory block 3 has a higher priority than the operation code recorded in bits preceding the upper bits, the decoder 4 starts the firmware control block 5, the control whose signal shifts to the left by one bit. The contents of the shift register registers of the memory block 3 are then unlocked by register 1, and the process proceeds to the analysis of the next lexical unit. If the operation code is entered into the higher bits of the shift registers of memory block 3,

thirty

ka 3 of memory is executed until in the preceding most senior ones

dah shift registers block 3 memory

there will be no operation code with priority lower than the priority

current operation.

If the next lexical unit has a closing bracket, the decoder launches microprogram control unit 5, the control signals of which (microcommands beats, y,) shift the contents of the 3 memory shift registers to the right by one bit and block the register 1. shifts of memory block 3. enters the decoder 4. If the contents of the upper bits of the shift registers of memory block 3 have an opening bracket code, the decoder 4 starts the firmware control block 5, the control signal to orogo (microinstruction y.) shifts the contents of shift register unit 3 memory register 1 unblocking occurs and a transition to the next analysis of lexical units, i.e. the closing and first of the opening brackets encountered do not fall into register 8. If the contents of the higher bits of the shift registers of memory block 3 are not the opening bracket code, decoder 4 starts the firmware control block, the control signal of which (micro-command Ud) switches switch 7 to write the contents of the higher bits of the shift register of memory block 3 8, shifts the contents of the shift registers of memory block 3 by one bit to the right. Decoder 4 determines the code value of the high bits of the shift registers of memory block 3. If this value is a null character code, that means there is no opening brace in the original expression, decoder 4 starts microprogram control block 5, the control signal of which (micro-command) generates an error signal. There is no opening brace, forms Stop and the process stops transfer . If the code value of the higher bits of the shift registers of memory block 3 is not a null character code, decoder 4 determines the code value of the higher bits of the shift registers of memory block 3, and the analysis process for the presence in the memory block opens the brackets until an opening bracket was found (which corresponds to the correctness of the original expression), or an empty character code was found (which corresponds to an error).

O

five

If the next lexical unit is the End-of-Stamp symbol, decoder 2 starts block 5, the control signal of which (micro-coder y) locks register 1. Decoder 4 determines the code value of the highest shift bits of the memory block 3. If the code value of the higher bits

the shift registers of memory block 3 is the empty character code; block 5 analyzes the value of the contents of the third bit of shift register 6. If this value is equal to one, then block 5 switches switch 7 to write the contents of register 1 to register 8 (micro-command y). The translation process is normally completed. The device is ready to translate the following expression. If the value of the third digit of the register

0 6 shift is zero, then the register 6 starts the block 5 of the firmware up-. Formation, generates a signal at an error Operand missing,

5 Stop is terminated and the transfer process is terminated. If the code value of the higher bits of the shift registers of memory block 3 is different from the code of the empty character, decoder 4 starts block 5

0 firmware control, which analyzes the value of the output signal of the decoder 4. If in the higher bits of the shift registers of memory block 3 there is a lexical unit

 (the bracket is open), then the firmware control unit 5 generates a signal for an error. There is no closing bracket and stops the operation of the device. If the error is absent, the decoder 4 starts the block 5, the control signal of which

0

(microinstruction u) switches switch 7 to write from the higher bit sizes of the shift registers of memory block 3 to register 5, and the right shift is by one bit of the contents of the shift registers of memory block 3. Then, the decoder 4 determines the code value of the higher bits of the shift register of block 3

0 memory and starts block 5; The process is repeated until an empty character code is detected or the opening bracket code is detected (indicating the presence of f

5 errors in the original expression) in the higher bits of the shift registers of the memory block 3 defined by the decoder 4.

If the next lexical unit is neither an operand, nor one ration, nor an opening bracket, nor a parenthesis, nor an end of expiration symbol, then the decoder 2 starts the microprogram control unit 5, which generates an error signal - 5 rows of the contents of the shift registers

which forms the value of the output signal, which by means of the microprogram control unit 5 is shifted to the left by one pa

The lexical unit does not belong to the alphabetical order of lexical units, register 1 is locked, stop is generated, and the translation process is terminated.

. Example 1. Let the input expression have the form AxB + C / (D-E) J where; used as a lexical unit. End of expression.

3.pam tee block. Thereafter, the register is unlocked.

The next lexical unit B is written to register 1 and decrypted for 0 s as operand. With block 5, switch 7 is connected to record from register 1, and the lexical unit is rewritten from register 1 to register 8, the right shift occurs

The process of translating the original expression 15 for one bit of the contents of register 6 (code 0010 is formed on the register). The transition to the next lexical unit is made,. The next lexical unit 20 is written into register 1 and is determined by decoder 2 as an operation,

register 1 is locked, shifting by one bit to the left of the register 6, i.e. on indicated

Neither the Polish inverse record is as follows. The initial setting of the values of register 6 and memory block 3, t, e, is made to register 6, code 0100 is entered, the bits preceded by the senior bits of shift registers of memory 3 are entered, the value of the empty character code is entered. Register 1 receives the lexical unit A, which is defined as 25, the register forms the code 0100, So with the decoder 2 as an operand, and using the firmware control unit 5, the input of the switch 7 is connected to the recording of the lexical unit A from register 1 to register 8, as well as a shift to the right by one bit of the contents of register 6 (code 0010 is formed on the register), Microprogram control unit 5 analyzes the value of the fourth bit of register 6, since it is zero, the transition to the next lexical unit is made.

as the value of the first digit of the register 6, the shift is zero, the decoder forms the value X | g O,

Out of register 1 code + record

30 in the higher bits of the shift registers of the memory block 3. The value of the code +, entered in the higher bits of the shift register registers of the memory block 3, and the value of the code x, included in the preceding

The ij leading bits of the shift registers of memory block 3 are fed to a decoder 4, which forms the output signal values x O, since the priority of the previous operation is pain

Register 1 receives the next lexical unit x, which is fixed by decoder 2 as an operation sign. A register 1 is locked, and from register 1, the code x is written to the upper bits of the shift registers of memory block 3. The left shift of the contents of register 6, i.e. code 0100 is formed on this register. In this case, decoder 4 generates the value of no error, since the value of the first bit of register 6 is zero. The code value x, entered in the upper bits of the shift registers of memory block 3, and the code value of the empty character, which is in the preceding most significant bits of the shift registers of memory block 3, go to the decoder 4,

range of shift register contents

which generates the value of the output signal, which by means of the microprogram control block 5 is shifted to the left by one 3.pami unlock. Thereafter, register 1 is unlocked.

The next lexical unit B is written to register 1 and decrypted as an operand. With block 5, switch 7 is connected to a record from register 1, and the lexical unit is rewritten from register 1 to register 8, it shifts to the right

for one bit of the contents of register 6 (code 0010 is formed on the register). The transition to the next lexical unit is made,. The next lexical unit + 20 is written to register 1 and is determined by decoder 2 as an operation,

register 1 is locked, a shift to the left of the contents of register 6 is effected, i.e. on indicated

25; the register forms the code 0100, So

The registrar generates code 0100,

as the value of the first digit register-. ra 6 shift is zero, the decoder 4 forms the value of X | g O

From register 1, code + is recorded

in the higher bits of the shift registers of the memory block 3. The code value +, entered into the higher bits of the shift registers of memory block 3, and the code value x, recorded in the preceding high bits of the shift registers of memory block 3, are sent to the decoder 4, which forms the output value x O, since the priority of the previous operation is greater

than follow. Using block 5, switch 7 switches to writing from the preceding most significant bits of the shift registers of memory block 3 and records the contents of these

bits in register 8 (in this case, the lexical unit x). Then, the shift of the shift register registers of memory block 3 is shifted by one bit to the right and the shift register registers of memory block 3 of the lexical unit + from the register 1 are written to the upper bits. The values of the most significant and previous bits of the memory shift of memory block 3 are received on

the decoder 4, which generates the output signal x, 1, since the priority of operation +, whose code is stored in the higher bits, is greater than the priority of the empty symbol stored in

eleven

preceding the high-order bits of the memory block 3 registers. Using block 5, left shift the contents of the registers

On register 1 is taken next

lexical unit -, which is defined by decoder 2 as an operation. A lock of the memory block 3 of memory is made. After this re za 1. The code is from register 1 of the http / -iii record

Master 1 is unlocked.

The next lexical unit. C is written to register 1, determined by decoder 2 as an operand, and

is in the higher bits of the registers, the shift of the memory block 3. Shifting to the left is carried out; one bit of the contents of register 6 (on the register by the help of block 5 the code 0100 is switched). In this case, the decryption of the input of switch 7 to write operand C to register 8, as well as a shift to the right by one bit of the contents of register 6 (on register forms 4, it generates a missing signal, and decoder 2, to which the values of higher bits (code) and preceding elders

c code 0010). Since the value of four bits (code C) of the shift registers of the register bit 6 is zero, memory block 3, forms output block 5, the signal x, 1, which the device uses to analyze the next lexical unit, controls the operation .

The next lexical unit / 20 shift of the memory block 3. Thereafter, it is determined by the decoder; 2 as opera-register 1 is unlocked, qi. A register lock is in progress. From register 1 using block 5 / write to the higher bit of block 5, left shift by one bit of the contents of the registers

The next lexical unit, E, is accepted into register 1. It is an operand. On register 6, code 0010 is formed, and code E is written to register 8.

The following lexical unit is accepted for register 1). Decoder 2, it is defined as the bracket

d the shift registers of memory block 3. A shift to the left by one bit of the contents of register 6 is effected (code 0100 is formed on the register). In this case, the decoder 4 generates a signal.

make mistakes. The code value is /, it closes. With the help of the block 5 of the registers carried in the higher bits, the shift of the memory block 3 is shifted by one bit, and the code value + stored earlier and located in the previous bits of the memory shift register 3, the output signal x ,, О,. as they blunt on the decoder 4, which for the oldest bits of the shift registers mire the value of the output signal X, 1, which by means of block 5 is shifted left by one bit of the contents of the shift registers of the block 40.a 5 switch

switch

right shift register contents

memory block 3 and re-locked. gistr 1. The decoder forms

unit 3 of memory is the code of the lexical unit - (i.e., a code other than the opening bracket). Via

3 memory, after which register 1 is unlocked.

The next logical unit C is written into register 1 and is determined by decoder 2 as a bracket from -, covering. By means of block 5, register 1 is disabled, and the value of code C is copied from register 1 to higher bits of the shift registers of memory block 3. After that, the left shift of the contents of the shift registers of memory block 3 is carried out, register 1 is unlocked.

Another lexical unit is D. is accepted into register 1. It is an operand. On register 6, code 0010 is formed, and code D is written to register 8.

7 to write from the higher shift bits of memory block 3, and the code of the lexical unit g is rewritten into register 8. Then

45 right shift for one bit of the contents of the shift registers of memory block 3. The decoder 4 generates the value of the output signal x O, since the value of the high-order bits

5Q shift of block 3 of the memory is not equal to the code value Empty symbol, which means that the block 3 of the memory contains operation codes and parentheses, i.e. the need for further translation in order to find out, J2, the surrounding bracket in memory block 3. The signal from the output of the decoder 4 starts the microprogram control unit 5, which analyzes the value of the output signal and, since

lo1290358 .12

On register 1 is taken next

lexical unit -, which is defined by decoder 2 as an operation. Lock is done

is in the higher bits of the registers, the shift of the memory block 3. Shifting to the left, one bit of the contents of register 6 (on the register of frames (code C) of the shift registers of memory block 3), produces an output signal x, 1, which

block 5, the left shift of the contents of the registers

shift block 3 memory. Thereafter, register 1 is unlocked,

The next lexical unit, E, is accepted into register 1. It is an operand. On register 6, code 0010 is formed, and code E is written to register 8.

The following lexical unit is accepted for register 1). Decoder 2 defines it as a closing bracket. Using block 5, a shift is performed by one bit ™ of the output signal x ,, О,. As the oldest bits of the shift registers. A 5 are switched

right shift register contents

memory block 3 and re-locked. gistr 1. The decoder forms

ka closing. By means of block 5, the shift by one bit ™ of the output signal x ,, О, is performed. As the oldest bits of the shift registers а 5 switch

unit 3 of memory is the code of the lexical unit - (i.e., a code other than the opening bracket). Via

30 ka closing. By means of block 5, a shift by one bit 35 ™ of the output signal x ,, О, is carried out. As the oldest bits of shift registers 40.a 5 are switched

switch

7 to write from the higher shift bits of memory block 3, and the code of the lexical unit g is rewritten into register 8. Then

45 right shift for one bit of the contents of the shift registers of memory block 3 The decoder 4 generates the value of the output signal x O, since the values of the high-order bits

5Q shift of block 3 of the memory is not equal to the code value Empty symbol, which means that the block 3 of the memory contains operation codes and parentheses, i.e. the need for further translation in order to find out, J2, the surrounding bracket in memory block 3. The signal from the output of the decoder 4 starts the microprogram control unit 5, which analyzes the value of the output signal and, since

131290358

- 1 (in the higher bits of the shift registers of the memory block 3 is the code of the opening bracket), block 5 allows the shift of the memory to the right by one bit of the contents of the shift registers. In this case, the code value of the opening bracket, which was before the shift in the higher bits of the shift registers of memory block 3, is lost after the shift and is not included in register 8. Unlocked register 1.

ten

neither in

more

not a single

Another lexical unit; is written to register 1 and is decoded as an end-of-expression code, dec 5 encoder 2 starts block 5, which blocks register 1, decoder 4 generates the output signal x "O, since the value of the higher times of the input level and the error detection conclude in follow up. The register 1 receives a lexical unit A, which is an operand and is rewritten into register 8. The next lexical unit + goes to the register and is decrypted as an operation and recorded into the upper bits of the shift register of memory block 3, after which the block masters are shifted 3 memories one time to the left, since the value of the output

The series of shift registers of block 3 of memory 20 of signal x of decoder 4 is 1, not equal to the code of the nycToiro character, but equal to the code of operation /, and the value of the output signal Xs O, since the value of the higher bits of the shift registers of memory 3 is not equal to the opening bracket code, and starts block 5, which switches switch 7 to write from the higher bits of the shift registers of memory block 3 (lexical unit / is rewritten to register 8), and then allows the right shift of one bit of the contents of the shift registers of block 3 memory and older bits istra shift register 1 blo Razblokiruets.

Register 1 is a lexical unit B, which is an operand and is copied to register 8,

The next lexical unit enters register 1, the decryption as a closing bracket. It locks register 1, and the right shift is performed by one bit of content from the shift pan of the memory block 3. The deractor 4 generates the output signal Xj О, since in the higher bits of the shift registers of memory block 3 there is an opening bracket code

3 memory gets a lexical unit of 35 (there is a code of lexical unit +, since the decoder has 4 formulas +) and starts block 5, which draws the values of the output signals x O, Xj O, in a similar way unit + census in

allows writing code + of the older ones

the bit shift of the memory block 3 through the switch 7 into the register 8, and then enables the right shift by one bit of the content of the shift registers of the memory block 3. In the higher bits of the shift registers of memory block 3, an empty character code is generated. Decoder 4 form register 8, and after the shift in seniors. The 40 bits of the shift register of the memory block are generated, the empty character code is generated, in this case the decoder 4 forms the output signal value x 1 and

starts block 5, which analyzes the 45 output signal x G, since the value of the third bit of register 6, the value of the higher bits of the registers

shift of memory block 3 is equal to the code of the empty symbol and starts block 5, which generates an error signal Othm shift of memory block 3 through switch 7 to register 8, and then enables right shift for one bit of content of shift registers of memory block 3. In the higher bits of the shift registers of memory block 3, an empty character code is generated. Decoder 4 forma, since the value of the latter is equal to one (no error), block 5 permits switching of switch 7

to write a lexical unit; of the 50, the opening bracket and the form registers 1) and 1 in register 8, the device has finished translating the expression and is ready to receive the next expression.

The device does not stop working.

Example 3. Let the input expression: has the form AB +; i.e. contains an error - in addition, the operandServes in a way, to register 1 post 55 with a missing sign of the operation between them.

the expression A x B + C / (D - E); and through register 8 to the output of the device, the expression came in the form AB x CDE- / +

The resulting order of the error detection process is as follows. First lexical

Neither does 1 match the Polish inverse record of the input expression.

Example 2 Let the input expression be A + B /; i.e. contains an error - the absence of a declining bracket.

The process of translating the input expression and detecting an error is to follow. Register 1 receives a lexical unit A, which is an operand and is rewritten into register 8. The next lexical unit + goes to register 1, is decrypted as an operation and is written to the upper bits of the shift registers of memory block 3, after which the register contents are shifted memory block 3 one bit to the left, since the value of the output

the signal x of the decoder 4 is 1,

Unlocked register 1.

Register 1 receives a lexical unit B, which is an operand and is copied to register 8,

The next lexical unit is supplied to register 1, interpreted as a closing bracket. Register 1 is locked, and right shift is performed by one bit of the content shift register of memory block 3. The decoder 4 generates the output signal Xj O, since in the higher bits of the shift registers of memory block 3 there is no opening bracket code

(there is a lexical unit code +) and starts block 5, which

allows writing code + of the older ones

(there is a lexical unit code +) and starts block 5, which

It outputs the output signal x G, since the value of the high bits of the registers

the bit shift of the memory block 3 through the switch 7 into the register 8, and then enables the right shift by one bit of the content of the shift registers of the memory block 3. In the higher bits of the shift registers of memory block 3, an empty character code is generated. The decoder 4 forms the error detection process as follows. The first lexical unit A is supplied to register 1. It is decrypted as an operand. The decoder 2 starts block 5, which records the lexical unit. And register 1 to register 8 through the switch 7 and allows the shift to the right by one bit of the contents of register 6 where the code 0010 is formed after the shift (the initial setting was code 0100). Block 5 analyzes the value of the high bit of register 6 and, since this value is zero, proceeds to the next lexical unit.

The next lexical unit B arrives at register 1. It is an operand, with the help of block 5 B it is written to register 8, it is shifted to the right by one bit of the contents of register 6, where code 0001 is formed. Block 5 of the firmware controls yes register 6 and, since it is equal to one, gives the signal y.

errors The number of operands exceeds the number of operations by more than one.

Omitted operation

blocks the right shift for once at once the row of the contents of the shift registers of memory block 3 (the code value (is lost), and the transition to the next lexical unit of the original expression is made.

Another lexical unit;

gyrist 1 and forms a shutdown

devices.

Example 4. Let the input expression-30 be interpreted as the end of an expression.

life has the form A + XB, i.e. contains Decoder 2 starts block 5, which blocks register 1. Since in the higher bits of the shift registers

error - missing operand.

The translation and error detection process is as follows. The perblock 3 of memory is the lexical code. The lexical unit A is a .one- 35 unit ((the second one is from the brackets of the rand. It is rewritten, into register 8, the register 6 forms the code 0010.

The next lexical unit + is an operation. She is recorded in

was lost because the closing bracket was encountered, and the first of the opening brackets is present in memory block 3), decoder 4 generates the value of the output signal Xg О and starts block 5, which analyzes the value of the output signal generated by the decoder 4, as well as x 1, block 5 generates a signal y

block 3 of memory, on register 6 a code 0100 is formed. The next lexical unit x is an operation. She is

lost, since the closing bracket was encountered, and the first of the opening brackets is present in memory block 3), decoder 4 generates the value of the output signal Xg О and starts block 5, which analyzes the value of the output signal generated by the decoder 4, as well. as x 1, block 5 generates a signal

written in block 3 pa.mti, register 1 is locked, and after shifting left by one bit the contents of the register 45 errors. There is no closing 6 on it the code 1000 is formed. brace and forms a stop of operation. Block 5 analyzes the value of the first

devices.

bit register register 6 and, since it is equal to.

but one, signal y, errors. The missing operand will detect the Number of operations more than the number of the operand 50 after correcting the error associated with the absence of a closing bracket when re-translating the steps. Missing operand. and forms a shutdown of the device.

Example 5. Let the original expression be ((A +);, i.e. 55 skipped brace and operand. Lexical units (, (entered into the shift registers of the block 3 units - M

Lexical unit A is rewritten to register 8. Lexical unit + is written to the shift registers of memory block 3, shifted by one bit to the right of the contents of the shift registers of memory block 3 The regular lexical unit is decrypted as a closing bracket. With the help of block 5, register 1 is locked, and the contents of shift registers of memory block 3 are shifted to the right by one, resulting in a higher bits of memory shift registers of memory block 3, a lexical unit + is created, which is written to register 8, and the shift to the right of the contents of the shift registers of memory block 3 is carried out, since in the higher bits of the shift registers of memory block 3 a lexical code is formed

units (,

and since x 1, wasp

there is a right shift for one bit of the contents of the shift registers of memory block 3 (the code value (is lost) and the transition to the next lexical unit of the original expression is made.

Another lexical unit;

decoded as the end of an expression.

unit 3 of memory is the code of the lexical unit ((second from the brackets

was lost because the closing bracket was encountered, and the first of the opening brackets is present in memory block 3), decoder 4 generates the value of the output signal Xg О and starts block 5, which analyzes the value of the output signal generated by the decoder 4, as well as x 1, block 5 generates a signal y

errors There is no closing bracket and forms a shutdown

Otsu brackets and pho errors

devices.

Claims (2)

1. A device for converting expressions into a Polish inverse record containing a decoder, the first register. the information input of which is the information input of the device, and the output is connected to the first information input of the switch, to the information input of the memory unit and to the input of the decoder of lexical units, the output of which is connected to the input of signs of lexical units of the microprogram control unit, the first output of microcommands of which is connected to the input for gtsi of the first register, the second output of micro-commands is connected to the first control input of the switch, the third output of micro-commands is connected to the recording input of the memory block, the second one A source whose output is an information output of a device, the start input of a microprogram control unit is a start input of a device, characterized in that, in order to increase speed and reliability of operation by ensuring control of the pair of opening and closing brackets, the characters of the input expression are included in the set of lexical units , the balance of operators and operations, ensuring the classification of errors, a reverse shift register is entered into it, with the information output and the output of the higher bit of the block memory connected respectively to the second and third informational inputs of the switch and the inputs of the decoder output commutators ,, pa connected to the input of the second register the output of the decoder is connected to the input of signs of prioritization of the microprogram control unit, the outputs of the micro-commands of which, starting with the fourth, are connected respectively with the second and third control inputs of the switch, with the inputs of the left-shift and right-shift of the memory block, with the left-shift and right-shift inputs reverse shift register and with the installation inputs of the memory unit and the reverse shift register, the bit outputs of which are connected to the input of the signs of the error of the microprogram control block, the sig als errors which are respectively output device error signals. 2. The device according to claim 1, characterized in that the memory block contains reversible shift registers, left shift, right shift, recording entries and setup inputs which are respectively left shift, right shift, recording and setup input block inputs, higher inputs shift register bits are connected with the information input of the block, the outputs of the high bits of the shift registers and the outputs of the bits preceding the high bits are respectively the output of the high bit and the information Fig2 / 7ycff Xfxf. 4 o Xw U1 Ua a, g Ua Ua J4 15 GB 13 12 H m ± JO // Xs fpus: (A g / yf4) ipueo Random polygons pr-tie, Uzhgorod, figb VNIIPI Order 7905/49 Circulation 673