SU1164890A1 - Device for converting codes - Google Patents

Abstract

CONVERTING DEVICE .CODES containing connected sequentially pulse generator, the first element AND, the pulse counter in the converted code and the first comparison element, the second comparison element, the pulse counter in other codes, the output, the register and the boot block, whose information input is connected to the control input of the device, the first output is connected to the first input of the second comparison element, and the second output is connected to the information output. the input of the pulse counter in other codes, the output of which is connected to the second input of the second comparison element and the information input of the output register, the output of which is the output of the device, so that, in order to expand the functional capabilities and increase noise immunity, it includes an address counter, a latch trigger, an element, a delay, an OR element, a second and an I-elements, three NOT elements and an input register, whose information input is connected to the device input, the output is connected to another the input of the first comparison element, the output of which is connected to the first input of the OR element and through the first element NOT to the second input of the first element AND and the input of the delay element whose output is connected to the plug-in inputs of the pulse counter in the code being converted and the pulse counter in other codes and through the second element is NOT to the control input of the input (Logo register, the output of the second element of the comparison is connected to the input of the address counter, the second input of the IL element and through the third element NOT to the first input of the second element I, the second the input of which is connected to the output of the delay element, and the output is connected to the input latching trigger trigger latch, whose output is connected to 4; with the first input of the third element, OS, the second input of which is connected to the tax input of the latch trigger and connected to the output of the first element AND, and the output to the counting input of the pulse counter in other codes, the output of the address counter is connected to the address input of the storage unit, output element OR is connected to the control input of the output register.

Description

The invention relates to automation and computing. It can be used in the construction of information processing devices in computing devices.

A device for encoding signals is known, which contains transmission control elements and command control elements, registers and decoders, the outputs of which are connected to the first inputs of indicators and output blocks, as well as AND, OR, control block, clock generation unit and switch, the inputs of which are connected to the outputs of the controls of the address, and the codes to the second inputs of the indicators and to the inputs of controls of the command CJ

However, this device is characterized by narrow functionality, since it does not provide the output of information in different codes and the possibility of changing the code during the conversion,

The closest to the present invention is a code conversion device comprising a pulse generator first connected in series AND, a pulse counter in the code to be converted and a first comparison element, a second comparison element, a pulse counter in other codes, an output register and a storage unit whose information input is connected to the control input of the device, the first output is connected to the first input of the second comparison element, the second output - to the information input of a pulse counter in other codes, the output of which is It is connected to the second input of the second comparison element and the information input of the output register, the output of which is the output of the device, as well as two monostable generators connected in series, a decoder and. Digital Indication RoR C2J. ,

However, this device does not allow to obtain a time-varying programmable code at the output of the device, which reduces the functionality and also is characterized by insufficient noise immunity due to the need for a long

convertible code at the input of the device.

The purpose of the invention is to enhance the functionality and increase the noise immunity.

The goal is achieved by the fact that, in a code conversion device, containing its first pulse element AND connected in series, the pulse counter in the code to be converted and the first comparison element, the second comparison element, the pulse counter in other codes, the output register and the storage unit, the information input of which is connected to the control input of the device, the first output is connected to the first input of the second comparison element, and the second output is connected to the information input of the pulse counter in other codes, the output cat The op is connected to the second input of the second comparison element and the information input of the output register, the output of which is the output of devices, the address counter, trigger, delay, OR, second and third AND elements, three NOT elements and the input register, whose information input is connected to the device input , the output is connected to another input of the first comparison element, the output of which is connected to the first input of the OR element and through the first element NOT to the second input of the first AND element and the input of the delay element, code to that is connected to the zero inputs of the pulse counter in the converted code and the pulse counter in other codes and through the second element NOT to the control input of the input register, the output of the second comparison element is connected to the input of the address counter, the second input of the OR element and through the third element NOT - to the first input of the second element And, the second input of which is connected to the output of the delay element, and the output is connected to the embedment of the trigger latch, the output of which is connected to the first input of the third element And, the second input of which union of a clock input triggerazaschelki and connected to the output of the first AND gate, and an output - to the count input of the pulse counter in the other codes, the address counter output coupled to the address input of the memory Single plaques, output of OR element connected to the control input of the output pa reg. The drawing shows a block diagram of a code conversion device. The device comprises a pulse generator 1, connected to the first input of the first element 2, whose output is connected to the counting input of the counter of 3 pulses in the code being converted, the output of which is connected to the first input of the first element 4 of the comparison whose second input is connected to the output of input register 5, whose input is the input of the device, and the output of the comparison element 4 is connected through the first element 6 NOT to the second input of the first element 2 AND and to the input of element 7 delay, the output of which is connected to the zero inputs of the counter 3 pulses in the converted code and the counter 8 pulses in another code, as well as through the second element 9 NOT to the control input of the input register 5} the control input of the device is connected to the information input of the memory unit 10, the first output of which is connected to the first input of the second comparison element 11, and the second output to the information input of the pulse counter 8 in other codes, the output of which is connected to the second input of the second comparison element 1 1, the output of which nen to the input address counter 12, whose output is connected to the address input of the memory unit 10; the output of the second comparison element 11 is not connected via the third element 13 to the first input of the second element 14 I, the second input of which is connected to the output of the delay element 7, and the output is connected to the zeroed inlet of the latch 15, the output connected to the first the input of the third element 16 And; the trigger input of the latch 15 is connected to the output of the first element 2 I and the second input of the third element 16 AND whose output is connected to the counting input of the counter 8 pulses in another code whose output is connected to the information input of the output register 17 whose output is output the device, and a control input is connected to the output of the OR element 18, the outputs of which are connected to the outputs of the first 4 and second 11 comparison elements; The code conversion device operates as follows. At the initial moment, registers 5 and 17 and counters 3 and 8 are reset to zero and the output of the comparison element 4 generates a write enable signal that prevents the generator 1 pulses from passing through element 2 AND, as well as passing through element 6 NOT, delay element 7 and element 9 DOES NOT allow writing the code to be converted into the input register 5, which stores the incoming code. At the output of the comparison element 4, the recording resolution signal is removed and the signals from the generator 1 pass through the element 2 And to the counting input of the counter 3, the clock input of the latch trigger 15 and to the input of the element 16 I. On the falling edge of the pulse, the trigger-latch 15 switches and allows the passage of signals from the pulse generator 1 through element 16 to the counting input of counter 8, Counter 3 displays the counted pulses in the code being converted, and counter 8 counts the same pulses according to the program stored in block 10 block. Counter 8 counts the pulses until its state coincides with the code received by the input of the comparison element 11 from the output of the storage unit 10. The signal from the output of the comparison element 11 allows the code from the output of the counter 8 to be written to the output register 17, zeroed trigger latch 15 and switches the address counter 12, which selects the new address in the storage unit 10 with the new counting parameters for the counter 8 and the new code, arriving at the comparison element 11. The next impulse coming from the generator 1 switches the trigger-latch 15 and then the operation cycle repeats until the code at the output of the counter 3 coincides with the code recorded in the input register 5. At the same time, the write enable signal from the output of the comparison element 4 arrives at the element 2 And, prohibiting the caNibiM passage of pulses from the generator I,

and at the same time allows the code from the output of the counter 8 to be written to the output register 17. In addition, this signal, passing through the delay element 7, enters the wrapping inputs of the counters 3 and 8 and the latch trigger 15 and through the element 9 does not enter the input of the input register 5 have permission to write a new code to be converted.

The delay of element 7 is chosen from the condition.

. t ,,.

where T is the period of the pulse generator 1; C is the delay time of element 7;

information recording time

H in the input 5 or in the output 17 registers.

Thus, by introducing an input register, three NOT elements of the two AND elements, a delay element, an OR element, an address counter, and a latch trigger with corresponding connections, the functionality of the code conversion device is extended by providing the output of the code to the device output, changing During the conversion according to a given program, in addition, the device noise immunity increases due to the lack of dependence of its operation on the input signals during the conversion.

Claims (1)

CODE TRANSFORMING DEVICE containing a pulse generator sequentially connected, a first AND element, a pulse counter in the code to be converted, and a first comparison element, a second comparison element, a pulse counter in other codes, an output register and a memory block, the information input of which is connected to the control input devices, the first output is connected to the first input of the second comparison element, and the second output to the information. . the input of the pulse counter in other codes, the output of which is connected to the second input of the second comparison element and the information input of the output register, the output of which is the output of the device, characterized in that, in order to expand the functionality and increase noise immunity, an address counter is introduced into it, the trigger latch, element, delays, OR element, second and ^ third AND elements, three elements NOT and an input register, the information * input of which is connected to the device input, the output is connected to another input of the first comparison element, the output of which is connected to the first input of the OR element and through the first element NOT to the second input of the first AND element and the input of the delay element., the output of which is connected to the zeroing inputs of the pulse counter in the converted code and the pulse counter in other codes and through the second 'NOT - to the control input of the input register, the output of the second comparison element is connected to the input of the address counter, the second input of the OR element and through the third element is NOT - to the first input of the second AND element, the second input of which is connected to the output of the delay element, and the output is connected to the zeroing input of the trigger-latch, the output of which is connected to the first input of the third element And, the second input of which is connected to the clock input of the trigger-latch and connected to the output of the first element And, and the output to the counting input of the pulse counter in other codes, the output of the address counter is connected to the address input of the storage unit, the output of the OR element is connected to the control input of the output register. '' SU <·, 1164890 I 164890