SU1765892A1 - Recirculation code-to-number converter of single pulses - Google Patents

Abstract

The invention relates to the field of instrumentation technology and can be used in multi-stage recirculating time converters — a code for digitally measuring the duration of short single pulses. The invention allows to reduce the amount of hardware costs due to the fact that in a device containing three elements AND 1, 4 and 11, two elements OR 2 and 13, a counter 9 pulses, three delay elements 3, 5 and 6, D-flip-flop 12, A pulse shaper 14 is inserted, instead of the additional counter present in the prototype device, a code comparison unit and additional logic elements. 1 sludge.

Description

The invention relates to a measuring and measuring technique and can be used in the construction of multistage recirculation time-code converters (MCI B K) as separate stages (except the latter) for digital measurement of the duration of short (nanosecond) single-pulse signals.

The known converter is time-code 1, which can be used as separate cascades of the MCTVC, containing a time recirculator consisting of OR, AND, delay, delay block, and counting unit, which has And element, first and second delay elements , main and additional counters, code comparison block,

A disadvantage of the known converter lies in the narrow area of its application, since it does not allow to form at its output the duration of the input (convertible) pulse, if it is less durable than the conversion converter resolution,

Known transducer 2, which can also be used as separate cascades (except the last) MRPK. This converter contains a time recirculator formed by the elements OR, AND, delay, delay unit; a counting unit consisting of the And element, the first and second delay elements, the main and additional counters, the code comparison unit; as well as the first, second and third AND schemes, the OR scheme, the first delay element and the D-flip-flop.

However, a disadvantage of the known converter is a large amount of hardware costs.

The purpose of the invention is to reduce the amount of hardware costs.

The goal is achieved by the fact that in a known converter containing the first element I, the first input of which is combined with the input of the first element

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delayed and connected to the first OR element, the second input is combined with the first input of the second delay element and connected to the output of the first delay element, the output of the first AND element is connected to the first input of the first OR element, the second input of which is the input information a bus, a pulse counter, whose setup input to zero is the setup bus to zero; the third element is And, the first input of which is connected to the output of the second delay element, and the second input is with the inverse output of the D-flip-flop, the C-input of which is connected to the output of the second element And, the first input of which is combined with the D-input of the D-flip-flop; the second OR element is entered pulse generator, the input of which is combined with the counting input of the pulse counter and connected to the output of the first element AND, and the output is connected to the first input of the second OR element, the second input of which is connected to the input of setting the pulse counter to zero, and the output is connected to input to the zero setting of the D-flip-flop, the D-input of which is connected to the output of the first OR element, the output of the third AND element being the bus to the Conversion end, and the outputs of the pulse counters provide information to the output bus.

The driver is not known to use a pulse driver, whose input is combined with a counting input of a pulse counter and connected to the output of the first element AND, and the output is connected to the first input of the second OR element, the second input of which is combined with the input of a pulse counter zero, to the input of the D-flip-flop setting to zero, the D-input of which is connected to the output of the first OR element, while the output of the third AND element is a bus to the Conversion end, and the outputs of pulse counters provide an information output bus.

Based on this, the conclusion is drawn: the proposed converter has significant differences.

The figure shows the functional diagram of the recirculation converter time-code of short single pulses.

The Converter contains the first element And 1, the first input of which is connected to the output of the first element OR 2 and with the output of the first delay element 3, the second input - With the output of the first delay element 3, with the first input of the second element And 4, with the input of the second delay element 5, but

output through the third delay element b - with the first input of the first element OR 2, the second input of which is connected to the input information bus 7, the installation bus at zero 8 of which is connected to the control input of the pulse counter 9, and the bus 10 End of conversion with the output of the third element AND 11, the first input of which is connected to the output of the second delay element 5, the second input - to the inverse output of the D-flip-flop 12, the C input of which is connected to the output of the second element 4, D - the input to the second input of the second element 4 and the output of the first element OR 2, R-input - with the output of the second element OR

13, the first input of which is connected to the bus 8 of installation to zero of the converter, the second input to the output of the pulse shaper

14, the input of which is connected to the output of the first element I 1 and to the counting input of the pulse counter 9. Note that here the time recirculator is formed by the elements AND 1, OR 2, delays 3 and 6.

The Converter operates as follows.

Before the conversion to the zero signal starts, the pulse counter 9 is set to zero, and the D flip-flop 12, by its inverse output, is set to a Logical one. A pulse is sent to the input information bus 8 of the converter (to the input of the temporary recirculator), the duration of which is to be converted. When txt t, the third element 11 is closed, since the D-flip-flop 12 is in the inverted output in the position Logical zero and there is no signal on the bus 10 Transmitter output.

At the output of the time recirculator (the output of the first element I 1) a pulse is generated, the length Atxi txr is -t (where t is the conversion resolution of the converter and at the same time the delay time of the first delay element 3 is selected from the required conversion accuracy), which is fixed in the pulse counter 9 and at the same time, it is fed to the input of the third delay element 6 and to the input of the pulse former 14. The inverse output of the D-flip-flop 12 is in this state Logical zero, since its C- and D-inputs simultaneously contain accordingly, the signal t.XT m. The pulse shaper 14 performs, firstly, the formation of a standard amplitude pulse from the back edge of an Atxi pulse and a duration of 1f tes (where t6a is the delay time of the third delay element 6), and secondly, from the back edge

the pulse generates a pulse of standard amplitude and the duration of the tfi (tfi values are selected based on the D-flip-flop time of 12 noR input, as 1fi -i-tDR, tDR is the D-flip-flop delay time 12 on the R input) it is necessary to fulfill the condition (1f + gfi) t6a. Pulse tfi through the second element OR 13 sets the logic unit D-flip-flop 12 to the inverse output after the delay in the third delay element 6 for the time Tbz txmax (txmax - MEXIMmaximal duration of the converted pulses) pulse Atxi, at the output of the time recirculator at Atxi t is generated by a pulse of length Atx2 Atxl - r tXT - 2 g, which is recorded in pulse counter 9, and pulse generator 14 sets D-flip-flop 12 to the state of logical unit on the inverse output. The third delay element b, the first delay element 3 and the second delay element 5 must have the minimum possible distortions in the transmission of pulse signals.

This process continues until the condition Atxn t is satisfied, as soon as Atxn t at the output of the temporary recirculator does not generate a signal, therefore, and pulse generator 14 does not generate a control signal at the R input and D-flip-flop 12, therefore, D-flip-flop 12 the inverse output remains in the state of a logical unit and a pulse of duration Atxn t after a delay in the second delay element 5 for ez time (where gaz (tn4 + toe)), ti / i4, toe is the switching delay time of the second element And 4 and D-trigger 12 at the C-in) passes through the open third lement and 11 to the bus 10 End conversion. At the same time, the number of recirculations (calls through the third delay element 6), recorded in the pulse counter 9, is a digital result of the W conversion of the converter,

When txr f, D-flip-flop 12, in its inverse output, remains in a state of logical unit and a pulse of duration txr t after a delay in the second delay element 5 through the third element 11 passes to the bus 10 End of conversion.

At the same time, since at the output of the temporary recirculator (the output of the first element I 1), a signal is not generated and, therefore, the fixation of the number of recirculation in the pulse counter 9 does not occur.

Thus, on bus 10 The end of the conversion produces a pulse whose duration is shorter than the value of conversion’s discreteness and is determined either by the duration of the input pulse if the latter is less than the value of r or by repeated the duration of the input signal and the value of the conversion discreteness.

Polaga pulse shaper 14 made on the basis of the elements AND-NOT or IL-NOT in capacitors, as in (3), the amount of hardware costs which does not exceed six elements AND-NOT (or OR NOT)

and two capacitors, it can be stated - the claimed converter as compared to the converter - the prototype has a smaller amount of hardware costs, since it is completely absent

blocks 5, 8, 9, 10, available in the prototype converter.

Thus, the purpose of the invention — reducing the amount of hardware costs — has been achieved.

Claims (1)

Claims of the Invention A recirculation converter time-code of single pulses containing the first element AND, the first input of which is combined with the input of the first delay element and connected to the output of the first element OR, the second input combined with the first input of the second element And, the input of the second delay element and is connected to the output of the first delay element, the output of the first element And through the third delay element connected to the first input of the first OR element, the second the input of which is the input information bus, the pulse counter, the installation input of O which is the bus of installation O, the third element I, the first input of which is connected to the output of the second the delay element, and the second input with the inverse output of the D-flip-flop, the C input of which is connected to the output of the second And element, the first input of which is combined with the D input of the D flip-flop, a second OR element, characterized in that; in order to simplify the converter, a pulse shaper is inserted into it, the input of which is combined with the counting input of the pulse counter and connected to the output The first element is AND, and the output is connected to the first input of the second element OR, the second input of which is combined with the installation input in O of the pulse counter, and the output connected to the installation input at O D Trigger, the D input of which is connected to the output of the first OR input, while the output the third element And is the bus End conversions, and the outputs of the pulse counters are the information output bus.