SU1359906A1 - Decade counter for seven-segment indicator - Google Patents

Abstract

The invention relates to digital technology and can be used in digital converters and digital measuring devices of various types, such as digital converters, for converting information of radio and light distance meters into a digital code with a seven-segment indication in units of the measured parameter. The aim of the invention is to improve speed. The device contains 1K-flip-flops 1-4, elements AND 5-12, elements OR 13-17, bus 18 logical unit, bus 19, which receives clock countable pulses, reset bus 20, transfer bus 21, used as input bus for the next decades, exits 22-28 for controlling the illumination of like segments of indicators. Increase in speed is provided by reducing the display time, as well as by reducing the processing time and using the information received. 2 tab., 2 Il. i (L has co with so about O5

Description

The invention relates to digital technology and can be used in digital converters and digital measuring instruments of various types, in particular in digital converters designed to convert information of radio and range finders into a digital code with a seven-segment display output in units of measurable parameter.

The aim of the invention is to increase speed.

Figure 1 shows a block diagram of a decade counter; FIG. 2 shows the time diagrams of its functioning.

The device contains the first 1, second 2, third 3, fourth 4 1K-flip-flops, first 5, second 6., third 7, fourth 8, fifth 9, sixth 10, seventh 11, eighth 12 elements And, first 13, second 14, third 15, fourth 16, fifth 17 elements OR,

bus 18 logical units, clock 25 second input of the fifth element And 9

bus 19, which receives input clock (counted) pulses, reset bus 20, transfer bus 21 used as an input bus for the next decade, exits 22 (a), 23 (d), 24 (b), 25 (c), 26 (f), 27 (q), 28 (e) to control the illumination of like-like a, b, c, d, e, f, q indicator segments.

The 1 input of the first trigger 1 is connected to the bus of the logical unit, the direct output of the first trigger 1 is connected to the first input of the first element 5, the output of which is connected to the first

and the first input of the fourth element OR 16, the second input of which is connected to the inverse output of the fourth trigger 4, and the output is connected to the second 30 input of the sixth element 10, the output of which is connected to the device a-output 22, the device's d-output 23

connected to the direct output of the third trigger 3, the inverse output of which, is connected to the first input of the fourth trigger 4, the device's output 24 is connected to the output of the second element MB, the third input of which is connected to the third input of the fourth element I 8,

the input of the first element OR 13, pr - 40 direct output of the fourth trigger 4,

my output of the second trigger 2 is connected to the first inputs of the second 6 and third 7 elements And, and the inverse output of the second trigger 2 is connected to the first input of the fourth element And 8, 1 the input of the third trigger 3 is connected to the output of the fifth element And 9, the first input which is connected to the inverse output of the fourth trigger 4, the first input of the sixth element And 10 is connected to the forward output of the third trigger 3, the inverse output of which is connected to the second inputs of the second 6, third 7 and fourth 8 elements And, from the input 25 of the device is connected to the code seventh element 11, the first input of which is connected to the device f-output 26, the clock inputs of the flip-flops 1-4 are connected to the input

19, and the inputs of the R-flip-flops 1-4 are connected to the device reset bus 20, the K-input of the first trigger 1 is connected to the 1-input of the first trigger 1, and the bus 18 of the logical unit, and the direct output of the first trigger 1 is connected to the first the input of the second element OR 14, the output of which is connected to the device output 28 and the first input of the eighth element AND 12, the second input of the second element OR 14 is connected to the first input of the sixth element AND 10 and the second input of the first element And 5, the output of which is connected to the first input of the third element OR 15, the second input of which connected to the output of the fourth element And 8, and the output is connected to the device f-output 26, the inverse output of the first trigger -1 is connected to the 1-input of the second trigger 2 and the second input of the seventh IL element, the inverse output of the second trigger 2 is connected to

and the first input of the fourth element OR 16, the second input of which is connected to the inverse output of the fourth trigger 4, and the output is connected to the second input of the sixth element And 10, the output of which is connected to the device a-output 22, the device's d-output 23

connected to the direct output of the third trigger 3, the inverse output of which is connected to the 1st input of the fourth trigger 4, the L output 24 of the device is connected to the output of the second element MB, the third input of which is connected to the third input of the fourth element I 8,

five

To the input of the second trigger 2 and the second input of the eighth element And 12, the output of which is connected to the first input of the fifth element OR 17, the output of the third element And 7 is connected to the second input of the fifth element OR 17, the output of which is connected to the signal transfer bus 21, the third inputs of the third 7 and eighth 12 elements are connected to the input 19 of the device, and the output of the first element OR 13 is connected to the q-output 27 of the device, the K-input of the third trigger 3 is connected to the inverse output of the fourth trigger 4, g the second input of the first element OR 13 connected to the output n of that ementa and 9, the K-input of the fourth flip-flop soe- of the connections with the inverted output of the second flip-flop.

0

3

The device works as follows.

The counting pulses are fed to input 19, and the device switches according to the time diagram (Fig. 2). When the first pulse arrives, the number seven is displayed. When the second read pulse circuit arrives at input 19, the states of the trigger 1 and 2 change to the state is logical zero, and the triggers 3 and 4 remain in the same state, i.e. in the state of logical unit, therefore the states of the inputs and outputs of the device are equal (figure 2 with

p4 1; eleven;

Q,

one;

one; k, 0;

Q 0; Q 0; Q, 1 Qj 1; Q, 0; Q 0, 1h 0; I 0; K, 1 K 1, a on the indicator is lit four and a transfer pulse appears, i.e. Reflection of numbers on the indicator and the appearance of a transfer pulse in the next decade occur when the pulses are received in accordance with Table 1,

Analyzing the operation of the device in the same way, we obtain all the remaining values of the signals (logical functions) at the outputs of the triggers to the decoder (Fig. 2). These values are tabulated.

Table 1 shows the order in which the pulses are received.

Table 2 shows the values of the signals at the outputs of the flip-flops and the decoder.

As can be seen from Table 2, after the arrival of ten pulses, the circuit returned to the initial state and, therefore, upon further arrival of the read pulses, the circuit repeats its states after every ten pulses. P1 transfer pulses, as can be seen from the table, appear when the circuit transitions from the 1st state to the 2nd, from the 2nd to the 3rd, i.e. after the second impulse, the third, etc.

Thus, the speed is improved by reducing the display time, and also by reducing the processing time and using the information obtained by providing information to the fourth AND element, and the output is connected to the f-counter of the counter, the inverse output of the rtepBoro trigger is connected to the 1-input the second trigger and the second input of the seventh element AND, the inverse

indications in units of the measured parameter with a pulse weight equal to seven. The reading is also provided in units of the measured parameter with a pulse weight of seven.

Claims (1)

Invention Formula ten 20 25 thirty 35 40 45 50 A decade counter for seven-segment indicators, containing four 1K-flip-flops, one AND element and a decoder, containing seven AND elements and two OR elements, the decoder outputs are connected to the a, b, c, d, e, f, q outputs counter, 1 input of the first trigger is connected to 15 bus of a logical unit, the direct output of which is connected to the first input of the first element AND, the output of which is connected to the first input of the first element OR, the direct output of the second trigger is connected to the first inputs of the second and third elements And, and the inverse output of the second the trigger is connected to the first input of the fourth element I, the 1 input of the third trigger is connected to the output of the fifth element I, whose first input is connected to the inverse output of the fourth trigger, the first input of the sixth element I is connected to the direct output of the third trigger, the inverse output of which is connected With the second inputs of the second, third and fourth elements I, the c-output of the counter is connected to the output of the seventh element I, the first input of which is connected to the f-output of the counter, the clock inputs of the triggers are connected to the input of the counter, and the inputs RT Iggers are connected to the reset bus of the counter, that is, so that, in order to increase speed, three elements are introduced into it, OR, the K input of the first trigger is connected to the 1 input of the first trigger, and my output of the first trigger is connected to the first input of the second element OR, the output of which is connected to the e-output of the counter and the first input of the eighth element AND, the second input of the second element OR is connected to the first input of the sixth element AND and the second input of the first element AND whose output is connected to the first input of the third element OR second input of which is connected to the output It is not with the f-counter of the counter, the inverse output of the rtepBoro trigger is connected to the 1 input of the second trigger and the second input of the seventh element AND, inverse the output of the second trigger is connected to the K-input of the fourth trigger, the second element of the fifth element AND and the first input of the fourth element OR, the second input of which is connected to the inverse output of the fourth trigger, and the output connected to the second input of the sixth element And whose output is connected to the a-output of the counter, the stroke of the counter is connected to the direct output of the third trigger, the inverse output of which is connected to the 1-input of the fourth trigger, the b-output of the counter is connected to the output of the second element I, the third input of which is connected to the third input of the even ertogo AND gate 1 2 3 7 4 1 Yes Yes 9906 direct output of the fourth trigger, K-input of the second trigger and the second input of the eighth element And, the output of which is connected to the first input  the fifth element OR, the output of the third element AND is connected to the second input, the fifth element OR, whose output is connected to the signal transfer bus, Q third entrances of the third and eighth elements AND are connected to the counter input, and the output of the first element OR is connected to the q-output of the counter, the K-input of the third trigger is connected to the inverse output of the fourth trigger, the second input of the first OR element - to the output of the fifth element I. Table 1 8 9 6 3 Yes Yes Yes Yes Yes Fig2 Editor T. Parfenova Compiled by 0.Skvortsov Tehred I., Popovich Order 6164/56 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A.Zimokosov