SU1368985A1 - Decade counter for semisegment indicator - Google Patents

Description

(21) 4094796 / 24-21

(22) 07/18/86

(46) 01/23/88, Bull. № 3 (72) V.I. Dreams

E53) 621.374 (088.8) 56) USSR Copyright Certificate 117200, cl. H 03 K 23/72, 1983. USSR Copyright Certificate 1330757, cl. H 03 K 23/72, 1985.

(54) DECADE COUNTER FOR SEMIS-MENTAL INDICATORS (57) The invention can be used in computing and measuring devices. The decade counter contains 1K-T1 igger 1-4, elements AND 5-13, elements OR 14-16. The proposed functional connection of elements increases the speed of the counter. Using the proposed decade counter for seven-segment indicators will allow maximum use of the frequency properties of the elements (triggers), since there are no additional logic elements in the I and K-inputs of the 1K-flip-flops. 1 il. with

00 O)

00

00

ate

The invention relates to a pulse technique and can be used in computing and measuring devices.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the proposed decade counter for seven-segment inig cutters, diagrams of its operation, where it is assumed that all 1K-triggers of the device are switched by negative signal on the counting inputs from 1K-triggers, and a schematic drawing of a seven-segment indicator with letter notation

items.

I

The decade counter for seven-segment indicators contains four IK-flip-flops 1-4, first 5, second 6, third 7, fourth 8, fifth 9, sixth 10, seventh 11, eighth 12 and ninth 13 elements And, first 14, second 15 and the third 16 elements OR, the clock bus 17, the reset bus 18, the bus 19 of the logical unit, the output bus 20 of the transfer signal P, the outputs a, b, c, d, e, and g of the device for connecting the corresponding seven-segment indicator. Counting, inputs C of all 1K-flip-flops 1-4 are connected to the clock bus 17, and R-BXOs are connected to the reset bus 18, the output of the second element I 9 forms the output bus 20 of transfer P, 1 is the input of the first IK trigger 1 connected to the bus 19 of the logical unit, the direct output of the first 1K-flip-flop 1 is connected to the first inputs of the fourth 8, seventh 11 and eighth 12 elements And, the inverse output of the first 1K-trIgger 1 is connected to the first inputs of the third 7, fifth 9 and ninth 13 elements And with the K-input of the second 1K-flip-flop 2, the direct output of which is connected to the first input of the first element And 5, with the second The third input of the third element is And 7 and with the I and K inputs of the third 1K flip-flop 3, the inverse output of which is connected to the second inputs of the first 5 and seventh 11 And elements, to the K input of the first 1K flip-flop 1 and from 1 -th K-inputs of the fourth 1K-flip-flop 4, the inverse output of which is connected to the third inputs of the third 7 and seventh 11 elements And and with the 1-input of the second 1K-flip-flop 2, the inverse output of which is connected to the second inputs of the sixth 10 and nine

five

0

five

0

five

0

13 elements I. A direct output of the third 1K-flip-flop 3 is connected to the second input of the fourth element I 8, the output of which forms the output b of the device, the direct output of the fourth IK-flip-flop 4 is connected to the second inputs of the second 6 and the fifth 9 elements I, the output of the first element AND 5 forms the output d of the device and is connected to the first inputs of the second element AND 6 and the first element OR 14 and to the second input of the eighth element AND 1 2, the output of which is connected to the first input of the second element OR 15 and to the third input of the third element OR 16. The output of the second element And 6 forms the output device and the output of the third element And 7 forms the output from the device and is connected to the first input of the third element OR 16, the output of which forms the output f of the device, the output of the fourth element And 8 forms the output b of the device, the output of the sixth element And 10 is connected to the second the input of the first element OR 14, the output of which forms the output of the device. The output of the seventh element And 11 is connected to the second input of the third element OR 16, the output of the ninth element And 13 is connected to the second input of the second element OR 15, the output of which forms the output g of the device.

With this scheme of connecting elements, the logical equations for the I and K inputs of all 1K flip-flops 1-4 and output logic functions at the outputs a, b c, d, e, f and g of the device and the transfer signal on the output transfer bus 20 will be as follows :

one, ,; i, Q

K, Q ,; ,; K, Q

 Q Q,

f cVdQ ,, VQ, Q, Q ,; , VQ, Q P Q, Q ,.

The diagrams denote: Input - input clock (counted) pulses on the clock bus 17; i is the sequence number of the state (clock) of the counter and the sequence number of the clock pulse on the clock bus 17;

Q, is the signal Q, at the direct output Q of the first 1K-flip-flop 1;

QJ-signal QJ at the direct output Q of the second 1K-flip-flop 2;

QJ is the signal Q at the direct output Q of the third 1K flip-flop 3;

0 - signal Q at the direct output Q of the fourth 1K-flip-flop 4;

a - signal a at the output and device;

b is the signal b at the output b of the device;

с - signal с at the output from the device;

d is the signal d at the output d of the device;

e is the signal e at the output of the device e;

f is the signal f at the output f of the device;

g is the signal g at the output g of the device;

P - signal P on the output transfer bus 20.

The operation of the proposed decade counter for seven-segment indicators is completely determined by the logical equations and is carried out in the following order.

On the Reset signal, arriving in the form of a pulse on the reset bus 18, all 1K-triggers 1-4 are set to the initial zero state, after which the output states will be equal (diagrams in the drawing with):

Q, 0; Q, 0; Q, 0; Q 0; , 0;

d Q.T5, 0-1 0; a 0; b 0; with 0; e 0; f 0; one.

As a result, a digit O is formed on the seven-segment indicator for a sequential circuit for switching on the element HTT of the seven-segment indicator with the selected configuration of digits: with a supporting circuit for switching on the elements of the indicator with a luminous element, the output of the device to which this element is connected will be the level of the dog zero therefore, only the element g will be illuminated in the initial device state (when) does not).

Based on the logical equations for the I- and K-inputs of 1K-flip-flops

then the inputs in the initial state (at) will be equal to:

eleven; 1 Q4 1; i, U

R, Q, 1J, 1; R,, 1. If in the previous clock cycle I 0; K oh

then, according to the next clock pulse, the 1K-trigger does not change its state - 15 nor, and if

I 1; K 1,

20

then the 1K trigger switches to the opposite state. If

I 1; K oh

then the 1K-trigger switches to the state of a logical unit, or its unit state is confirmed in the previous cycle. In the case when

I 0; K 1,

thirty

The 1K flip-flop switches to the logical zero state, or its zero state of the previous clock cycle is confirmed.

Based on the specified order of operation of the 1K-trigger and the meaning of the I and K inputs in the previous cycle, we obtain the values of the outputs of the proposed device after the operation of the first clock pulse (diagrams at):

  Q, 0; Q, 1;

45

50

55

P 0; ,,

and on the seven-segment display the number 1 is highlighted.

In this case, the input states will become equal:

1.1; eleven; 1.1;

K, 1; , K, 1; TO..

As a result, in the next clock cycle for the second clock pulse, the states of the inputs will become as follows (diagrams at):

Q, 0; Q, i; Q, l;

P 0; .

A seven-segment display shows the number 2.

The state of the inputs changes as well: 1.1; eleven; eleven; 1.0; K, 0; K ,, 1; K, 1; .

Considering the work of the proposed decade meter for the seven-segment indicators in the same way, we obtain all the values of the outputs and inputs for all i (see diagrams). In this case, the numbers from O to 9 will be sequentially formed on the indicator. The transfer signal P will be equal to

P - 1 only during the ninth time period of 25 pry 1K-flip-flop, direct output of the cathoi 1 9. Therefore, the duration cG of the transfer pulse will be equal to the duration of one period of following the input clock pulses.

The application of the proposed decade counter for seven-segment indicators allows maximum use of the frequency properties of the elements (triggers), since there are no additional logic elements in the I- and K-inputs of the 1K-flip-flops, as in the known device. The number of elements and chains remains the same as in the known device.

Formula

the invention

A decade counter for seven-segment indicators containing four 1K-flip-flops, nine AND elements, three OR-elements, a clock bus, an IK-flusher reset bus to the initial zero state, a logical unit bus, an output bus P of the transfer signal P and outputs a, b c, d, e, f, g counter for connecting the corresponding elements of the seven-segment indicator, in which the counting inputs of all 1K-flip-flops are connected to the clock bus, and

n

368985

R-inputs - with a reset bus, 1-input of the first 1K-flip-flop is connected to the bus of a logical unit, the output of the first

 element And forms the output d of the counter b

and connected to the first inputs of the second

the element And the first element OR, the inverse output of the first 1K-flip-flop is connected to the first input of the third

1Q of the AND element, the output of which forms the output from the counter, the outputs of the second and fourth elements AND of the first element OR form the outputs a, b, e of the counter, respectively, the output n 15 of that element I forms the tire P of the transfer signal, characterized in that In order to increase the speed of the counter, the direct output of the first 1K-flip-flop is connected to the first 2Q inputs of the fourth, sixth, seventh and eighth elements AND, the inverse output of the first 1K-flip-flop is connected to the first inputs of the fifth and ninth elements And and from K- input 0

five

0

five

0

five

It is connected to the first input of the first element I, to the second input of the third element I and C of the I and K inputs of the third 1K flip-flop, the inverse output of which is connected to the second inputs of the first and seventh elements And, to the K input of the first. 1K-flip-flop and with I- and K-inputs of the fourth 1K-flip-flop, the inverse output of which is connected to the third inputs of the third and seventh elements And and with 1-input of the second 1K-flip-flop, the inverse output of which is connected to the second inputs of the sixth and ninth elements And, the direct output of the third 1K-flip-flop is connected to the second input of the fourth element I, the direct output of the fourth 1K-flip-flop is connected to the second inputs of the second and fifth elements And, the output of the third element And is connected to the first input of the third element SH, the output of which go forms the output f of the counter, The output of the sixth element AND is connected to the second input of the first element OR, the output of the seventh element AND is connected to the second input of the third element OR, the output of the eighth element AND is connected to the first input of the second element OR and to the third input of the third element SH, the output of the ninth element And is connected to the second input of the second element SHS, the output of which forms the output g of the counter.

Claims (1)

Claim A decade counter for seven-segment indicators, containing four IK triggers, nine AND elements, three OR elements, a clock bus, a reset bus of the ΙΚ-triggers to the initial zero state, a logical unit bus, the output bus П of the transfer signal P, and the outputs a, b, c , d, e, f, g of the counter for connecting the corresponding elements of the seven-segment indicator, in which the counting inputs of all IK triggers are connected to the clock bus, and R-inputs - with a reset bus, the 1-input of the first IK trigger is connected to the logical unit bus, the output of the first AND element forms the counter output d and is connected to the first inputs of the second AND element and the first OR element, the inverse output of the first IK trigger is connected to the first input of the third 10 element And, the output of which forms the output from the counter, the outputs of the second and fourth elements of And and the first element of OR form the outputs a, b, e of the counter, respectively, the output of the fifth of that element And forms the bus P of the transfer signal, characterized in that in order to increase b In the counter, the direct output of the first IK trigger is connected to the first 2Q inputs of the fourth, sixth, seventh and eighth elements AND, the inverse output of the first IK trigger is connected to the first inputs of the fifth and ninth AND elements and to the K input of the second IK trigger, the direct output of which is connected to the first input of the first element And, with the second input of the third element And and With the I and K inputs of the third IK trigger, the inverse output of which is connected to the second inputs of the first and seventh elements And, with the K input of the first. IK-trigger with I- and K-inputs of the fourth IK-trigger, whose inverse output is connected to $ 3 by the third inputs of the third and seventh elements And and with the 1-input of the second IK-trigger, whose inverse output is connected to the second inputs of the sixth and ninth AND elements, direct output _{40 of the} third IK trigger is connected to the second input of the fourth AND element, direct output of the fourth IK trigger is connected to the second inputs of the second and fifth AND elements, the output of the third ₄ 5 I element is connected to the first input of the third OR element, the output of which go forms the output f of the counter a, the output of the sixth AND element is connected to the second input of the first OR element, the output of the seventh AND element is connected to the second input of the third OR element, the output of the eighth AND element is connected to the first input of the second OR element and to the third input of the third OR element, the output of the ninth AND element Soy55 is connected to the second input of the second OR element, the output of which forms the output g of the counter.