SU1647891A1 - Serial counter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in the construction of counting devices and frequency dividers. The purpose of the invention is the expansion of functional capabilities. The goal is achieved by providing a parallel installation of an arbitrary e (snapshot code and its display). The serial counter consists of counting triggers 1, each of which is executed on elements AND-NOT 2-7 Elements AND-NOT 2 and 3 form an RS-flip-flop, the outputs of which are the information outputs of the counting flip-flop 1. Element AND-II 9 serves to indicate the moments of transient completion in the counter during its operation in the counting mode The l / i-OR-NOT 13 element is used to indicate that the corresponding code of the initial code is written to the counting trigger 1, and the AND-OR element 14 and the AND-15 element - to indicate the process of recording the start code in the meter as a whole, 1 or SL

Description

The invention relates to a pulse technique and can be used in the construction of counting devices and frequency dividers.

The purpose of the invention is the extension of the functionality of a sequential counter by implementing a parallel initial installation of an arbitrary code in the counter and an indication of the process of recording this code.

The drawing shows a diagram of a three-series sequential counter.

A sequential counter consists of counting triggers 1, each of which is performed on the elements S / I-HE 2-7 The element AND NOT 2 and 3 form an RS-trigger. the outputs of which are the information outputs of the counting trigger 1. The output of the element AND-NOT 5 of the counting trigger 1 k is

the counting input of the counting trigger 1k -f 1 The input 8 is the counting input of the counter and is connected to the counting input of the first counting trigger 1. The AND-HE element 9, the output of which is connected to the output 10 of the counter, serves to indicate the ends of the transients in the counter the process of his work in the account mode. The direct and inverse information inputs 11.k, 12.k transmit the value of the k-ro bit of the initial coding element AND-OR-HE 13 to indicate that the corresponding bit of the initial code is written to the counting trigger 1, and the element OR-HE 14 and AND-NE 15, the outputs of which are connected respectively with the outputs 16, 17 of the counter - to indicate the process of recording the initial code in the counter as a whole. The direct and inverse outputs of the RS flip-flop are connected respectively.

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with the first inputs of the third 4 and fourth 5 AND-NES elements and are the direct and inverse information outputs of the counting trigger 1, the RS input of the RS flip-flop is connected to the second inputs of the fourth 5 and fifth 6 AND-NOT elements and the output of the sixth 7th IS element of the same counting trigger, the S input of the Ro-triggerge is connected to the second inputs of the third 4 and sixth 7 AND-NOT elements and to the output of the fifth 6 AND elements of the same counting trigger, the outputs of the third 4 and The fifth 6 I-NOT elements are connected respectively to the third inputs of the fifth 6 and sixth 7 I-elements. E, the first inputs of which in all counting triggers, except the first one, are connected to the output of the fourth 5th AND –NE element of the previous trigger, and in the first counting trigger - to the counting input 8 of the counter, the outputs of the third AND-NOT 4 element, as well as the output of the fourth element The NAND 5 of the last counting trigger is connected to the inputs of the NAND element 9, the output of which is the output 10 of the indication of the end of transients in the counter. The first input of the first group AND element AND-OR-NOT 13 is connected respectively to the additional third and fourth inputs of the third 4 and fifth 6 AND-NOT elements and the direct information input of the counting trigger 1, the first input of the second group AND element AND-OR -NE 13 is connected respectively with additional third and fourth inputs of the sixth 7 and fourth 5 AND-NOT elements and inverse information input of the counting trigger 1, the second inputs of the first and second groups AND AND-OR-HE elements 13 are connected respectively with the inverse and other my output RS-flip-flop, in The moves of the additional elements OR-NOT 14 and the elements AND-NOT 15 are pairwise combined and connected to the outputs of the elements AND-OR-13 of each counting trigger.

The counter has two modes of operation: the recording mode of the initial code and the counting mode. The single execution of the mode will call it a cycle. Each cycle consists of two phases: the working phase and the storage (or quenching) phase. Before the start of the cycle, the counter must be in the storage phase of the information code, which is characterized by setting at the input 8 and the inputs of all the counting triggers 1 logical unit value. In this phase, in all counting triggers, the values at the outputs of elements b and 7 (2 and 3) are opposite, and at the outputs of elements 6 and 3 (7 and 2) are the same, at the outputs of elements 4 and 5, logical units, and the indicator output the end of the transient processes at the count of 9 (indicators of the entry of the initial code) / is in the state O (11).

The working phase of the recording mode of the initial code begins by transferring the signals at the information inputs 11.k, 12.k from the blanking state (1.1) to the working state, in which the direct k-ro bit of the written code is transmitted to the 11.k input, and input 12.k is inverse. In this case, each of the counting triggers one of two processes:

1) if the value of the recorded bit corresponds to the state of the RS flip-flop on elements 2, 3 (the value at input 11 coincides with the value at the output of element 2), then only the output of the AND-OR-NOT 13 element switches to

2) otherwise, the bit triggers on elements b, 7 and 2.3 are sequentially switched, and then the output of element 13 is set to state 1, we note that when switching triggers on elements b, 7 and 2, 3 the outputs of elements 4, 5 they retain their values, since at least one zero is always present at the inputs of these elements.

After the outputs of the elements 13 of all of the counting triggers 1 are set to single values, both the outputs of the elements 14 and 15 will become zero, which is a sign of the end of the first phase.

The second recording phase begins by transferring the information inputs 11.k and 12.k to the quenching state (1.1) and ends with the appearance of single values at both outputs of the elements 14, 15.

Since in the counting mode information inputs 11. 12 are constantly in the quench state (1.1), and the transit state of the RS flip-flop on elements 2,3 and (1.1), in the counting mode, elements 13, 14, 15 do not change their meaning.

Claims (1)

Claims of the invention A sequential counter containing an AND-NOT element and counting triggers, each of which consists of six AND-NOT elements, the first and second AND-NOT elements form an RS flip-flop, the forward and inverse outputs of which are connected respectively to the first inputs of the third and the fourth NAND elements and are the forward and inverse information outputs of the counting trigger; the R input of the RS flip-flop is connected to the second inputs of the fourth and fifth IS-NOT elements and to the output of the sixth NAND element of the same counting trigger, S- RS trigger input with dinene with the second inputs of the third and sixth elements AND-NOT and with the output of the fifth element AND-NOT of the same counting trigger, the outputs of the third and fifth elements AND-NOT are connected respectively with the third inputs of the fifth and sixth elements AND-NOT, the first inputs which in all counting triggers, except the first, are connected to the output of the fourth element AND –NE of the previous trigger, and in the first counting trigger - to the counting input of the counter, the outputs of the third element AND –NE, as well as the output of the fourth element AND –NE last counting trigger connected to the inputs the NAND element whose output is the output of the indication of the end of transient processes in the counter, characterized in that, in order to expand the functionality by implementing a parallel initial installation of an arbitrary code in the counter and indicating the process of recording this code, additional elements are introduced into it OR-NOT, AND-NOT, s is also in each counting trigger element AND-OR-NOT, while the first input of the first group AND elements AND-OR-NOT is connected respectively with the additional third and fourth inputs of the third and fifth elements AND- NOT and direct information input of the counting trigger, the first input of the second group AND element AND-OR-NOT is connected respectively to the additional third and fourth inputs of the sixth and fourth elements AND-NOT and inverse information input of the counting trigger, the second inputs of the first and second groups AND element AND-OR-NOT connect are, respectively, with inverse and direct outputs of the RS-flip-flop, the inputs of the additional elements OR-NOT and AND-NOT are pairwise connected and connected to the outputs of the AND-OR-NOT elements of each counting trigger. n 2