SU1383493A1 - Ring counter - Google Patents

Abstract

The invention relates to a pulse technique and serves to expand the functionality of the device. The ring counter contains ND-triggers I - 1 ... 1 -N, elements AND 2-4, elements OR 5. The introduction of the element OR-NOT 6, the element AND-NOT 7 and the formation of new functional connections ensure the operation of the counter as in code 2 of the N, and in the Johnson counter code. 1 dw., 2 tab.

Description

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The invention relates to a pulse technique and can be used as a ring counter, operating in a code with a constant number of 2 units of N or in a code of a Johnson counter in the construction of measuring and computing devices, as well as in automatic control systems.

The purpose of the invention is to enhance the functionality of a ring counter by enabling operation in both the 2 of N code and the Johnson counter code.

The drawing shows a block diagram of a ring counter.

The ring counter contains ND triggers 1 - 1 - N, the first 2, the second 3, the third 4 AND elements, the ORIT element 5, the OR element NOT 6, and the AND element NO 7.

The direct output of the first D-flip-flop I - 1 is connected to the D-input of the second D-flip-flop 1 - 2, the direct output of each D-flip-flop, starting from the fourth, is connected to the D-input of the next D-flip-flop, the direct outputs of the second 1 -2 and the third 1-3 D-flip-flops are connected to the D-inputs of the third 1-3 and fourth 1-4 D-flip-flops, respectively. The counting input 8 of the ring counter is connected to the clock inputs of the first i D-flip-flops, where i N / 2 + 1 when N is even and i N / 2 is f-1.5 when N is odd, and with the first input of the first element I 2, the output of which is connected to the clock inputs of all the triggers, start with i + l-ro. The inverse output of the first D-flip-flop I - 1 is connected to the first input of the second element AND 3. The direct output N-ro of the D-flip-flop (1 - N) is connected to the second input of the third element And 4. The outputs of the second element And 3 and the third element And 4 are connected respectively to the first and second inputs of the OR element 5, the output of which is connected to the D input of the first D-trigger 1-1. The direct output N-ro of the D-trigger (1 - N) is connected to the second inputs of the second element AND 3 and the element OR-HI: 6, the output of which is connected to the third input of the element OR 5. The forward output of the first D-flip-flop 1 - 1 is connected to the first the third element AND 4 and the second input of the element AND- NOT 7, the output of which is connected to the second input of the first element AND 2. The control input 9 of the ring counter is connected to the first inputs of the element AND-HE 7 and the element OR-NOT 6, as well as with the third inputs of the second 3 and third 4 elements I.

Consider the operation of the ring counter at N 7.

The ring counter operates as follows.

Before operation, the counter is set at 1,100,000.

To ensure the operation of the ring counter in the "2 of N" code, the control input 9 is given a logic level signal

0

g

which unit At the same time, at the output of the element OR NOT 6 there is a zero signal, at the output of the element NE-NE 7 there is an inversion of the signal from the single output of the first D flip-flop 1 - 1.

Finding the D-flip-flop 1 - 1 in the single state prohibits the passage of a pulse arriving at the input 8 through the first element I 2 to the clock inputs of the generous 1 + 1) and the seventh 1 - N D-flip-flop, resulting in a shift by one bit. Only the first five bits, the content of the generous and seventh bits remains unchanged. Moreover, from the state 1000001 the counter goes to the state 0100001, since in the state of the counter 1000001 at the output of the element OR 5 there is a zero logic signal.

When the D-flip-flop 1–1 is in the zero state, the pulse arriving at input 8 through element 2 and directly from input 8 enters the clock inputs of all D-flip-flops, resulting in a cyclic shift of information by one bit. d.

five

0

When D-flip-flops of the first and fifth bits in the unit state are found at the same time, the output of the OR 5 element is a single logical signal, and the output of the AND 2 element has a zero logic signal, as a result of which the counter from state 1000100 goes into state 1100000 which is the initial state of the counter.

In tab. Table 1 lists the state transitions of the ring counter when operating in code "2 of N (logical unit 5 at control input 9). In this mode, the counter status is removed from the direct trigger outputs from the first no.Nth.

The number of states of the counter operating in the code "2 of N is determined by the formula

0 S - and for a seven-bit counter it is equal to 21.

To ensure the operation of the ring counter in the code of Johnson's counter, control input 9 is supplied with a zero signal. In this case, the output of the third and fourth elements will have a zero signal, and the output of the OR-NOT 6 element will invert the signal from the single output of the N-ro flip-flop. Thus, in this mode, the D-input of the first trigger from the output of the element OR 5 will be

Q receive the inverse output signal of the N-ro trigger. In addition, the output of the element And 7 will be a single logical signal, therefore, at the output of the element And 2 there will be a signal arriving at input 8, i.e. The signal arriving at input 8 in this mode is turned on at the C inputs of all D-flip-flops. As a result, the ring counter described above will operate in the Johnson counter mode, and it should be taken into account.

that in this mode, information about the state of the counter should be removed: the low-order bits from the third to Nth trigger outputs, the two high-level bits from the inverse outputs of the first and second triggers.

In tab. Figure 2 shows the state transition data of the ring counter when operating in the code of the Johnson counter (a logical zero at control input 9).

Thus, the counter operation is ensured both in the code "2 of N and in the code of the Johnson counter, which makes it possible to significantly extend its use in various devices.

Claims (1)

Invention Formula Ring counter containing ND-flip-flops, first, second and third elements AND, element OR, ring-counter, the counting input of which is connected to the clock inputs of the first i D-flip-flops, where i N / 2 + with N even and i N / 2 + 1.5 when N is odd, the counting input of the ring counter is also connected to the second input of the first element, the output of which is connected to the clock inputs of all triggers, starting with () -ro, the direct output of the first D-thrngger is connected to the D-input of the second D trigger, direct output of each D-trigger, starting with the fourth, connected to the D-input of the next D-flip-flop, the inverse output of the first D-flip-flop is connected to the first input of the second And element, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the third And element, the first input of which is connected to direct output of the first D-flip-flop, direct outputs N-ro and i-ro of D-flip-flops are connected to the second inputs of the second and 0 third elements AND, the output of the OR element is connected to the D-input of the first D-flip-flop, the direct outputs of the second and the third D-flip-flops - with D-inputs Essentially, the third and fourth D-flip-flops, characterized in that, in order to extend the functionality by enabling operation in both code 2 of N and in the code of Johnson counter, the ring counter contains a control input, an OR-NOT element and an AND element -NON, the control input of the ring counter is connected to the third inputs of the second and third AND elements and to the first inputs of the OR-NOT and AND-NOT elements, the outputs of the OR-NOT and AND-NOT elements are connected respectively to the third input of the OR element and the second input of the first element And, wto The input of the element OR is NOT connected to the direct output of the N-ro D-flip-flop, and the second input of the element IS-NOT is connected to the direct output of the first D-flip-flop. five 0 table 2