SU1298768A1 - Device for generating column chart - Google Patents

Abstract

The invention relates to numerical and measurement techniques and can be used to analyze the distribution of random variables and processes. The aim of the invention is to increase speed. In the device design, each of the N comparison blocks consists of L reference elements. In addition, each comparison element, except for the last one, is connected by informational inputs of the corresponding pair of triggers. Introduced (L-1) additional and (L-1) intermediate registers. The device also contains a register, delay elements, groups (N + 1) of elements AND, counters, a count of the number of formations, N registers of the interval boundaries. The proposed device allows to increase the speed of data processing by using the conveyor principles of processing the incoming numbers when constructing the histogram. 2 Il. 9 clips from 00 o: oo

Description

The invention relates to computing and measurement technology and can be used to analyze the distribution of random variables and processes.

The purpose of the invention is to increase speed.

The invention uses the conveyor principle of information processing, aimed at increasing the rate of data arrival in the construction of the histogram.

FIG. 1 is a block diagram of a device for forming a histogram} in FIG. 2 is a diagram of the element from equal in one of the possible variants of its execution.

The device contains N registers 1–1 of the interval boundaries, outputs connected to the inputs of the corresponding N M-bit comparison blocks, each of which contains L comparison elements 2, the first, and second outputs of each element 2. (, N; j 1, B-1) comparisons are connected via the first and second, respectively 4 | Triggers from (L-1) groups to control inputs of subsequent comparison elements, outputs More and Less than each 2-element of the comparison block are connected respectively to the inputs of AND elements 5 and 5-, the group (N + 1) AND elements, the output of each elements And 5, groups are connected to the counting input of the corresponding counter 6, -6 ". the group (N + 1) of the counters, the information input 7 of the device is connected to the inputs of the receiving register 8, whose M / L outputs of the higher bits are connected to

2 -2 n of the comparison of all the elements of m (M is the size of the 7 numbers entering the input), the remaining bits of the register 8 are connected to the inputs of the first of (L-1) intermediate registers 9. - 9. The outputs of each of which are connected to the inputs of the respective additional registers,.,, each register 9. and lOj (jl, L-1) have (Lj) M / L bits, with the M / L outputs of the higher bits of each additional register 10j connected to the inputs of the two comparison elements, and the remaining bits of each register Ur (, L-2) are connected to the inputs of the intermediate register 9

t + i

Clock

the input 11 is connected to the control inputs of the reception of the code of registers 8 and 10, the counting input of the counter 12 of the number of histogram formations and the input of the first delay element 13, the output of which is connected to the control inputs of the reception of the code of registers 9 and the input of the second delay 14 whose output is connected to the control the inputs of all (L-1) trigger groups 3

and 4, counters 6 and inputs (N + 1) elements And 5 groups.

The comparison element (FIG. 2) contains the elements AND-NOT 15, the elements OR-16, the elements OR 17, the elements NOT 18.

The device works as follows.

In the initial state on the registers

1 -1 stored ordered codes

one

borders of the histogram intervals, counters 6 and 12, as well as registers 8-10, are reset. With the arrival of the clock

a pulse at input 11 is used to receive the received M-digit code number at input 7 to register 8 and add one to the contents of the counter. In the time interval determined by the first delay element 13, the M / L of the upper bits of the incoming number is compared with the corresponding register bits 1. This comparison is performed

on the respective first elements 2-2, a comparison of all comparison blocks. If the code of the specified bits of register 8 is greater than the code of the corresponding bits of register 1, then the unit

a signal is generated at the first output of the corresponding reference element, and at its second output is a zero level signal. With the inverse ratio of the codes arriving at the input of the corresponding comparison element, the potentials at its outputs have the opposite level: at the first — zero, at the second — unit. In case of equality of the codes entering the inputs

of the corresponding reference element, zero potentials are formed at its both outputs. The output signal of the element 14 delay potentials from the outputs of the elements

rewritten to the corresponding

triggers 3-3, 4 ,, - 4 groups. A signal from the output of the delay element 13 makes a census (M - (L-1) M / L) of the empty bits of register B on register 9 ,.

With the arrival of the next clock pulse at input 11 to register 8, input 7 records a new (second) number, and the contents of register 9 is rewritten to register 10, one is added to the contents of counter 12. For the period determined by delay element 13, the M / L most significant bits of the second received number are compared with the corresponding register bits 1 on the elements and the M / L bits are compared (with M (L-2) / L-ro by M (L-1) / b) of the first of the incoming numbers stored on register 10, with the corresponding bits of registers 1 on comparison elements 2-2, while at the control inputs of the last inputs: -3; , and4; -

signals from triggers

groups so that each of the elements makes a comparison of the act2 1 P

codes on its inputs only if zero-level potentials are supplied to its control inputs

while on elements 2-2, the M / L most significant bits of the number received last (stored on register 8) are compared with the corresponding bits of registers 1, on each of the elements (, L), the bits are compared with (M (Lk ) / L) -ro in (M (L-k + 1) / L} -H of the k-th of the received numbers (counting the last

fO from the received numbers) with the corresponding bits of registers 1. By the signal from the output of delay element 13, the contents of the bits that did not participate in the comparison of all numbers except for L-ro

15 (all bits of which took part in the comparison), is rewritten from registers 8,10 -10L-J to registers 9, - 9 |. respectively. The output signal of the element 14 delay results

20 comparisons (L-1) of numbers (except L-ro) are fixed from the outputs of the comparison elements 2 on the corresponding 1x triggers of groups 3 and 4 and, moreover, elements of group 5 and 5 are opened (i.e., if the comparison of the highest M / L a differential signal formed at the output of one of the elements AND 5 (g 2, p) corresponds to finding the L-number between the histogram threshold values fixed on registers 1. and if a single signal is fixed at the output of the AND 5 the threshold recorded on the register

The code numbers of the first number with the corresponding bits of the corresponding register 1 did not reveal the largest of them), otherwise the potentials identical to those entering the control inputs are formed at the outputs of the above comparison elements. By the signal from the output of the element 13, the delays of the unmatched bits of the first and second numbers from the registers 8 and 10, respectively, are recorded in registers 9 and 9, respectively. According to the signal from the output of the delay element 14, the comparison results are recorded on the corresponding triggers of groups 3 and 4.

thirty

group, it corresponds to the fact that the L-e number is less than the minimum of 35 1., if a single signal appears at the output of the AND element of the group, then it corresponds to the fact that the L-e number is greater than the highest threshold fixed on register 1 ,.

40 A single signal from the output of the element And 5 of the group is used to increase the content unit of the corresponding counter 6.

Further operation of the device

is repeated according to the described principle so that L numbers 7 that are received at the input are processed simultaneously. The clock pulse supplied to input 11 is used to add one to the contents of counter 12 and record the newly received number to register 8, as well as to rewrite the bits (L-1) of the numbers previously received from the registers that were not processed at the previous clock cycles. ,

respectively.

oh oh

1 and- (

for registers 10 -10j. For the period defined by delay element 13, parts L are compiled with the threshold values.

while on elements 2-2, the M / L most significant bits of the number received last (stored on register 8) are compared with the corresponding bits of registers 1, on each of the elements (, L), the bits are compared with (M (Lk ) / L) -ro in (M (L-k + 1) / L} -H of the k-th of the received numbers (counting the last

O from received numbers) with corresponding bits of registers 1. By a signal from the output of delay element 13, the contents of bits that did not participate in the comparison of all numbers except the L-ro

5 (all bits of which took part in the comparison) is rewritten from registers 8,10 -10L-J to registers 9, - 9 |. respectively. The output signal of the element 14 delay results

0 comparisons (L-1) of numbers (except L-ro) are fixed from the outputs of the comparison elements 2 on the corresponding 1x triggers of the 3rd and 4th groups and, in addition, the elements of the 5th group are opened, a single signal formed at the output of one of the elements And 5 (r 2, p) corresponds to finding the L-ro number between the threshold values of the histogram recorded on registers 1. and if a single signal is fixed at the output of the element And 5. to the threshold recorded on the register

thirty

 the signal formed on the out of the And 5 (g) elements corresponds to the finding of the Isla between the threshold values of the togram fixed on the bits 1. and if a single is fixed at the output of the element. orog recorded

group, then it corresponds that the L-e number is less than the minimum

1. If a single signal appears at the output of an AND group element, this corresponds to the fact that the L-e number is greater than the largest threshold fixed on register 1 ,.

A single signal from the output of the element And 5 of the group increases the content unit of the corresponding counter 6.

With the arrival of the next clock pulse, the described cycle of operation of the device repeats. The contents of the counters 6 corresponds to the number of incoming numbers, found pr1hs within the appropriate limits.

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Claims (1)

Invention Formula | A device for forming a histogram, containing N registers of interval boundaries, a group of N + 1 elements AND, a count of the number of formations, histograms, a group of N + 1 counters, N M-bit comparison blocks, receiving the register whose information input is the information input of the device, the M / L outputs of the upper bits of the receiving register are connected to the first information N inputs of the M-bit comparison blocks, the second information inputs of which are connected respectively to the bit outputs of the N registers of the boundary limits, exits The main register is connected to the first information inputs () of the comparison elements of all the comparison blocks, and the outputs of the remaining bits of each t-ro additional register (, L-2) are connected to the bit inputs (t + 1) -ro of the intermediate register , 11 the information inputs of the first intermediate More and Less each i-ro block fO of the register are connected to the outputs M -M / L of the lower bits of the receiving register, the outputs More and Less Comparisons (, N) are connected respectively to the inputs of i-ro and (i + l) -ro elements AND groups, the outputs of elements AND groups are connected to the counting inputs All L-1 comparison elements are connected to the information inputs of the corresponding corresponding group counters, input 15 group triggering triggers, outputs a histogram number count is a device clock input, characterized in that, in order to increase rapidly, the triggers of each group are connected in pairs, respectively, to the first and second control inputs of subsequent comparison elements, the reception control inputs of the receiving code and the additional registers, as well as the input of the nepBOL o delay element are combined and are the clock input of the device, the output of the first element actions, each of the N M-bit comparison blocks contains L comparison elements, and L-1 trigger groups of 2 N in each group, two delay elements, L-1 additional and L-1 intermediate-25 that delay are entered into the device connected to the input of control registers, the number of bits of each laziness is received by the code of intermediate j-ro (, L-1) of which is equal to the registers directly, and four (LJ) “M / L, while the outputs of each cut are the second delay element - from the intermediate register are connected by the control inputs of the triggers to the inputs of the corresponding additional 30 groups, with the corresponding input register, M / L outputs of the elder elements of the AND group, and the counting bits of each j-ro additional group. The main register is connected to the first information inputs () of the comparison elements of all the comparison blocks, and the outputs of the remaining bits of each t-ro additional register (, L-2) are connected to the bit inputs (t + 1) -ro of the intermediate register 11 Information of all comparison elements L-1 are connected to information inputs of corresponding 20 the triggers of each group are connected in pairs, respectively, to the first and second control inputs of subsequent comparison elements, the reception control inputs of the receiving code and the additional registers, as well as the input of the nepBOL o delay element are combined and are the clock input of the device, the output of the first delay element is connected to the control input for receiving the code of intermediate registers directly, and through the second delay element - with the control inputs of the trigger 30 groups, with the corresponding inputs of the elements AND groups and COUNT kov- group. Compiled by E. Sechin Editor E. Papp Tehred L. Serdiukon. Proofreader O.Lugov Order 891/52 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4