SU1383494A1 - Decade counter for seven-segment indicators - Google Patents

Abstract

The invention relates to the field of pulsed technology. The ten-day counter for seven-segment indicators contains 1K-triggers 1-4, elements AND 5-13, elements SHSh 14-17, clock bus 18, through which input (readable) pulses flow, reset bus 19, bus 20 logical units, transfer bus 21 used to control the next decade. The decade counter has an increased speed by obtaining new output logic functions of the frequency divider, which made it possible to construct a two-stage decoder without increasing the logic elements. 2 ill., 1 tab.

Description

And u

(L

00 CX)

from 4i f

four

tf

/ 7

-

g

The invention relates to a pulse rate, a technician, and can be used in computing and measuring devices.

The aim of the invention is to improve the speed of the device

FIG. 1 shows a decade counter circuit for seven segment and dicators; in fig. 2 is a diagram of the job.

The counter contains the first 1, the second 2L the third 3, the fourth 4 1K-trigger- | 1, the first 5, the second 6. the third 7, the fourth 8, the fifth 9, the sixth 10, the 11th, the eighth 12, and nine The 13 elements are And, the first 14, the second 15, the third 16, the fourth 17 elements OR the t1 tact bus 18 through which the input (read) pulses are received, the wn 19 reset, the bus 20 logical e | cinnamon, the 2G transfer bus, using - to control the next decade, outputs a, b, c, d, e, f, q.

The counting inputs of all the triggers are connected to the clock bus 18 of the Bia device, and the reset inputs are connected to the bus 19 of the device reset, the I and K inputs of the first trigger 1 are connected to. bus logical units, the direct input of the first 1 | riggra 1 is connected to the K-input of the second Fjoro trigger 2, the first inputs of riepBoro 14, the second 15 and the third 16 OR elements. The output of the third element OR is connected to the first input of the first element I 5, the inverse output of the first trigger is connected to the g | first input of the second 6 element I, E | OUT of which is connected to the device outputs, the inverse output of the second trigger is connected to the first inputs Dami the third 7 and fourth 8 jJieHTOB AND elements, the output of the fourth element I is connected to the output d of the device, the second input of the second element OR 1 whose output is connected to the output e of the device, the output of the fourth element AND 8 is connected to the first input of the fifth element AND 9, the output which podkl chen to yield a va ustroyst, a direct output of the third flip-flop 3 is connected to a second input of the fourth AND gate 8. The 1-input of the second flip-flop and a second input of the first AND gate 5 whose output is connected to the output f of the device. Inverse output of the third trigger. Connected to the first input of the sixth element And, the second input of which is connected to

0

five

0

five

0

d 0 5

0

five

Mbw by the output of the fourth trigger, and the output is connected to the output b of the device. The output of the seventh element And is connected to the K-input of the third trigger, the inverse output of the fourth trigger is connected to the first input of the eighth element And, the output of which is connected to the transfer bus, the output of the first element OR 14 is connected to the second input of the third element And, the output of which is connected to output q devices. The first input of the fourth element OR 17 is connected to the inverse output of the first trigger, the second input is connected to the inverse output of the fourth trigger and the second input of the first element OR 14, and the output is connected to the second input of the fifth element AND 9, 1 to the input of the fourth trigger is connected to the right the output of the third trigger, the second input of the second element And 6 is connected to the direct output of the second trigger and the second inputs of the eighth element And and the third element OR 16, and the third input is connected to the direct output of the fourth trigger and the first input of the seventh ementa And, the second input of which is connected to the inverse output of the second flip-flop, one input of the third flip-flop and a first input of a ninth AND gate, connected to the second vhod.kotorogo direct output of the first flip-flop, and an output connected to the K-vhdu fourth flip-flop.

Elements 7-12, 14-17 form a yes-: encoder for sequential switching on (it is possible through the corresponding driver) elements of a seven-segment indicator, 1K-triggers 1-4 with elements 5, 6 and 13 form a frequency divider by 10. Triggers respond to clock changes from TI-1 to TI-0.

Fig 2 shows:

i — order numbers of device states;

TI - clock (input) pulses on the clock bus 18;

P - signal transfer on the bus 21,

a, b, c, d, e, f, q are the signals at the corresponding outputs a, b, c, d, e, f, q of the device.

1 - bus 20 logical units.

The operation of the proposed decade counter for seven-segment indicators is completely determined by the logical equations for the Ij and Kj inputs. In the initial position, all 1K-three1 Hera

1 to 4 by a reset signal, arriving in the form of a pulse on the reset bus 19, are reset (diagrams in FIG. 2 at), while

Q, 0; Q ,, 0-, Q, 0; Q4 0.

Based on the logical equations for the Ij and Kj inputs of the trigger inputs, the inputs will be as follows:

I, 1; Ij Oh, - I, 1; 1 Oi.

K, 1; KJ 0; K, 0-, K 0.

According to the logical equations for the outputs of the decoder, we determine that

and d (Q V Qj O, b Q.Q 0; with Q.QjQ 0-, d Q, Q, 0; e Q. v d 0, f Q, (Q, VQj) 0, q Q (9iV Q) 1 ,.

the O number is illuminated on the seven-segment indicator. Since the 1K-trigger on the input clock pulse when I O and K O does not change its state, with I 1 and K 1 switches to the opposite state, with I 1 and K O - switches to the state of a logical unit, and when 1 connects a logical zero, then by the first clock pulse on bus 18, the first 1 and third 3 1K-flip-flops switch to the state of a logical one, and triggers 2 and 4 do not change their states (diagrams in FIG. 2 with i 1). In this case, the states of the outputs of the triggers 1-4 will become equal to Qi. l; Qi 0, Qs 1, Q4 0. The states of the I and K inputs and

will be equal

I, 1; I ,, 1; I, P I, 1,

K, 1; KJ i; KJ Oi to 1,

a on the outputs of the decoder will be signals a 1, b 0; with 0; d 1, e 1; f 1; q 1 and the number 1 appears on the display,

I

On the second clock pulse

(diagrams in fig. 2 with i 2) the states of the outputs and inputs will become equal

0; Q,

one; Q, 1-. Q4 1;

eleven; eleven; I, 0; I, 1, - to, G,. K, o, k, o, - K. o, a 0, b 0; 5 and the number 2 appears on the seven-segment display.

Analyzing in the same way the work of the proposed decade counter for seven-segment indicators, we obtain all the values of the signals (logic functions) at the outputs of the frequency divider and decoder (diagrams in FIG. 2) for all i, which

20

25

zo . .Q D5

50

five

rye are given in the table.

The proposed decade counter for seven-segment indicators has a transfer speed twice as long as compared with the known and approximately 15% faster response time. The increase in the duration of the transfer output signal is achieved by changing the connections between the outputs and the I and K inputs of the triggers, and the speed by obtaining new output logic functions of the frequency divider, which allow us to construct a two-stage decoder. Obtaining a longer output signal makes it possible to use a less fast and, hence, simpler and cheaper decade counter in the next decade.

Further, upon receipt of clock pulses at the cycle input, it will start from the zero state of the device.

Claims (1)

Invention Formula The decade counter for seven-segment indicators, containing four 1K-flip-flops, nine AND elements, three OR elements and having outputs a, b, c, d, e, f, q for connecting the corresponding elements of a seven-segment indicator, the counting inputs of all the triggers are connected The device has a clock bus, and the R inputs of all triggers are connected to the device reset bus, the I and K inputs of the first trigger are connected to the logical unit bus, the forward output of the first trigger is connected to the K input of the second trigger, and the first inputs of the first, second, and ThirdILE OR, output tr Another element OR is connected to the first input of the first element AND, the inverse output of the first trigger is connected to the first input of the second element AND, the output of which is connected to the output from the device, the inverse of the second frigger is connected to the first inputs of the third and fourth elements AND, pyhod the fourth element And connect (; output d of the device, the second way of the second element OR, the output ijcoToporo is connected to the output e : | device, the output of the fourth element | I is connected to the first input of the ptog: element I, the output of which is connected to: k output of the device, direct output of the warm trigger connected to the second stroke of the fourth element I, 1-in; ohm of the second trigger and the second input jiepBoro of the element And, the output of which is connected to the output f of the device, the third spring of the third trigger |: connects to the first input of the sixth element And, the second input of which is from Dinen with the direct output of the fourth (trigger, and the output is connected to the output b of the device, the output of the seventh ele and is connected to the K-input tr teg flop inverse output chetvertog (flip-flop connected to the first input : 0 About 0000 00 10 0101 II 2 o 1 110 1 O 30 till 1 o 01100 10 0101100 01000 00 01101 11 10010 00 10011 00 connected whose exit lane with second q of the eighth element And, the output is connected to the transfer bus, the first element of the 1SH is connected by the input of the third element And, the output of which is connected to the output of the device, characterized in that, in order to improve speed, a quarter is entered into it element OR. The first input of which is connected to the inverse output of the first trigger, the second input to the inverse output of the fourth trigger and the second input of the first OR element, and the output to the second input of the fifth And, 1, the input of the fourth trigger is connected to the forward output of its trigger, the second input of the second element And is connected to the forward output of the second trigger and the second inputs of the eighth And element and the third OR, and the third input is connected to the forward output of the fourth trigger and the first input of the seventh element And, the second input of which is connected to the inverse output of the second trigger, 1-input of the third trigger and the first input of the ninth element And, the second input of KOToporcf is connected to the direct output of the first trigger, and the output is connected to the K-input of the fourth trigger. 000001О 0011111 0100102 0001103 0011004 1001005 1000006 0011117 0000008 0001009 F1 / g.2