SU601695A1 - Malfunction registration device - Google Patents

Description

the decoder 5, the counter 6, the output register 7, the p-time 8, the element is NOT 9, the pulse generator W and the driver lil.

The inputs 12 of the device are connected with the first bar of the inputs of the register L-ami, /, the second group of inputs of which are connected to the outputs of the group of elements AND 4. The outputs of the register of memory I are connected to the inputs of the first element OR 2 and the second inputs of the elements AND 4. The output of the first element OR 2 is not connected to the first input of the element HE 9 and via ph; p1M1ir01eatel And with the installation input to the zero count: ka 6. The first group of outputs of the counter 6 is connected to the decoder descents 5, the outputs of which are connected with the first input elements NOT 4. The second group of outputs of the counter 6 connect It is not available from the input of the register 7. The outputs of the elements AND 4 through the second element of the ILR 5 are equipped with the inputs of the relay time.

5 and the register input Register 7. The output time-e. 5 is connected to the second input | M of the HE element 9, the output of which is connected to the counting input of Counter 6 via the generator 10 of them.

The device works following i-oh, brazom. In the outgoing state, when there are no fault signals, the impulse generator 10 does not work, because it is potentially energized from the output of the HE element 9.

The input signal to the inputs 12 of the device for the fault signals from the sensors at the outputs of the register memory 1 is set up to have the logical level "1. The signal from the output of the first element OR 2 through the formatter // sets the counter

6IB ' O, and through the element NOT 9 starts a pulse generator 10, the pulses from the output of which are given to the counting input of counter 6.

The signals from the outputs of the decoder 5 oorashi. The state of the elements is 4. And at the combination of signals at their first and second inputs, signals from the corresponding outputs of elements 4 are fed to the second inputs of the memory register / and to the inputs of the second element OR 3. When signals are received to the second inputs of the memory register 1, at its outputs, a state is set corresponding to its logical level "O. If there are us / fault signals on the first inputs on the corresponding outputs of this peTTHiCTipa, the state is set to the level "1. The signal from the output of the element OR 3 3 ai has a relay time of 8 and 8 and through

The HE element 9 prohibits the operation of the generator of pulses 10 and enables the writing of a malfunction code in the register 7. When the time relay 8 returns to its initial state, the generator of emulsions 10 is started, thereby ensuring the interrogation cycle of the E 4 elements. At the end of the interrogation cycle of the And 4 elements the device returns to its original state if the signal at the output of the element OR 2 is absent. In the presence of fault signals at the inputs 12 of the device, a new polling cycle begins.

In this way, the introduction of a memory register into the device improves the reliability of information transfer, since it provides the storage of fault signals.

Claims (2)

1. USSR Author's Certificate No. 265562, G 06 F 5/06, 1968. 2. USSR author's certificate No. 396687, G 06 F 5/06, 1972. YT TG