SU1374051A1 - Device for recording discrete signals - Google Patents

Abstract

The invention is intended for the accumulation and output to digital printing of data on the change in the state of the actuators of the control systems recorded by two-position sensors with reference to the current inputs.

Description

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of time. The purpose of the invention is to increase the number of discrete-shaped binary signals and to increase the information content of the recorded information on changes in the input information. All changes of electrical signals arriving at information inputs 1,2, ..., o., P of quantizer 1 are subject to registration. After recording the next code vector of the interrogated group of circuits in register 2, elements 3-l..o3-k detect a discrepancy of electrical signals. Counter 7 provides alternate

interrogation of these circuits within the group and establishes which of them was incomparable. In memory block 6, the switching of electrical signals is recorded at inputs 1,2, .., with the indication of the sequence number of the input at which the signal level has changed, the nature of this change, and the current time. Formed by block 23 of the time code. In order to output the data recorded in the registers of block 6 of memory, the counter 30 switches its registers to the inputs of the differential printer 27 and reads their contents. 1 tab., 2 Il.

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The invention relates to digital computing technology and is intended to accumulate and print data about a change from one hundred HY of actuators of control systems fixed by two-position sensors, linked to the current time.

The purpose of the invention is to increase the number of recorded signals of discrete shape and increase the information content recorded on the data carrier about the change of input information

Figure 1 shows the functional electrical circuit of the device; FIG. 2 shows a structural quantizer of input signals.

The device contains (Fig. 1) quantizer 1 input signals, register 2, elements 3 (3-l..p3-k) matches 4 keys (4-1 o o.4-e), group of registers 5 (5- 1, .. 5-d), memory block 6, first 7, second 8 and third 9 counters, first AND 10 elements of the first 11. (ll-l - .. ll-k) and second, 12 (12- 1 ... 12-k) groups of E subjects, second 13 and third 14 elements And, element 15 of memory, generator of 16 pulses, switching element 17, switch 18, element IL 19, elements 20 - 22 of delay, code generator 23 time, switching on, for example, the generator 24 pulses and the counter 25 of the current time, the module 26 control furnace Tew and Digit Block 27.

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Module 26 in the simplest version includes a pulse generator 28, a switching element 29 and a counter 30

The quantizer 1 (figure 2) is built, for example, on the elements And 31 (31-1 .. 31-p), which are combined into several groups (31-1.o31-k, 31- (k + l). ., 31-2k, etc.) in accordance with the number of second inputs 0,1, ..., m.

The device works as follows.

All electrical signals entering information inputs 1,2, .., n quantizer 1, for example, from the outputs of two-position sensors (not shown), indicating the current time when these switchings are subject to registration. The device starts up by short-circuiting the switching element 17. This sets the memory element 15 into one state, And 14 opens, and the voltage pulses from the output of the generator 16 begin to flow into the interrogation circuit of the input circuits, built on two ring circuits counters 7 and 8. The polling mode is cyclical. At the beginning of each cycle, both counters are reset to zero, elements AND P-1 .. „11-k, 12-1.о.12-k are closed, and registers 5-1 ... 5- (the information about the presence of electrical signals on At the zero output of counter 8, an electrical signal is generated corresponding to 1, which goes to input O of the quantizer 1 and through switch 18 to the input of key management 4-1, B to the quantizer, this signal opens AND 3i-l elements. .. 31-k of the first group, as a result of which the information signals from its inputs l, 2, o., K are translated into register 2, fic it is connected to it by a voltage pulse arriving at its rewrite input and output O of counter 7, and transmitted to the first inputs of elements 3-1 ... 3-k matches Other inputs of these elements using closed keys 4-1 are connected to the outputs of the register 5-1.

Elements 3-1 ... 3-k compare the electrical signals received on their first and second inputs and, depending on the result obtained, determine the further mode of pulse counting by counter 7.

If the contents of register 2 fully correspond to the register code 5-1 (information on inputs 1,2, „o., K of the device with respect to the previous survey remained unchanged), then the voltage at the outputs of elements 3-1 ... 3 -k is absent and the element And 13 forms an electrical signal that opens the element I (Yu). As a result, after reading the first pulse at the first output by the counter 7, a voltage is excited which through the open element AND 1Q and the element OR 19 enters the counting input of the second counter of the polling circuit and changes its state as follows:

The first unit is recorded in the counter 8, as a result of which an electrical signal is excited at its first output; the latter enters quantizer 1 and involves AND 31- (k-fl) elements in operation. . .31-2. k, preparing for polling the second group of device inputs; at the same time, the signal from the first output of the counter 8 through the switch 18 is transported to the control input of the keys 4-2 and opens them, connecting the outputs of the register 5-2 to the second inputs of the elements 3-1.o 3-k coincidence; after an interval of time equal to the setting of the delay element 20 and sufficient for stable switching of the counter 8, the counter 7 returns to the initial

the state and at its zero output a voltage is formed, over which the code vector of the second group of device inputs is copied to register 2; elements 3-1..3-k again compare the electrical signals received at their inputs and, if they coincide, open elements 13 and 10 to pass a voltage pulse from the first output of the counter 7 to the second input of the RShI element 19 and further to the counter 8 with the aim switching it to the second position. As a result, a third group of device inputs was prepared for the survey (3 k each inclusive) and

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Thus, if the code vector of the input signals remains unchanged for some time, then the counter 7 does not fill up (operates in a pulsating mode) and for each period of the voltage pulses excited by the generator 16 one of the information circuit groups is interrogated.

If after writing to the register 2 oche. If the second code vector of the interrogated group of circuits, for example (2k + l) .., 3k, elements 3-1 ... 3k, detects a mismatch of electrical signals connected to them, the first and second inputs, then elements 13 and 10 remain closed, and counter 7 provides alternate polling of these circuits within the group and determines which one of them has passed the incomparability, namely:

as the counter 7 is filled, the elements of the first and second groups are then alternately opened: signal P-1, 12-1, then 11-2.12-2, and so on;

at the output of the coincidence element, by which the input signals are not matched, a voltage is generated which is transmitted through the open element II of the second group, for example 12-3, to the counter input of the counter 9 and through the delay element 22 to the recording input of the memory block 6;

the contents of counter 9 is incremented by one, and it switches to the information inputs of block 6 its register, in which, at a time interval equal to the setting of delay element 22 and sufficient for passing transients, counter 9 and block 6 write the code generated by counters 7 and 8 and the order number is polled.

th input, and the current time code generated by the shaper 23;

information about the magnitude of the electrical signal that has been established on the polled input at a given time is recorded in a separate cell of this register (1 means the arrival of a high level signal and O means a low one);

this signal is transmitted to input 0/1 of block 6 from the corresponding output of register 2 through an open element And (12-3) of the second group;

when the pulse signal at the output (k + l) of the counter 7 is excited, the switch 18 is set to the position at which all its inputs 0,1, ..., t are connected to the overwriting inputs of the registers 5-1 ... 5- (}, but since only one input (the second) is under voltage at a given time, the contents of register 2 are read into register 5-3;

after removing the signal from the output (k + l), the switch .18 returns to its original state;

upon filling of the counter 7, a signal is excited at its last output (k + 2), under the action of which the counter 8 is switched and after an interval of time corresponding to the setting of the delay element 20, the counter is reset to the initial state

If, as a result of a subsequent survey, the switching of electrical signals to other

Invention Formula

A device for registering discrete signals, containing elements of coincidence, a block of memory with a print control module, a first counter, and a first element AND, differing from the fact that, in order to increase the number of recorded signals

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the inputs of the device, the information about this is processed in the same way and is written into the new registers of block 6, selected by the counter 9,

The polling cycle ends with filling the counter 8 and re-blocking it with the voltage pulse that is excited at its last output.

Thus, in memory of block 6, all switchings of electrical signals at inputs 1, ... n of the device are fixed, each time the sequence number of the input at which the signal level changes, the nature of this change (in the form of logical zero and one or characters ON-OFF) and the current time, formed by block 23, with an accuracy of hundredths or a thousand fractions of a second.

For data, the data recorded in the registers of block 6 closes the switching element 29 of module 26, as a result of which its counter 30 begins to fill with voltage pulses produced by generator 28, Counter 30 switches the registers of block 6 to the inputs of the digital printer 27 in the sequence in which they recorded the information, and reads them, the contents, fixing on the carrier the specified information about the switching of input signals, for example, in the form of the following table:

catching and increasing the information content recorded on the data carrier; the input signal quantizer connected in series and the register whose outputs are connected to the first inputs of the coincidence elements, the group of keys whose outputs of the same name are combined at the second inputs are entered into it

matching elements, respectively, a group of registers, outputs connected to the corresponding inputs of a group of keys, second and third counters, a switch, the first group of outputs which is connected to the control inputs of the keys, and the second to the overwriting inputs of a group of registers, respectively, the first and second groups of elements And , the first, second and third delay elements, the second and third elements AND, the pulse generator and the memory element, the outputs of which through the third element AND are connected to the counting input of the first counter, switching electric the cop whose output is connected to the input of the memory element, the OR element and the time code generator, while the zero output of the first counter is connected to the register overwriting input, the first inputs of the same name elements of the first and second groups are combined with the first information inputs of the Bloc information inputs of the switch respectively, the same inputs of the register group are combined with the second inputs of the AND elements of the first group and connected to the register outputs, respectively, the outputs of the matching elements are connected to the second inputs of this The elements of the second group and from the input 10 of the second element I, the inverse output of which is connected to the first input of the first element I, the outputs of the time code generator are connected to the third information inputs of the memory block, the outputs of the elements AND of the first group are combined by the fourth information input of this block, the outputs of the elements And the second group are connected to the counting input of the third counter

20 and through the third delay element with the memory input of the memory block, the other inputs of which are connected to the outputs of the third counter, the second input of the first element I is connected to the first memory memory and connected to the information output of the first counter outputs of the first counter, another ka and the output of this element is connected to the output of which is connected to the control with the second OR element, the output of the switch input, and the overflow output of this counter is connected to the first input of the OR element, the information outputs of the second counter are connected to the second information inputs of the memory block, with the second inputs quantizer input signals and

with the information inputs of the switch, respectively, the same inputs of the register group are combined with the second inputs of the AND elements of the first group and connected to the register outputs, respectively, the outputs of the coincidence elements are connected to the second inputs of the AND elements of the second group and with the inputs of the second And element, the inverse output of which is connected to the first input of the first element And, the outputs of the time code generator are connected to the third information inputs of the memory block, the outputs of the elements And of the first group are united by the fourth information This inlet-insulating block, and outputs elements of the second group are connected to the counting input of the third counter

and through a third delay element with a write input of the memory unit, the other inputs of which are connected to the outputs of the third counter, the second input of the first element I is connected to the first ingo connected to the counting input of the second counter and through the first delay element to the zeroing input of the first counter, and the overflow output the second counter through the second delay element is connected to its input zeroing about

Claims (1)

SUMMARY OF THE INVENTION A device for detecting discrete signals containing coincidence elements, a memory unit with a print control module, a first counter and a first element And, characterized in that, in order to increase the number of recorded signals and increase the information content recorded on the medium data, into it are introduced sequentially connected quantizer of input signals and a register, the outputs of which are connected to the first inputs of coincidence elements, a group of keys whose outputs of the same name are combined at the second inputs coincidence elements, respectively, a group of registers with outputs connected to the corresponding inputs of the key group, second and third counters, g switch, the first group of outputs of which ^{1 is} connected to the key management inputs, and the second to the rewrite inputs of the group of registers, respectively, the first and second groups elements And, 10 first, second and third delay elements, second and third elements And, a pulse generator and a memory element, the outputs of which through the third element And are connected to the counting input 1G of the first counter, switching an element whose output is connected to the input of the memory element, an OR element, and a time code generator, while the zero output of the first counter is connected to the register overwrite input, the first inputs of the same elements of the first and second groups are combined with the first information inputs of the memory block and connected to the information outputs of the first counter, the other output of which is connected to the control input of the switch, and the overflow output of this counter is connected to the first input of the OR element, the information outputs of the second counter connected to the second information inputs of the memory block, to the second inputs of the quantizer of the input signals and ⁸ to the information inputs of the switch, respectively, the same inputs of the register group are combined with the second inputs of the elements of the first group and connected to the outputs of the register, respectively, the outputs of the matching elements are connected to the second inputs of the elements of the second group and with the inputs of the second element And, the inverse output of which is connected to the first input of the first element And, the outputs of the shaper of the time code are connected to a third by the information inputs of the memory block, the outputs of the elements of the first group are combined On the fourth information input of this block, the outputs of the elements of the second group are connected to the counting input of the third counter and through the third delay element to the recording input of the memory block, the other inputs of which are connected to the outputs of the third counter, the second input of the first element And is connected to the first information output of the first counter ,. and the output of this element is connected to the second OR element, the output of which is connected to the counting input of the second counter and through the first delay element to the zero input of the first counter, and the overflow output of the second counter through the second delay element is connected to its zero input about Figure 2