SU448458A1 - Input device - Google Patents

Description

one

The invention relates to the field of automation and computing.

Devices are known for inputting information from a number of pulse sensors into a computer, comprising a buffer register, counters of signals from a number of pulse sensors, a poll distributor, a synchronization unit, a control unit, and a interface unit with a computer.

The purpose of the invention is to reduce the cost and increase the reliability of the device.

The goal is achieved by introducing an address driver, the inputs of which are connected to the outputs of the buffer register and the polling distributor, and the output with an interface block, and a signal counter, one input of which is connected to the interface block and the control unit, the other input the third input with the synchronization unit, the polling distributor and the buffer register, and the output of the signal counter is connected to the interface unit.

The drawing shows a block diagram of the device.

The buffer register 1, which is an individual single memory, is designed to receive signals from each number-pulse sensor. The shaper 2 sensor addresses, represented by an encryption scheme, are designed to organize the memory cell address of the computer in which the current is stored; and the sum of the signals

from this sensor. The polling distributor 3, p), which is a switching circuit, is intended for cyclically circling the bits of the buffer register. A counter of 4 signals with a number of pulse sensors, made in the form of an electronic counter with a width of a cell of a computer memory, is intended to add 1 to the current sum of signals for each of the number of pulse sensors. The interface unit 5 organizes the connection of the device with the computer, converts the individual data format into a standard one and provides a specific sequence of control signals through the interface. The synchronization unit 6, made on the basis of a generator operating in a multivibrator mode, is designed to generate a series of pulses necessary for clocking the control circuits of the device. The control unit 7 is designed to organize the polling of the buffer register and the exchange of information between the memory of the computer and the count of pulse signals.

The scheme works as follows.

A certain clock pulse coming from synchronization unit 6 records information from the number of pulse sensors into buffer register 1. At the time of analyzing the state of buffer register 1, reading information from it and integrating it, writing to buffer register 1 is prohibited.

According to the enabling signal from the control unit 7 and the clock pulse from the synchronization unit 6, the polling distributor 3 switches the next group of bits of the buffer register 1. The control unit 7 analyzes the state of the polled bits of the buffer register 1. When information is found, at least in one bit communication with a computer. At the same time, at the output of the imaging unit 2, the modified code of the address of the youngest of the polled bits of the buffer register 1 is set, on which a single information is recorded. This code is the address of a computer memory location that stores the current sum of signals from a pulse number sensor, the output of which is connected to the input of the polled digit of the buffer register 1.

The modified address from the output of the imaging unit 2 is fed to the information inputs of the interface block 5 and, via a corresponding signal, from the control unit 7 is output to the input-output control unit of the computer.

In response to this, the I / O control device puts into the interface unit 5 the contents of the memory cell whose address was issued. The cell content is the current sum of the signals on the corresponding count pulse sensor. This number, according to a certain clock pulse, from the synchronization unit 6 is copied from the outputs of the interface unit 5 to the counter 4 of the number of pulsed signals through its register inputs.

The next clock pulse arriving at the counting input of the counter 4 adds "1 to its content. The new sum is fed from the outputs of the counter 4 of the pulse signals to the information inputs of the interface unit 5 and, according to the signal from the control unit 7, is stored in the same memory cell of the computational mashina. At the end of the transmission, the signal from the control unit 7 clears the counter 4 and resets the corresponding bit of the buffer register 1. Then the whole cycle is repeated for the next bits of the buffer register 1, which stores

single information from the number of pulse sensors.

After processing the information on all the bits of the polled group of buffer register 1, the poll distributor 3 moves on

the signal from the control unit 7 and the corresponding clock pulse from the synchronization unit 6 to the next position, repeats again the entire cycle of polling and integrating information from another group of number-pulse sensors.

Thus, using a single signal counter 4, information is accumulated from a large number of n-pulse sensors. The central computer is not involved in the accumulation operation. The interruption of a computer is issued only when the sum reaches a certain, predetermined value.

Subject invention

A device for inputting information comprising a buffer register, a polling distributor, a synchronization unit, a control unit, and an interface unit, characterized in that

that, in order to increase the reliability of the device, an address driver has been entered into it, the inputs of which are connected to the outputs of the buffer register and the polling distributor, and the output with the interface unit, and a signal counter, one input of which is connected to the interface unit and the control unit the input is with the control unit, the synchronization unit, the polling distributor and the buffer register, and the output of the signal counter is connected to the interface unit.

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