SU756659A1 - Matrix signal generator - Google Patents

Description

The invention relates to communication technology and is intended to generate a matrix of signals used to transmit discrete information.

A matrix generator 5 is known, containing a master oscillator, the output of which is connected to the first inputs of the shift register and the element I, the second input, and the output of which are connected respectively to the first output of the control trigger and the input of the binary frequency divider, the output of which is connected to the first input control trigger, the second input of which is connected to an additional input of the register of the shift register, the outputs of which are connected to the first inputs of the corresponding elements And, the second inputs and outputs of which are connected to the outputs of the remote fratora whose input is fed Tacto vy-20 signal and the OR gate inputs and the output trigger [1].

However, the known generator of matrix 25 signals has a limited frequency range and design complexity. ·

The aim of the invention is to expand the frequency range.

2

To this end, a matrix signal generator containing a master oscillator, the output of which is connected to the first inputs of the shift register and the element I, the second input and output of which are connected respectively to the first output of the control trigger and the input of the binary frequency divider, the output of which is connected to the first input of the control trigger, The second output of which is connected to the auxiliary input of the shift register, the outputs of which are connected to the first inputs of the corresponding elements And, the second inputs and outputs of which are connected to the outputs of the decrypt RATOR, at the input of which a clock signal is supplied, and the inputs of the OR element, as well as the output trigger, additional AND, OR elements and a binary switching glint are introduced, the inputs of which are connected respectively to the outputs of the OR element and the master oscillator, while the additional decoder outputs are connected respectively, to the first inputs of the first additional element AND and the first additional element OR, the output of which is connected to the first input of the second additional element AND, the second and third inputs of which are co3

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are united respectively with the output of the OR element and the second output of the control trigger, and the second, third and fourth inputs of the first additional element And are connected respectively with the output of the binary switching unit, the second output of the control trigger and the first output of the Nogo trigger, the input of which is connected to the second input of the control trigger controlling the binary input, the frequency divider and the output of the second additional element OR, the inputs of which are connected to the outputs of the additional elements AND, the second od trigger output connected to a second input of the first OR additional element.

The drawing shows the functional electrical circuit of the proposed device.

The matrix signal generator contains master oscillator 1, shift register 2, AND 3 element, control trigger 4, binary frequency divider 5, AND 6, 7 and 8 elements, decoder 9, OR 10 element, output trigger 11, as well as additional AND elements 12 and 13, OR 14 and 15, and a binary switching unit 16.

The device works as follows.

The high-frequency signal from the master oscillator 1 through the element And 3 enters the binary divider 5 frequency. The latter, overflowing, sets the control trigger 4 to the state "0", thereby closing the element 3, stops the supply of pulses to the binary divider 5 of the frequency. Simultaneously from the inverted output of the control trigger 4, the signal "I ^th is fed to the sequential register 2 shift and to the input of additional elements I 12 and 13, preparing them to pass through them a pulse from one of the outputs of the register 2 shift to the input of the output trigger 11.. the control input of the shift register 2 constantly receives clock pulses from the master oscillator 1. In the process of advancing "1" through the shift register 2, a pulse delay occurs. After some time the signal from the shift register 2 through one of 6, 7 and 8 / elements cat ing fed with pulse decoder 9, an OR gate is held at 10. With its output to the count input of the output flip-flop 11 has two branches passage.

The right one through the second is optional: the element I 13 is used for even and odd division factors, and the left one through a binary switching unit. 16 and the first additional element And 12 only for odd.

From the second additional element OR 15, the pulse arrives at the counting input of the output trigger 11 and the measurement * ·

his state, thus ending the formation of one half-period of a given frequency position of the signal matrix. Simultaneously, the pulses from the output of the second additional Element OR 15 are fed to the installation input "1" of control trigger 4 and the installation input "0" of the last trigger of binary frequency divider 5. The first goes to state "1" and opens element I 3.

‘From this moment on, the formation of the second half period of the output signal begins. The path of the pulse from the master oscillator 1 to the output trigger 11 remains

15 the same. A pulse arriving at its input changes the state of output trigger 11, thus ending with the formation of one oscillation period of a given frequency position of the matrix. Therefore in this case the division factor

K '= 2 (2 * + Ν)

where 2 ¹¹ is the division factor of the binary frequency divider 5;

25 N - the division ratio of the register 2 shift is really an even number.

The formation of the frequency position of the signal matrix, obtained by dividing the frequency of the master oscillator by an odd number, occurs differently. At the same time, from the decoder 9 to the first additional AND 12 element comes "1" and the first additional element OR 14 to "0" . Now the signal path from the element OR 10 to the output trigger 11 is determined by the state of the latter.

Obviously, finding the output trigger 11 in the state "1" allows the pulse to pass through the second additional element AND 13, and the reverse state of the output trigger 11 allows the signal from the element OR 10 to pass through the binary switching unit 16 and the first additional element 12. In the binary switching the block is an additional signal delay for one period of high-frequency oscillations. Thus, the resulting division ratio in this case is odd;

Κ «= 2 (2 ^η + Ν) -» - ΐ.

Thus, when forming

the frequency positions of the matrix, which are divided by the frequency of the master oscillator into even and odd coefficients, use the same basic elements: the binary frequency divider, the shift register, the elements

> AND, OR. It simplifies the device and

6θ increases its reliability, which distinguishes it from the prototype.

In addition, the use as a divider with a variable division register shift register leads to

• 65 that the master oscillator can

five

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work at any frequency, limited only from above by the final speed of the microcircuits.

Claims (1)

Claim .A matrix signal generator containing a master oscillator, the output of which is connected to the first inputs of the shift register and the element I, the second input and output of which are connected respectively to the first output of the control trigger and the input of the binary frequency divider, the output of which is connected to the first input of the control trigger, the second output which is connected to an additional input of the shift register, the outputs of which are connected to the first inputs of the corresponding elements And, the second inputs and outputs of which are connected to the outputs of the descript-Yurator, on the input of which is fed a clock signal, and the inputs of the OR element, as well as an output trigger, characterized in that, in order to expand the frequency range, 25 introduced additional elements And, OR and binary switching unit, the inputs of which are connected respectively to the outputs of the OR element and the master oscillator, while the additional outputs of the decoder are connected respectively to the first inputs of the first additional element AND and the first additional element OR, the output 5 of which is connected to the first input of the second additional element And, the second and third inputs of which are connected respectively with the output of the OR element and the second output of the control trigger ϊθ, and the second, third and fourth inputs of the first additional The leg of the element and are respectively connected to the output of the binary switching unit, the second output of the control flip-flop output and the first output latch having an input coupled to the second input of the control flip-flop, a control input of a binary divider. frequency and output of the second additional element OR, the inputs of which are connected to the outputs of additional elements AND, and the second output of the output trigger is connected to the second input of the first additional element OR.