SU1203515A1 - Dividing device - Google Patents

Description

OR of the control unit, the outputs of which are connected to the bit outputs of the counter of the control unit and the second control input of the demultiplexer, the outputs of the elements of the second group are connected to the information input of the buf

The invention relates to computing and can be used in dividing and -digit numbers.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a device for dividing; FIG. 2 is a block diagram of the control unit of FIG. 3 - time diagram of the device.

The device contains registers 1 divisible and 2 dividers, block 3 divisions, I / K K -digital multipliers 4, subtractive counter 5, first adder 6, subtractor 7, second adder 8, three groups of elements AND 9-11, buffer register 12, control unit 1, demultiplexer 14, private register 15, sign 16 output of subtractor 7, outputs 17-19 of control unit 13, output 20 of control unit 13 of device termination.

The control unit 13 comprises an AND element 21, a first delay element 22, a second delay element 23, a counter C 24, and an element OR 25.

On the timeline of work

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devices 1.J1 and tjj delay times of delay elements 22 and 23, respectively: 1,2,3, ..., Q is the number of device operation cycles.

The TI input of the control unit 13 is the device clock input, the device output A is the information inputs of the divisor register 1, the device inputs the information inputs of the divider register 2, the input Q of the control unit 13 is the input of the device’s cycle number code, and output C of the register 15 private - the output of the device.

The device works as follows.

The ferric register, the bit outputs of which are connected to the second inputs of the elements AND of the third group, whose outputs are connected to the second information input of the register of the dividend.

In the initial state in the register 1 of the dividend, the direct code of the h-bit divisible is stored, in register 2 of the divisor - the direct h-bit code

the divisor, in the C 24 counter, is the constant Q of the number of division cycles, the buffer register 12 and the private register 15 are set to zero. It is assumed that the dividend and divisor are correct.

the positive fractions and the divisor in absolute value are greater than the dividend. The process of determining the frequency consists of. of i-1 cycles (where TA H / k is the number of K-bit groups

private).

The first cycle begins with the determination of the most significant bit of the quotient of the quotient, which is formed in block 3 division, the inputs of which

Outputs 2 To the higher bits of the register 1 of the dividend and the outputs of the k high bits of the register 2 divider. The difference between the value of the private, obtained by dividing

I h is the digit number, and the value of the quotient, obtained by dividing 2k most significant bits of the dividend by k most significant bits of the divisor, lies within

About f -2.

The k-bit private value obtained by dividing truncated numbers can either be equal to the value of the highest ones; k private bits obtained by dividing h-bit numbers, or more than one unit of the least significant bit with a weight of 2. With the help of multipliers 4 and adder 6, the product of the h-bit divider by k-bit quotient is formed, and with the help of subtractor 7 - the next remainder, defined as the difference between the contents of the register 1 of the dividend and the content of the adder 6.

The result from the outputs of the subtractor 7 is fed to the first inputs of the adder 8, the second inputs of which, in the case of a negative residual, are fixed to the divider from the outputs of the register 2 divider in the case of a negative residue. If the remainder at the output of the subtractor, 7 is positive, then at the output 16, the zero and the remainder at the adder 8 add up with a zero value at the outputs of the And 11 group elements. The result from the outputs of the adder 8 through the elements of the 9th group under the control of the signal 17., From the output of the control unit 13 is recorded in the buffer register 12. In the case of a negative remainder, k-pazpone, e is obtained with an excess per unit of the least significant bit with a weight of 2 therefore, in the subtracting counter 5, under the control of the output 16 of the sign bit of the subtractor 7, the k-bit quotient of the least significant bit is reduced; result

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This subtraction — the exact value of the k-bit private — is de-multiplexed 14 under the control of signals 17 and 19 from the outputs of control unit 13 to the high-order bit of register 15 private.

The positive balance from the outputs of the buffer register 12 under the control of the signal 18 from the output of the control unit 13 with a shift to k bits to the left (towards the higher bits) is written to the register 1 of the dividend and serves in the next cycle as a dividend. At the end of the cycle with a signal from

15, the output of the second delay element 23 is performed by decreasing the content of the CW 24 counter by a unit of lower order.

In each subsequent cycle, the next k-bits of the exact quotient bits are recorded in the register of the private 15, starting with the most significant bit obtained in the first cycle.

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20 Editor To Petrash

Compiled by E.Zakharchekko

Tehred I.Astalosh .. Proofreader A.Obruchar

Order 8417/51

Circulation 709Subscribe

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, ud.Proektna, 4

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FIG. 2

FIG. five

Claims (1)

DEVICE FOR DIVISION, containing the registers of the dividend, divider, division block, ^and | k-bit multipliers (and - the resolution of the dividend and divider), an adder, subtractor and control unit, and the outputs of the divider and the dividend device are connected respectively to the information input of the dividend register, outputs K 2 MSBs are connected to first inputs of a subtracter and a divider, a second input coupled to an output of the adder, the first and second information inputs connected with outputs to senior and K ⁿ LSBs 1k multipliers, respectively, the first and second inputs of which are connected respectively to the outputs of the division block and the divider register, characterized in that, in order to improve performance, a subtracting counter, a second adder, three groups of AND elements, a buffer register, a demultiplexer and a private register are introduced into it, and the control unit contains a counter, an OR element, an AND element, and two delay elements, the output of the result of the device being connected to • the outputs of the private register, the information inputs of which are connected to the outputs of the demultiplex ora, the information input of which is connected to the output of the subtracting counter, the information input of which is connected to the output of the division unit, the second information input of which is connected to the output K of the upper bits of the divider register, the bit outputs of which are connected to the first inputs of the elements K of the first group, the second inputs of which are connected to the counting input of the subtracting counter and the output of the digit of the subtracter, the bit outputs of which are connected to the first information input of the second adder, the second information input which is connected about the outputs of the elements AND of the first group, and the output is connected to the first inputs of the elements AND of the second group, the second inputs of which are connected to the first control input of the demultiplexer and the output of the first and the input of the second delay elements of the control unit, the output of the second delay element of which is connected to the first inputs of the elements And the third group and the counting input of the counter of the control unit, the information input of which is connected to the input of the code of the number of cycles of the device, the clock input of which is connected to the first input of the element AND block board, a second input coupled to an output end of the device and the output element OR control unit, the outputs of which are connected to the discharge outputs of the counter of the control unit and the second control input of the demultiplexer, the outputs of the AND elements of the second group are connected to the information input of the buffer register, the discharge outputs of which are connected to the second inputs of the AND elements of the third group, the outputs of which are connected to the second information input register divisible.