SU1541594A1 - Arithmetical unit with microprogram control - Google Patents

Abstract

The invention relates to the field of computing and can be used in the design of arithmetic devices of computers. The purpose of the invention is to increase the speed of the main commands of division operations while reducing equipment. The device contains an arithmetic logic unit made up of N computational cells and an accelerated transfer node, a bus driver, a state controller, a memory address register, two operand sampling nodes, each of which contains a connected address multiplexer and an address register, and a microprogrammed control unit, consisting of a command register, a command decoder, an interrupt decoder, a firmware control node, a microinstruction memory node, a first microcommand register and an interrupt processing node, as well as the connection between -bound elements according to the drawing. New is the introduction in the microprogram control unit of the micro-command address register, the second micro-command register, the bit signal decoder and the private bit generator. The address decoder is inserted into the operand selection node, connected between the second output of the address multiplexer and the second input of the address register. The private bit generator contains a private decoder and an address decoder. 9 il.

Description

ISO. Brethren is related to computing and can be used in designing arithmetic devices of computers.

The purpose of the invention is to increase the speed of execution of basic commands and the division command while reducing equipment.

Figures 1 and 2 show diagrams of an arithmetic device with microprocess control; on fig.Z - structural diagrams of the first node of the sample operands and shaper

dov private; FIG. 4 shows the microcommand format; Fig. 5 is a diagram of the organization of the firmware control; 6 is a time chart of the organization of the firmware control; , FIGS. 7 and 8, division algorithms; Fig. 9 shows the contents of the Fission cycle execution algorithm.

Rhymetrical device (Figures 1 and 2) contains arithmetic logic unit 1 (AB), which performs arithmetic and logical operations on rand operatives; microprogram control unit (BMU) unit 2 controlling the operation of the battery.

AB1 contains arithmetic logic unit 3 (ALU), consisting of computational cells 4-7 (1-N) (large integrated circuits, for example, BIS.1804 BC1); the node 8 accelerated transfer (2UPP) (BIS 1804 BP1), which serves to organize the accelerated transfer between cells of the ALU; 9 states controller (CIL) - (BIS 1804BP2), used for the connection of shear elements

ALOUS, control of transfer signals, recording, reading and modifying the signs of the state, generating a flag (control transmission signal) for organizing branches along a microinstruction; a bus driver 10 (SFI), which is used to communicate the interface bus; a memory address register (RAL) 11, for storing a memory address during fetch or write operations; the first node 12 of the sample operands (SVR) and the second node 13 of the sample operands.

Firmware control unit (MCU) block 2 contains a command register (RC), which is used to store command information on the channel during execution; 15 interrupt vector decoder (LBD) - (BIS555РТ7 (2Кх8), interrupt vector code transcoder into the initial addresses of the corresponding interrupt processing microprograms; 16 commands decoder (LBD), which is a permanent storage device that decodes the operation code into the microprogram's initial address of this operation ; node 17 of microprogrammed control (UMU) - (BIS1804VU4), generating the following address of microcommand depending on the signal G

ten

25

415944

control (flag) of the KCC9 device; an address generation register (upper bits) serving to store the address of the microcommand during its retrieval from the memory node; micro-command memory node 19 (UPMK) - four eight-section sections of the Navy 556PT16 (8Kx x8); the first register of 20 micro-instructions (PQM) is a conveyor register used to store the micro-command for its execution time (32 bits) synchronously with the signal; the second register of 21 micro-instructions (PQM) is a conveyor register used for storing the micro-command and its execution time (32 bit) synchronously with the signal T; interrupt processing node (OPS) - (BIS 585I314), which serves to control the priority levels of interrupts, receive interrupt signals and form their vectors; a decoder for 23 bit control signals (DSBBS), a shaper of 24 bits of a private (PSD), a data bus 25 and a bus 26 of address, a source 27 of direct current; 28 clock direct input; input 29 clock inverse signals; input 30 Instal 15

20

ka

The node 12 contains (FIG. 3) the address multiplexer 31, the address decoder 32 and the address register 33, and is distinguished from the node 13 by the presence of the address decoder 33. The private bit shaper contains the address decoder 34 and the private decoder 35, the input 36 is logical 1, the input 37 is logical O.

In order to synchronize time processes, the address information of the microcommand at the output of register 33 must be synchronous with the operation of ALU 3. For this purpose, the reception of the address at the RA input is gated with a clock pulse T, which also blocks the operation of ALU 3.

The decoder 32 zero-bit address (LAD) node 12 emulates the zero-bit address d depending on the input signals C1-SZ by the formula

d - (C, where C, C and

C2) SC,

C3

the inputs of the decoder 32; - the output of the decoder 32.

515A

The truth table of the states of the input and output signals of the DSHA 32 I is presented in Table 1.

Table 1 C, J Cr Sz

Note. X matches any value (0 or 1); The DSHA 34 serves to eliminate the generation due to the positive feedback of the inputs and outputs of the shift registers POH and Q ALU.

At inputs 1-4 of the decoder 34, a combination of code 0110 with a constant current source (+ 5V) is implemented.

In each command, the division (Fig. 3 under the control of RON ALU 3 of the highest bit of the shift register (output 9 cells 4 ALU 3) containing the value 16 (the oldest of the 32 bits) of the divisible remainder, the even / odd address of RON ALU is emulated 3 according to table 2.

table 2

Emulated RON address value

About 1

Even (14) Odd (15)

Note. The initial value of RON ALU 3 specified in the microcommands of the division cycle is odd, for example, 15.

The format of the microcommand of the proposed AU is shown in FIG. The word microcommand is contained in the registers RMK 20, RMK 21 (0-31 and 32-63rd bit of microcommand, respectively). Register bits are combined into device control fields (a total of nine fields). The number of microcommand fields (0-63) corresponds to the size of the outputs of the blocks of the registers RMK 20 and RMK 21.

5946

The control field of the PMK 20 register (0–31st digit of the microcommand): the first control field (23–31st digit of the MC) - control of the functions of the ALU 3; the second control field (20–22th bit of the MK) - management of loading the initial addresses of microprograms of commands (ASC 16), vectors of microprograms of interrupt processing (SSP 15), return addresses of microinstructions (RMK 20); the third control field (12th to 15th bits of the MC) is the control of receiving data from the ShFI 10 from the interface 25 bus; 5, the fourth control field (16th to 19th bits of the MC) —controls the functions of forming the address of the CMD microcommand 17; the fifth control field is the formation of microcommands of three parallel formats; the first format (0-11th digit of the MC) Address - the formation of the address constant of UMU 17; the second format (0-8th bit of MK) I Constant - formation of a constant as operand of ALU 3; the third format (0-4th bit of MK) Shift - formation of functions of shifts KCC 9.

The use of multi-format microcommands (the use of individual bits and microcommand fields (words) to form the functions of bits and microcommand fields (words) to form the control functions of various devices) allows the required word length of the microcommand to be diverted. For example, in the considered structure of the BMU, the length of the microcommand word is shortened by 15 bits.

The control field of the PMK 21 register: the first control field — the control of nodes 12 and 13 of the ALU 3 (48–59th bit of the MC) - is divided into the control of node 12 (the 48–53th level of the MC), 5 per control of the node 13 (54-59th bit of the MK), 50-53th and 56-59th of the first-floor MC are involved in choosing the register number through ports A and B of ALU 3 and 48, 49 and 54, 55th bit dy 0 MK in the choice of the source of the operand in ALU 3; the second control field is the BCB 23 control (60-63rd bit of the MC), which are used to form sixteen bits of the micro-command control features; the third control field is the management of the recording of the signs of the state and the formation of the KCC 9 flag (32–44th bit of the MC); fourth control field - formation when

five

0

715

interface characters that serve as interface information support signals and control the operation of SHFI10 and PAII11 (bit 45–47 of the MC).

In the block diagram of the organization of the firmware control (FIG. 5), the interrelationships of the main information flows of the UKS 2 and A3 1 between the blocks of the UMU 17, RAY 18, UPMK 19, RMK 70 and RMK 21 nodes 12 and 13, ALU 3 and KCC 9 are shown.

From the output of the CMD 17 to the 12-bit bus, the address of the microcommand enters the first group of inputs of the RAMK 18. The address code of the microcommand is fixed by the leading edge of the strobe T via the first input of the RAMK 18. The temporary strobe T is a signal with a period of 0.5 µs and a duty cycle of 2. Time signal T is an inverse signal T.

From the output of the RAMK 18, the 12 most significant bits of the address come from the microcommand to the input of the node 19. The T signal is also connected there; which is zero in this case (lower-order bit address). Therefore, during the period of passage of the signal & T, the information from the 32-bit bus on odd and then on (even address. Read information | from TPCM 19 is written to the first groups of inputs of the registers RMK 20 and RMK 21 at the time of the leading edge of the signals T and T arriving at the first inputs of the registers.The information from the first group of outputs of the RMK 21 about the choice of sources of operands is shifted forward to the tact of the ALU 3 operation, is fed to the inputs of the MPA of nodes 12 and 13 and is synchronized by the gate T.

With the selected nodes 12 or 13, arithmetic and logical operations in ALU 3 are performed on the four-bit addresses of the addresses of the cells 4-7 with the operand. The operation results in a selection of status indications with an output of the status indication of the ALU 3 cells. KCC 9 for storage and modification.

The result after processing the signals on a 13-bit bus (the third group of outputs of the RMK 21) arriving at the input of microcommands KCC 9 is the generation of a signal F at the output of the transition condition KCC 9, post 5948

barking in node 17 at the entrance (CL). When generating a signal F from the output of the KCC 9, information on a 12-bit bus with

The fifth group of outputs RMK 20 passes through the first group of inputs to node 17 as information of the next address MK. In the absence of an F signal from the KCC 9, the 12-bit address from the CMD 17

Q is formed depending on the code combination on the 4-bit bus of the inputs to node 17.

Consider the essence of the interaction of blocks 1 and 2.

 The start of operation is initiated by a signal set at the input of the PMK20, according to which the address of the microcommand from the fifth output of the register 20 is recorded synchronously with the signal

Q T in two cycles through node 17 in PAMK 18. This is the initial state for starting the operation of the device.

The address of the MC is formed at the input of the node 19 sequentially for the period

5 T signals twice: in odd and even half periods, differing by one of the least significant bit. The information selected at the odd address is recorded in the RMK 21 by the signal T, and even in the RMK 20 by the signal T. The information stored in the register of the RMK 20 controls the operation of ALU 3. The number of the general register (RON) ALU 3 is produced

c nodes 12 and 13 synchronously to the signal T. The dotted lines in Fig. 4 show the passage of information simultaneously for three consecutive values of the next address of microcommands (А А + 1, А + 2).

At the time interval X, the following actions occur.

Under the control of registers 20 and 21, arithmetic or logic

The 5 ces operations in ALU 3 for F A are formed from its results, signs of the word process state and are recorded at the end of the time interval in CSC 9, Under the control of the PAMC 18 register and T sign, two times are selected (odd, then the even address MK A + 1) the information from the ZUMK 19 and at the end of the time interval X is recorded, respectively, in the RMK 21 (odd address) and RJ 20 (even address). Under the control of a 4-raster tire from the fourth group of outputs of the RMK 20, the following address of the micro-command is formed in CMD 17

0

91

A + 2 and at the end of time interval X is recorded in RAMK 18.

The dynamics of the formation of the next microcommand address, the operation of the AAP and CBS is illustrated by the timing diagram presented in Fig. 6, in which the numbers of cyclograms are vertically marked from top to bottom, horizontally the duration and types of cyclograms with the selection of time interval X.

The cyclograms 1 and 2 show the sequence of sync pulses T and T, synchronizing the operation of the device. On cyclograms 1-10, the work of the sequence of micro-instructions from A-1 to A + 5 is considered.

Suppose that the time X corresponds to the execution of micro-command A according to the sequence diagram 5 in ALU 3.

Then in the register of PMK 20 (cyclograms 3 and 4) there is information controlling the operation of the A-th micro-command, and in the register of RMK 21 during the first half-period there is information for the A-th micro-command, and during the second half of the period - for A + 1 microcommand. At the same time, under the control of PAMC 18, containing information on the number of microcommand A – H (sequence diagram 9), the odd number and then the even address of the A + 1th micro command are selected from the unitary program 19 (sequence diagram 7).

The selected information, corresponding to the A + 1st micro-command, from UPMK 19 at an odd address is recorded in the PMC 21 (cyclogram 4) and at an even address - in the CMC 20 (cyclogram 3). The RON ALU 3 number, containing the operand required to perform the ALU operation, is stored in node 12 or 13 in synchronization with the operation of ALU 3 (sequence diagram 10).

 From the timing diagram (Fig. 6) and the block diagram of the control organization (Fig. 5), it can be seen that the proposed scheme has a conveyor for 2 outputs of the next microcommand address, i.e. when actions are performed under the control of micro-command A in ALU 3, under control of the CAMA 18, information A + 1 of the micro command is selected from UPMK 19, and the address of A + 2 micro-command is generated at CMD 17. Combining the production process. The following address for microinstructions A, A + 1, A + 2 creates an opportunity

ten

five

The possibility of a significant reduction in its execution time.

Twice sampling from ULMK in one cycle reduces the number of UPMK microcircuits by one half. The time cycle (if information is doubled from ZUMK 19) is reduced from T 300 not to T 250 not Q in a specific implementation example.

Figures 7 and 8 show the algorithms for performing the division operation (the division method is without restoring the remainder).

Operator 1 performs the following actions: sets the required number of cycles (equal to the number of digits of the divider in the cycle counter of the DMD 17; choose from the external memory 0 from the value of the dividend (double length 32 bits) and the divider (16 bits); dividend placed in the RON and RANU 3 shift control registers; the divider in another RON ALU 3 register. 5 Operators 2 and 3, by the value of divider Y 0 or divisible X 0, transfer control over the execution of operator 12 actions that form the status word - 0 tatam divide operation, with Cheney operands x Y 0, X f O is transmitted by the operator control 4.

Operator 4 by the value of the most significant bit of the divider transfers control to operator 5 in the case of Zn Y 1, or on operator 6 in the case of Zn Y 0.

Operator 5 performs preparatory operations on placing in Q two adjacent registers of the RON-ALU divider value so that the selected divisor number contains the direct divider code and the odd-numbered code is additional. Operator 6 performs the same operations as operator 5, i.e. the additional divider is written into the odd RON ALU, and the even divider is written into the even direct code. The operator 7 performs the actions of the first Q dividing cycle, after which the results of the first cycle are analyzed by the operator 8.

In the event of division incorrectness (overflow of the 16-bit-wide dividing result of the dividing grid), the control is transferred to the operator for the formation of signs of the operation, otherwise the remaining division steps are performed by operators 9-11 (analysis

five

 one

the conditions for the division inaccuracy are not considered hereinafter).

Consider separately the division cycle (Fig.9).

In the device, all actions of these operators are performed by operators 9 and 10 (Fig. 8), which are two microcommands. The actions of these microinstructions include the addition of a residue and a divider; subtraction from the remainder of the divider.

These actions are performed depending on the values of the divider signs and the highest bit of the dividend (remainder) according to Table 3.

Table 3

154159412

RAPU register register according to Table 4.

ten

T a

faces

T a

faces

Note. The highest bit of the dividend (remainder) is analyzed after the actions in the previous division cycle.

In the microcommand of the division cycle, the odd RON address of the pair of RON registers is specified, in which the forward or additional divisor codes have been generated by the operator 5 or 6. Therefore, taking into account the microcommands the odd address of one of them, allow node 12 to select the desired operand (divider) in the forward or additional code for the add-in microcommands for the subdivision of the dividend (input 4) and the division sign (input 5).

At the same time, the result obtained in the registers — the RON shifter (.degree) and the lower bits of the dividend (register Q) move left one bit. But the value of the older bit of the RON (remainder) and the sign of the PDD24 fixed in the Republic of Kazakhstan and the KCC 9 is generated by the bit private and is written into the isp

The formation of the bits of the quotient in the KCC9 is performed by FDF24 by switching the shift function (codes 0110 or 0111) by changing the value of the least significant bit of the function.

Shift control codes correspond to the types of shift (Table 5).

35

Table 5 Type of shift

Shift code

0

0110

Per.RON 15 O

Per. 15 o

About raz d

"- {Balance |" - Private-Private

Per. RONPer, 1

0111 15 015 O

 Balance -) Private | "-

The shift function 0110 is indicated in each microcommand of the Divide cycle. The lower order bit of the shift function is switched in HDF24. The division cycle is performed by repeating (-Ј2)

time two microco

mand, where N is the number of bits of the divider).

The first microcommand of the division cycle performs decrement (subtraction) of the contents of the register of the counter of cycles of the BMU and the comparison of the obtained

13. 1

result with zero. If N 0 0, a transfer of control for the repetition of a micro-command occurs, if N 0 is transferred to operator 12.

Thus, the Dividing cycle consists in performing two micro-commands cyclically (when organizing a pipeline of sampling the next micro-command address with module two), in each of which one bit of a particular bit is formed. As a result, for the division cycle, two bits of the private are formed.

The microcommands (21- and 9.2-) of the division cycle differ only in the address function of the CID 2 (Fig. 7). In the first microcommand (address A), the decrement of the counter (reduction of the counter by a unit of the least significant bit) of the cycle of UMU 2 is performed, control is transferred depending on its value. In the second micro-command, unconditional (mandatory after the conditional: branch condition) is performed, the control is transferred to the micro-command with the address А + 1.

The work on performing arithmetic and logical operations on operands in ALU 3 is performed under the control of the microcommand fields from the first output groups of the RMK 21 (12-bit bus bottom) and the RMK 20 (9-bit bus bottom). Under the control of signals on the first group of outputs, the RMK 21 selects nodes 12 and 13 of the source addresses of the operands of the internal RAM of ALU 3 (source 1 — RK 14, source 2 — RMK 21). From the outputs of the PMK 20, the control of arithmetic or logical operations in ALU 3 on the operands is performed. Operands can be used depending on the values of the control functions of the ALU 3 coming from the first & (9-bottom tire) and fifth (5-bottom tire) of the outputs of the RMK 20, from the internal RAM of the ALU 3 or from the data bus 25 through ShFI 10 to the D-inputs of the ALU 3.

According to the results of operations on operands in ALU 3, signs (Z, C, V, N-inputs KCC 9) of the state words ALU 3 are generated. According to the control signals from the third group of outputs RMK 21 (13-bit bottom) in the KCC 9 memorizes and processes the signs of the state word and, depending on their combination, the signal F is generated for the organization 1594

14

branch of the firmware branching process. The process of exchanging information with external devices is carried out via address 26 and data bus 25. If it is necessary to exchange information with external information carriers over a narrow bus interface, the address and data are combined.

From the first exits of RAL 11, the address bus 26 receives a 16-bit address code and features for tracking it.

5 The result of operations on operands from the first outputs of the cells 4-7 ALU 3 is fed to the first inputs of the ShFI 10 for storing in the buffer register and broadcasting through the outputs of the ShFI 10 to 0 D inputs of the cells 4-7 ALU 3 as the operand of the next operation or the first inputs / outputs of the ShFI 10 to the data bus 25 for storage in external media. 5 in the case of storing the result of calculations in the external RAM, the microcommands generate the address of the external RAM cell from the first outputs of RAL 11 to bus 26, provide the interface to receive the address from RAL 11 and data from SchFI 10 through bus 25 to external RAM.

Due to the convolution of the time processes occurring in EMU 2 during the sampling time of the address of the next microcommand, a shorter information processing time (250 nons) is reduced when the BMU 2 equipment is reduced.

0 Various types of arithmetic and logical operations are performed in time: Type register register 1 µs (4 clocks) 5 Memory - register 2 µs (8 clocks) Multiplication 6-10 µs (24 40 clocks) Division 10-15 µs (40 60 cycles)

0 The execution time range is determined by the command system implemented.

Consider the work of the AU, starting from the moment it is turned on, i.e. initialization of the start address of the start-up firmware. Signal Installation at input 30, indicating the absence of secondary power supply voltage of the ALU or the presence of transient

15

processes at their establishment, goes to the installation input PMK2Q. In the PMK 20 register, under the control of the signal, the fourth field (Fig. 3) sets up the control function of the CMD 17 to generate addresses 0 ... 0 arriving from the fourth group of outputs on a 4-bit bus to the input group of the CMD 17. The SMD 17 generates 12 The bit address (0 ... 0) and exposes it at the output. The RAMK 18 writes the specified 0 ... 0 (even) address using the synchronization signal T and begins to fetch the contents of the zero cell of the UFMC 19 (senior bits 32-63) with the recording of information on the sync signal T in the PMK 21.

The sync pulse T connects the lower-order bit of the address at the UPMK input 19. Address 00 ... 01 (odd) selects the contents of the first cell from UPMK 19 and records it via the T signal in the PMK 20 (low-order bits 0-31). Thus ends the initialization process of the initial address of the firmware Initialization, in the process of BI & - the load of which is loaded, the values of the various counters and nodes AB1 and BU2 are reset. The initialization program ends with loading into PK14 of the first command at a signal from DSBR 23 received from the storage device. The command bits on the 16-bit bus go to the ASC 16. The data on the DSU 16 control input is controlled by the decoder outputs, switching the outputs from high impedance to active mode. At the same time, the signals at the output of the chipboard 15 and at the fifth group of outputs of the RMK 20 (return address) are in a state of high impedance, i.e. disabled.

From the output of the ASC 16 to a 12-bit bus, the start address of the command's firmware is sent to UMU 17, transmitted by it, emulated depending on the control function of the transfer of the address coming from the fourth group of outputs of the PLC 20. The emulated address is received from the output of UMU 17 to the information inputs of PAMK 18 and, as described, in the case of a sample of the initialization address, it is selected twice during the clock cycle from the DCS and is written to the registers RMK 21 and RMK 20.

Suppose that the next selected from the external storage bus

159416

Data 25 teams - team division. From the condition that in the registers RMK 20 and RMK 21 the code of the first division micro-command is set, the execution of the division firmware is started according to the algorithm (Fig.7 and 8). Operator 1 is performed on a sample of information.

JQ of the dividend and divider from internal registers RON ALU or external memory.

Location (source) of operands and memory addressing methods

15 are determined by the command system. Suppose that a command system of the type CM-4 is implemented. In this case, the information of the dividend is located in two registers RON, even and odd 20 nome, the number of the first one is specified in the command. The divider, depending on the addressing system specified in the command, is selected by a sequence of microinstructions according to the generated

25 address from external memory. Suppose that the command uses the addressing method9 when the address is placed in the RON with the number specified in the command's 0-2 bits (the address method is specified in the 3-5th bits). The first microcommands of operator 1 set the value of the specified RON ALU 3 to the output of ALU 3 and record its contents in RAS 11 as the address of the operand on highway 26.

The operand (divider) selected from the external memory from line 25 enters ShFI 10 and is recorded in the buffer register. FIR 10 implements the interface exchange procedure, i.e. receiving information on tracking signals and issuing appropriate quoting signals on receiving information under control

The dc of the control signals of the PMK microcommand 2. A third of the microcommand of the operator 1 rewrites the information of the divider from the buffer register ShFI 10 into the working RON ALU 3. A quarter of the micro5Q, the command of the operator 1 forms a constant about the number of cycles of repeating the microcommands of the division. From the fifth group of outputs of the RMK 20 to a 12-bit bus, the Address enters the UMU 17, where information is stored 35

55

ets in the loop counter.

Generating the next micro-command address when moving from the first micro-command to the second one, etc. implemented from the fourth group of outputs of the PMK 20 to the 4-bit bus. Moreover, each micro-command number A indicates the address of the sample from the U11MK A + 2 micro-command.

Having performed the actions of operators 1, and then operators 2 and 3 (the actions were considered in describing Figures 7 and 8), the information is prepared by the action divider of the microcommands of operator 5 or 6. The microcommands of operator 5 are loaded into two adjacent working registers of the FOH ALU (even and odd) information divider; even register (for example, number 14) RON is an additional code, in odd (15) RON is right. The actions of the microinstructions of operator 9 load information into the indicated registers in the opposite way: into even (14) is direct, and odd (15) is an additional divider code.

After these preparatory actions, microcommands of the 1st measure of the division are executed. Consider what are the control fields of the Microcommand Dividing. In field 5 of the PMK 20, the 3 Shift format is applied, the KCC 9 shift functions are controlled, namely the left shift of the ROH and Q registers (code 0110).

In the fourth stage, the information controlling the CMD 17 is set so that the decrement of the register-counter of cycles and the analysis of its state with transition over the state

Lcu

 0 to repeat microcommands

division, and the state R mid 0 - on the actions of the operator 12.

The first field of RJ 20 is controlled by the ALU 3 — a summation operation is performed and the received sum is transferred to the address (RON number) specified in the first field of node 13, where the dividend is contained, and the remainder is subsequently. The first field of the node 12 indicates the address (number of the RON), information in which there is a divider indicating its location in the odd ROH (in our example 15).

Node 12 emulates using the DSHA 3 address decoder, the initial single value of the zero bit of the RON number under the control of the higher bit of the shift register of the PAMN ALU 3. When PAMN ъ 0, the address (RON number) from the output of the node 12 is even (14). With

about

PAMN 1 - address (RON number) from the output of node 12 - odd (15).

Under the control of the first field, the PMK 20 ALU 3 performs the action of adding the contents of the RON (R) number specified in the microcommand, where the dividend (remainder) and the divisor are placed, in direct or additional codes,

0 previously placed in the even and odd registers RON operator 5 or 6 (Fig.7 and 8). Node 12, the emulator, depending on the values of the higher bit of RAM ALU 3 (divisible / remainder), the selection of even or odd RON ALU 3 registers, acts as operator 12 or operator 13, corresponding to known operators.

0 Simultaneously, under the control of signals, the sign of the divider (input 1), the highest bit of the dividend / remainder (input 3) in the HDF 24 emulates the low order bit of the Shift Left KSS 9 7 function.

5 so that the actions of operators 14,16 or 14, 17 are executed.

The algorithm for performing actions on the formation of an even-numbered one corresponds to that described in Table 4 and is determined by soldering PSD 24 (Fig. 2), which is a multiplexer with organization 1.

The address decryption device 24.1 represents the logical side of the OR. The emulation of the low-order bit of the shift function (4th bit of the RMK 20) is performed in accordance with Tables 6 and 7 of the input and output signals of the HDF 24 and LBD 24.2.

five

WITH

five

ABOUT

one

one

ABOUT

The current value of the 4th bit RMK 20

one

About About 1

one

Oh oh

one

about 1 about

1 about 1

about

one

Note. Input 1 - the value of the sign bit divider;

1915

input 2 is the value of the highest bit of the dividend; input 3 - the value of the sign of division; output is the low-order value (Op) of the Shift control function (4th digit

RMK 20).

The state of the input and output signals of LSPC 35 (multiplexer 8-1) is shown in Table 7.

Table 7

Output

Control inputs 11 I 10 1 9

Yu

About About About About

one

Oh oh

eleven

about 1

about

one

about

one

- comNote. DO-D7 mutated output signals; DO-D3 - low level signals; D1 and D2 - high level; D4 and D5 - do not commute; D6 and D7. - the current value of the zero bit of the Shift function (4th bit of the RMK 20).

During the execution of the division cycle, the decrement of the content of the cycle counter and its analysis are performed. The control is transferred to repeat its execution during the IN c loop | 0 and to perform the actions of operator 12 at the exit of the division cycle at 1 N cc cycle, | 0

It is necessary to clarify the principle of receiving and processing interrupt signal OPS 22. Node 22, during the execution of the current firmware, commands are received and memorized interrupt signals from a digital computer. Node 22 performs interrupt handling according to the priority assigned to it. The highest received interrupt signal is converted into a 3-bit vector coming from the first group of outputs of the OPS 22 to the data inputs of the hard chip board 15. Sampling by the address of the vector is resolved after the command firmware is executed at the time of loading the initial address 159A

20 sa, the next rz DSHK 16. With the second

the output group of the RMK 20 receives control of the selection and loading of the address and microcommand from three possible sources; from the fifth group of outlets of the RMK 20, with the release of DSHP 15 and DShK 16. The states of the outputs of these sources at any moment in time are as follows

that only one can be active, and the rest should be in a state of high impedance (turned off), it is possible to turn off all three sources. If from the second group of OPS 22 outputs a PEPP signal is generated over a 3-bit bus, indicating the presence of at least one interrupt, a certain switching occurs at the tristable sources of the address of the microprocessor DShP 15, DShK 16, RMK 20, and the output of the DShP becomes active 15.

The result is that

5, instead of loading the starting address of the next command from the AAD 16, the starting address of the interrupt signal of the highest priority intercepted interrupt signal is loaded.

The end of the execution of the interrupt processing firmware is again the micro-command for loading the initial address of the micro-command from the ASC 16. If there are no interrupts, the transition to the execution of the next command from command register 14 occurs.

five

Claims (1)

Invention Formula A firmware control arithmetic unit containing an arithmetic logic unit containing N computational cells, an accelerated transfer node, a bus driver, a state controller, a memory address register, two operand sampling nodes, each of which contains an address multiplexer and an address register, and a block control program containing the command register, interrupt decoder and command decoder, microprogram control node, microinstruction memory node, first microinstruction register and processing node pre data, the device data pin is connected to the information input of the command register and the first information input of the bus driver, the information outputs of which are connected to the information inputs of N computational cells, the information outputs of which are connected to the information inputs of the memory address register, the outputs of which are the device address bus, The first and second outputs of the bidirectional shift circuit of the i-th computational cell (where i is 1,2, ..., N-1) are connected to the first and second bidirectional shift inputs (1 + 1) -th deduction The first and second bidirectional shift inputs of the first computational cell are connected to the first and second bidirectional shift outputs of the state controller, respectively; the third and fourth bidirectional shift outputs of which are connected to the first and second bidirectional shift outputs of the Nth computation cell, the first, second and the third sign of the states of the first computational cell are connected to the first, second and third inputs of the conditional transition signs of the state controller, you the transfer path of which is connected to the serial transfer input of the Nth computational cell and to the transfer input of the accelerated transfer node, the group of information inputs of which are connected to the serial transfer inputs of the 1st computational cells and the output and distribution solutions of the transfer of (i + 1) -x computational cells , the first group of outputs of the command register is connected to the group of information inputs of the command decoder, the group of outputs of which is connected to the first group of address inputs of the microprogram control node, second group address inputs of which is connected with a group of outputs of the decoder interrupts invariant. the formation input of which is connected to the output of the interrupt processing node vector; the second and third groups of the outputs of the command register are connected to the control inputs of the address multiplexers of the first and second operand selection nodes, respectively, whose outputs are connected to the information inputs of the corresponding address register; 0 five 0 five 0 five 0 five connected to the controller of the state of the microprogrammed control node, the input of the device’s direct clock signals are connected to the synchronous inputs of the state controller, the microprogrammed control node, the address registers of the first and second operand selectors whose outputs are connected to the first and second address inputs, respectively, of all computational cells, characterized in that, in order to increase the speed of execution of the main commands and the command of the division operation while reducing equipment, the microcommand address register, the second microcode register, the bit control signal decoder and the private bit generator containing the address decoder and the private decoder are entered into the firmware control block, the address decoder is entered into the first operand selector, the first information input is connected to the output the multiplexer address of the first operand selection node; the output of the address decoder of the first operand selection node is connected to the write enable input address of the first node's address register; Selecting operands, the output of the microprocess control node is connected to the information input of the micro-command address register, the output of which is connected to the address inputs of the micro-command memory node, the output of which is connected to the information inputs of the first and second micro-command registers, the synchronous input of the micro-control node of the micro-commands register the memory of microinstructions, the first register of microinstructions and all the vytaktovyh signals of the device is connected to the synchronous input of the second register of microinstructions, the first The group of outputs of the first register of micro-commands is connected to the inputs of micro-commands of all computational cells, the second group of outputs of the first register of micro-commands is connected with the inputs of the processing node interrupts, the outputs of the interrupt signal of which are connected to the control inputs of the interrupt decoder, the decoder of the command and the first register of microinstructions, the setup input in 23 154 the initial state of which is connected to the device installation input, the third group of outputs of the first micro-register register is connected to the data receive control inputs, the fourth group of the first micro-command register outputs is connected to the control inputs of the microprogram node. a lot of control, the third group of address inputs of which is connected to the fifth group of outputs of the first register of micro-instructions, the pole of the group of outputs of which is connected to the input of a bus driver constant, the address input of which is connected to the information input of the memory address register, the control inputs of which are connected to the first group of outputs the second register of micro-commands and with the control inputs of the bus driver address; the seventh group of outputs of the first register of micro-commands is connected to the first group of inputs of micro-commands of control a leler of states, the second group of inputs of micro-commands of which is connected to the second group of outputs of the second register of micro-instructions, a third group of outputs of which is connected to the inputs of the decoder of the bit control signals, the first output of which is connected to the input of recording resolution of the command register, the output of the sign bit of which is connected to the first control input of the decoder private, the second control input of which is connected to the first information 59424 the input of the address decoder of the private bits generator, the second input of the address decoder of the first operand selection node, and the second output of the bit control signals decoder, the fourth and fifth groups of outputs of the second micro-command register are connected to information inputs Q multiplexers addresses of the first and second operand selection nodes, respectively, the outputs of the address registers of the first and second operand selection nodes are connected to the first and second 5 entries of the address, respectively, of all computational cells, the low-order output of the first register of micro-instructions is connected to the first, second, third and fourth informational 0 inputs of the decoder private, fifth and sixth information inputs of which are connected to the input of the logical unit of the device, the input logic zero of the device is connected to the seventh 5 and the eighth information inputs of the private decoder, the third control input of which is connected to the output of the address decoder, the private bit generator, the second information input of which is connected to the third information input of the address decoder of the first operand selector node and the second bidirectional shift input of the first computational From the cell, the output of the private decoder is connected to the input of the shift-control microcommand. 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