SU1417009A1 - Fixed-point number dividing device - Google Patents

Abstract

The invention relates to computing and can be used, in particular, in the creation of specialized information processing systems. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that in a device for dividing fixed-point numbers, containing adder 1, divisible register 2, divisor register 3, private register 4, blocks 5, 14 elements, AND element 7, counter 8, memory block II TI and block of 3 elements AND, the element OR 6, multiplexers 9, 10, delay element 12 and the group of I5 multiple divisor registers with corresponding connections are introduced. 2 ill., 2 tab.

Description

RU

№ 7 5.3

(L

oh oh

with

Rztyosits invention to computing and can be used to create special systems for information processing,

The chain of the invention is to reduce hardware costs.

FIG. 1 shows a diagram of a device for dividing fixed-point numbers (for P3); in fig. 2 is the timing diagram for the arrival of clock pulses at the device inputs (for P 3, where P is the number of quotient bits generated). The device contains an adder 1, a register of a dividend 2, a divider 3, a private 4, a block of 5 AND elements, an element of OR 6, an element of AND 7, a counter 8, a multiplexer 9 and 10, a block of 11 pa, a 12 delay element, a block of 3 Elements OR, block 14 elements AND, a group of registers 15 multiple dividers, input 16, device divider, input 17 of the divisible device, inputs 18 and 19. device constants, clock inputs 20-24 of the device, group of clock inputs 25.1-25.3 of the device, output 26 of the frequency device, younger registers 27 register 4 frequency, sign bit 28 adder 1, senior bits 29 sums torus, older bits of register 30 3 divider.

In the device, the action is performed on numbers with a comma fixed before the high-order bit. The divisor is normalized, and the conditions, 5; Xi-Y, where X is the dividend (remainder), Y is the divisor.

Previously, for all combinations truncated to (P - (- 2) - high order bits, remainder X, and divider YQ, a partial Z is obtained. Partial partial ZQ is obtained from Z by truncating it to P senior bits with preliminary addition to (P + 1) th dropable unit of discharge.

The absolute error in determining the partial quotient is equal to

Ho „-P-I Ho + yH

z f

Iq

f 2

YO

uY

, (one)

,-R

where ixi 2

The numerical value is made by the expression

uZ "2

R

(2)

From formula (2) it follows that an hour, - a partial quotient obtained in such a way, is equal to its exact value or more by a unit of the least significant bit.

At the stage of obtaining the partial bits ZQ for the corresponding X, Ye, a negative residue and a difference of 2 -Zg are obtained.

The corresponding partial quotients Z are written to the memory block at addresses X, Yg, and at addresses. (X, - Y) differences (ZQ).

Before the division cycle, the values of the partial sums of the memory divider, 5U, 7U, ..., (2 -l) Y) are formed and recorded.

In this case, the division cycle is described by the following algorithm.

Based on the analysis of the (P + 2) -hh bits of the remainder of the divider and the remainder sign, the P-bit partial quotient Z is determined; (i - cycle number).

The remainder is determined

x;

X; -2 - Z; Y, if X; b 0,

X - 2 + (2 - Z;) Y, if X,

Partial private values are corrected.

Z;

,; if X; i oh

Z; - 2 if X; 0..

(four)

five

Q

0

five

To obtain an n-bit private dividing cycle, repeat p / p times.

The device works as follows. In the initial position of the device in the adder I and the register 3 of the divider, the value of the divisor Y is found, and in the register 2 of the dividend, the value of the divisible X.

Depending on the code received at the control input of the first multi-i typelexer Y, the selection of the information input with the transmission of signals to the output is made according to the table. 1 match (see example for R 3 in Table 1), where KY (K 1, 2, ...,) is the inverted value of KY, including the sign bit.

In the () -disk cells of the memory block 11 at addresses X, (X - -Yjj) Yjj stores the pre-formed information in the form shown in Table 2. I.

In the second and fourth columns of the table. 2 respectively, the P-bit partial private code is located

Z and differences (2 -Z), and in the first and third columns - a sign. At the inputs 18 and 19 of the device are set, respectively, the constants 1010 and 0000 DL (P 3).

Preparation of the device to perform the division is as follows.

By the signal from input 20, the value from input 18 through block 5 of the elements AND and block 13 of the elements OR is fed to the control input of multiplexer 9 (Fig. 2). At the specified value (see Table I), a multiple of two divider 2U from register 3 divider is fed to information input of adder 1. The same signal is used to add the contents of adder 1 with a multiple divider 2U,

According to the signal from input 25.1, arriving at the control input of the first register of 15 multiple divisors, the contents of the adder; I, equal to 3Y, is written to this register.

Similarly, the signals from inputs 20, 25.2 and 20, 25.3 on the second and third registers 15 of the multiple divider form the values of 5Y and 7Y, respectively. Further, according to the timing diagram (Fig. 2), a signal appears at the input 24, which is used to cancel the adder J. According to the signal from input 21, the value from input 19 passes through block 14 of the AND elements and block 13 of the OR elements to the control input of the multiplexer 9.Po It (see Table I) the contents of register 2 divisible through multiplexer 9 enters the information input of adder 1 and is entered into it.

The division is as follows.

To determine the n digits of the quotient, n / p equal division cycles are performed. In the first cycle of each cycle. . (by the signal from input 22) a shift to the left by the P bits of the contents of the partial register 4 is performed, the reading from the memory block 11 of the partial partial

Z and difference 2 - Z with the corresponding signs in accordance with the address consisting of (P + 2) -x high-order bits of the remainder (the contents of the adder 1), sign bit, residual, () -highs of the divisor (register divider 3), entering on the counter 8 from the output of block 11 of the memory partial partial Zg, and

also generating a code at the control input of the first multiplexer 9, depending on the value of the signal at the control input of the second multiplexer 10, from one of the inputs of block I 1 in the form of a code consisting of the value Z with a sign O or in the form of from the difference 2 - Z with the sign J, through the chains of the second multiplex -. litter 10 and block 13 elements OR. In accordance with the code at the control input of the first multiplexer 9 on

information input of the adder 1 in accordance with the table. f the corresponding divisor code KY or KY is supplied.

In addition, the addition is made

the contents of adder 1 with the corresponding code of a multiple divisor (the next remainder X is formed).

In the second cycle of each cycle (according to the signal from input 23)

left shift mantissa residue on adder 1, the correction of partial private ZP on the counter 8 according to the rule:

2 o if the remainder is x o, oh j.

(ZQ, if residue,

as well as the entry of the corrected partial h-aktnogo younger bits 27 of the register 4 private.

35

Claims (1)

Invention Formula A device for dividing fixed-point numbers containing an adder, a divisible register, a divisor, and 40 private, two blocks of elements AND, element AND, a counter, a block of memory and a block of elements OR, the inputs of the divisible and the divisors of the device are connected respectively to the inputs of the registers of the dividend and divider, the first and second clock inputs of the device are connected respectively to the first inputs the first and second blocks of elements And the outputs of which are connected respectively with 50 by the first and second inputs of the OR block, the third clock input of the device is connected to the shift register enable input of the quotient register and the meter recording resolution input, the fourth solenoid input of the device is connected to the adder shift enable input, the sign bit output of which is connected to the first input of the AND element , outputs (P + 2) -x (p - number of forms of fyx bits of privately} - the upper bits of the adder and the divider register are connected respectively to the first and second address inputs of the memory block, the first, JBbtft output of which is connected to the information input of the counter, the output is connected to the information input P low bits of the register of the meter counter, the device divider input is connected to the set input of the adder, the information input of which is connected to the output of the first multiplexer, the control input of which is connected to the output of the block of OR elements, the third input connected to the output of the second multi jHoro, the output of which is the output of the plexer, the first and second information element OR, .- " In order to reduce hardware costs, it contains two multiplexers, a delay element and a group of 2 i divider divides registers, with the first and second clock inputs of the device connected to the first and second inputs of the OR element, the output of which is connected to the input of the addition of the adder of the adder, the zeroing input of which is connected to the fifth or five clock input of the device, the third clock input of which is connected to the third input of the OR element and to the input of the readout of the memory block, the device’s fourth clock input is connected to the second input of the AND input and, through a delay element, to the input of the receive register of the private register, the output of the AND element is connected to the enable input of 0000 The input inputs of which are connected respectively to the first and second outputs of the memory unit, the third address input of which is connected to the control input of the second multiplexer and to the output of the character bit of the adder, the output of which is connected to information inputs of registers of multiple dividers of the group, inputs of resolution 20 Receipts of which are connected to the corresponding clock inputs of the device group, the first and second inputs of the constant of which are connected respectively to the second inputs 25 of the first and second blocks of elements And, the output of the register of the dividend, the direct and inverse output of the register of the divider, the direct and inverse outputs of the registers of multiple depot groups of the group are connected, respectively, to the information inputs of the first multiplexer. Table 1 1Y 2y 3Y 4y 5y 6Y 71 Y 2y 3Y 4y 1101 1110 1111 20 75.1 2Q 25.2 20 DZ 2 21 2 3 22/5 22/5 O L i L P P fl O O (O O I P Editor E. Kopcha Compiled by A. Klyuev Tehred L. Oliynyk Order 4067/48 Circulation 704 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Rausch “sa nab. 4/5 Continuation of table 1 5Y 6Y 7y table 2 i Fie.2 Proofreader V. Booth ha Subscription