SU1667057A1 - Device for dividing - Google Patents

Abstract

The invention relates to digital computing and is intended for use in universal and specialized computing devices. The aim of the invention is to reduce hardware costs when implemented in a device for dividing operational detection of computation errors. Rapid detection of computation errors consists in performing a re-computation with shifted operands and comparing its results with the results of the first computation. In this case, the device for dividing is characterized by temporal and instrumental redundancy. The goal is achieved by the fact that when re-calculating, the divisor shifts one digit to the right, the dividend shifts by two bits to the right. Such an organization of operand shifts can reduce hardware redundancy during device implementation. The device for dividing allows to detect all computational errors in the dividing matrix with restoring the residual, if its malfunction is limited by the malfunction of one cell of the matrix. The device includes computational cells 6, elements NOT 7, registers 8, 10 of frequency and residual, comparators 9, 11 of particular and residual, element 12 OR, inputs 1.1 - 1.N divider, inputs 2. (- M + 1) - 2.N divisible, outputs 3.1 - 3.M private, outputs 4.1 - 4.N residual, output 5 of the control for the correctness of calculations, the first and second control inputs 13, 14 of the device. 2 Il.

Description

The invention relates to digital computing and is intended for use in universal and specialized computing devices.

The purpose of the invention is to reduce hardware costs when implemented in a device for dividing online detection of computation errors.

Figure 1 shows a functional diagram of a device for dividing; figure 2 - timing diagram of the device.

In Fig. 1, the inputs 1.1-1.p of the device divider, the inputs 2 (-t + + 1) -2 of the divisible device, the outputs 3.1-3.t of the private device, the outputs L-.p of the device remainder, the output 5 of the calculation of the calculation accuracy , computational cell 6, element NOT 7, register 8 private, comparator 9 private, register 1 (1 residue, residual comparator 11, element OR 12, first and second control inputs 13.1 of the device (clock inputs of the private and balance registers), the first, second, and third information inputs 15–17 of the computational cell 6, the first and second outputs, 18.19, respectively; 6-inflammatory cell, a control input 20 of the cell computer 6.

The computational unit cell 6 is described by the following system of equations

z х ® a (y (), and хЬ 4 vh

ABOUT

where x is the value of LMOR KOR values at the input I G5; y - at the entrance Ib; B - at the input I; a - enter I1;

five

0

five

0

five

0

45

50

five

z - exit 18; and - at exit 19;

computational cell 6 devices for dividing.

The device for dividing allows to detect any calculation error if the failure of the device is limited by the failure of one computational cell or one element NOT generating a bit of a private one.

The dividing device works as follows.

In order to detect calculation errors, the calculations are carried out. In the first calculation, the dividend X, the divisor Y. R recalculate the dividend, the divisor Y-2. The first calculation starts from the moment of installation of the divider bits at the inputs 1.2-1.p and the bits of the dividend at the inputs 2. (- t + 3) - 2.p, and at the inputs 2 / (- t + 1), 2 | (( - that + 2), 1.1 in the first calculation signals O are given.

Through the transition time Tb in the division matrix, the quotient

and the remainder of the first calculation is set, respectively, at the output of the private matrix and at the first information outputs of the computational cells of the penultimate series and at the information inputs of the private and residual registers connected to them. At the moment of time T, the inputs 13 and 1 of the device are fed with recording pulses, which are used to write to the registers of the quotient and the remainder, respectively, of the quotient and the remainder of the first calculation. At the end of the recording, the division matrix is ready to be recalculated. Recalculation starts from the moment the divider bits are installed at the inputs of l.l-l. (N-l) and the bits of the divisible at inputs 2, (- n + 1) - 2, (n - 2), and at inputs 1.p. 2.p, 2. (p-1) in the recalculation, the signals O are given.

sixteen

After the time Tg, the transition process in the division matrix, the quotient and the remainder of the re-calculation are set at the outputs of the quotient and the remainder of the division matrix, respectively, and at the inputs of the first operands of the quotient and residue comparators, the inputs of the second operands of which are shifted respectively the bit to the right is partial and two bits to the right is the remainder of the first calculation.

After the time T of the total delay of the signals in the comparator and the element

Claims (1)

OR output 5, a signal appears indicating the correct operation of the device, if the results of the two calculations coincided, or a calculation error, if the results of the calculations did not coincide. Invention Formula The device for dividing, containing the matrix n m (m + 1) of the computational cells, (where n-1 is the divisor size, n + m - 2 is the divisible bit, m is the quotient of the quotient), m + 1 elements are NOT, registers of private and residual, comparators of private and residual, with the first information input (i, j) -u of the computational cell (i 2, ..., n, j 2, m) connected to the first output (i-1, j -1) -th computational cell, the first information inputs of (K, 1) -x and (1,1) -th computing cells (where, ..., t + 1) are connected to the inputs of the corresponding bits of the divisible device, the second information input (i-1, l) -x and (n, 1) to the computational cells are connected to the inputs of the corresponding bits of the device divider, the second information input (n, j) -u of the computational cell is connected to the input logic five 0 5 5 0 / The third information input (i,) - n of the uygLITRP cell is connected to the second output of the (i-1, 1) -th computational cell, the second output of the n-th computational cell of the 1st row is connected to the input of the 1st of the NOT element and with the control inputs of all computational cells of the 1st row, the control inputs of the (I, 1) computational cells are connected to the inputs of the logical zero of the device, the outputs (jl) -x of the elements are NOT connected to the information inputs of the private register, the outputs bits of which are connected to the inputs of the bits of the first operand of the comparator private, the bits of the second operand of which are connected to the outputs of the x-elements of HE, the first outputs (i-1, m) x of the computational cells are connected to the information inputs of the remainder register, the bits of which are connected to the bits of the first operand of the comparator private, the bits of the second operand of which are connected to the outputs from the first to (n-2) -th computational cell (m + 1) -and lines, which are due to the fact that, in order to reduce hardware costs, the device contains the element OR , the first and second inputs of which are connected to the output With the signals of the private and residual comparators, respectively, the output of the OR element is connected to the output of the control of the correctness of the computations. The inputs for enabling the recording of the registers of the private and the remainder are connected to the first and second control inputs of the device; the remainder register is connected to the outputs of the remainder device. st "si € S V s "n vl . ,one NJ one J hS-  ,: