SU911520A1 - Device for squaring n-digit numbers - Google Patents

Description

(S) DEVICE TO INCLUDE p-BIT NUMBERS IN SQUARES

I

The invention relates to computing and can be applied in specialized computing devices.

It is known a device for raising binary numbers into a square, containing a counter, the counting input of which through an AND element is connected to the input of a block of OR elements, a recurrent shift register, a block of modulo two adders, the first and second blocks of AND elements

In the device, the initial number is converted into K pseudorandom sequences and their subsequent processing is implemented, which determines the low speed of the device and performance, as well as the low reliability of the calculations due to the inability to implement simultaneous control of the computational process,

Of the known devices, the closest to the proposed technical entity is a device containing (p-1) a group of elements And i elements in each (where i is the group number), adder 2.

A disadvantage of the known device is the low reliability, due to the fact that during the computational process (the transition process in the circuit) there is no parallel control of its correctness.

10 performance, and low productivity.

The purpose of the invention is to improve the reliability and performance of the device for the construction of n-discharge

15 numbers in a square. The above objective is achieved by the fact that in a device for raising n-bit numbers into a square, containing (n-1) a group of elements AND

20 i elements in each (where i is the group number (i 1, ... n-1) and adder, the comparison scheme, the OR element, half adders and modulo adders. 39 are two, and the AND elements of the groups are combined into a matrix, each the column of which is the i-th group, the first inputs of the elements AND of each i-ro column of the matrix are combined and connected to the (1 + 1) -th digit of the input device code, the second inputs of each i- are connected to the iy discharge of the device input code The element ro and all columns of the matrix, the first input of the i-ro bit of the comparison circuit and the first input of the i-ro half-adder, the outputs of the element a AND each j-th row of the matrix (, 2, ... n-3j are connected to the input of (j + 1) -ro bit of the adder, the output of each 2i-th bit of which is connected to the second input of the i-ro half-matrix and the first input of the i-ro adder by mode / cho two, connected by its second input to the OUTPUT i-ro half-adder and the corresponding 2i-My bit output-of the device code, and the output to the second input of the corresponding bit of the comparison circuit, the output of each (2i -1) -ro bit of the adder is connected with (2i-1) -M bit of the output code, the highest bit of which is connected to the output of the OR element, to the first and the second inputs of which connect the transfer outputs of the adder and the floor of the adder of the previous bit, and the transfer output of each (i + 1) -ro half-adder is connected to the input of the adder of the next bit: a, (2n-1) -th and 2n-th the output code is connected respectively to the logical zero bus and to the nth bit of the input code. The drawing shows a diagram of a device for squaring n-bit numbers for the case when the information is represented by binary bits. The device contains a matrix 1, an adder 2, a comparison circuit 3, an element OR 4, a half-adders 5, one-bit subtractors 6. A matrix 1 of. elements And 7 is made of (n-1) -th column, each i-th (, 2, ... n-1) column which is shifted relative to (i-l) -ro by one bit down. The adder 2 is made of one-bit adders 8. Each i-th bit of the comparison circuit 3 is made of the addition element 9 modulo two, the output of which is connected to the i-th input of the OR 10 circuit. X in the expression previously presented in bit form. G ° lfc | Ll5il-V- | 4 | 11 ... -discharge vectors representing the bit image of the numbers X and Y, respectively: the bit matrix representing the bit image of X with n 3. The expression (1) in expanded form with n 5 is represented as 5 and forms the basis of the parallel operation algorithm of the proposed device. To increase the reliability of the device, the paths of the implementation of the parallel office of the computational process (i.e., the parallel verification of the correctness of the squaring operation) and increase the productivity by fixing the time of the operation (i.e., the transient process in the circuit) are resolved expression (2) with respect to signs of X bits of the vector X 1 2 ia V- (XX.p) 4 2i 14 4 A 44 Y- (XX + XX f.,) VS XV - (XX + L 44 L XV - (XX + „- - (XX) yS (444 Q. where the transfer value (in expression (2) and the youngest to the highest order, i.e., sixth, fourth and Ora respectively:

e l5 34 a 5 6

1 11 U

s XX; s XX + XX + p

,

The operation of determining the values of X of the vector L from expression (3) is realized on the basis of the proposed Expression, underlying the operation of each bit of the subtractor

where φ is the sign denoting addition modulo two.

In accordance with expressions (3) and (4), expressions (2) can be written as

V

V

five

V to P

S vectors in the process of calculating their components.

Consider the above for a specific example of the value, 90625 and, accordingly, the result of the calculation is 0.8212890625 or in the bit form

 -P | 1I1oP1

F I1CHOI | o | D | Cho | op

in accordance with the expression (5), the computational process of finding v

Torah A

Claims (1)

 V can be represented as 20 Thus, by implementing the expression (5), we obtain the square of the value of Islam X, and by implementing the expression C) on the basis of the expression V. (5), we obtain the vector l, comparing which with the given vector X, we determine the correctness of the construction of the square and the time of its completion, with the value of times; 1-Shm2 V.V, V, Viwierer vector. 1466G72T47 Gu and bits S, S, S, S.BeKTOpaSi: | SiS | s | s is determined in the process of calculating V9 V of the square of the number XV, and the difference VV of the vectors V and S (i.e. control of the computational process) is implemented in parallel with the computational process of squaring by razrnodnogo subtraction of the vector 79 n 4 6 where S, S, S О, S, and the process of implementing parallel control calculations based on the expression C), respectively, 1 1 F o 1 1 ® o X 1 о® 1 i 1.2,3. о о Ф о The operation of the proposed device is carried out as follows. V When the number 11 is fed to the input bus, 1) 0 | G JB a transient process occurs, after which the output of the second, fourth, sixth and eighth bits of the one-bit totalizers 8 cyfwaTopa 2 results in the output | g O, o , S 4, 0 | The second inputs of the one-bit subtractors 6, respectively, arrive, and the values of o are formed at the outputs of the half-adders 5. T V bits of the desired vector Y are fed to the first inputs of one-dimensional subtractors 6, in which the difference between the input components 1 .. realts and S is realized. At the outputs of one-bit subtractors 6, the values of bits X 1, X 4V 1 are formed X 1, X О vector X "each X i component of which is fed to the second input of the i-th bit of the addition element modulo two 9 comparison schemes 3, the first input of which is respectively X i -component of the specified vector l i-ro bit input bus. In comparison scheme 3, V compares a given vector X with the vector X computed during the solution and at the output of the OR 10 scheme of the comparison scheme 3 produces a signal that signals that the squaring is done correctly and the transition process is completed. device | You can serve the following number. The use of the new elements of the comparison circuit, the OR element, half-adders and one-bit calculators — distinguishes the proposed device from the known, as the proposed device significantly increases reliability due to the fact that the device is monitored in parallel with the computing process. in Vfl V, the process of calculating XV calculates the h vector S, and the difference between V and S is the parallel control of you, the numeral process (starting with the youngest and ending with rshim discharge); In addition, the productivity of the proposed device is significantly increased due to the fact that at the output of the comparison circuit 3 a signal of the end of the transient process is produced in the circuit and the device can immediately start for the next cycle of operation. Otherwise (when the signal of the end of the transient is not produced) the device will be in the standby mode until the time period of its operation is closed, after which it starts for the next cycle, and since the duration of the transient process when different numbers are fed to its input is different long enough idle. Claims An apparatus for squaring n-bit numbers containing (n-1) a group of elements And i elements in each group (where i is the group number (i 1 .... | -1) and the adder, o l and ch yu e. so that, in order to increase the reliability and productivity, it additionally contains a comparison circuit, the element OR, the semi-sum, and moduli two moduli, the elements of the AND groups forming the matrix, the first inputs of the AND elements each d-th column of which is combined and connected to () the unit's input code bit, to the iy unit's unit code slot Triplets connect the second inputs of the i-ro element AND all columns of the matrix, the first input of the i-ro bit of the comparison circuit and the first input of the i-ro bit of the circuit