SU1520512A1 - Matrix-type squaring device - Google Patents

Abstract

The device is related to computing and allows calculating the square of the argument and controlling the calculations by unresolved result codes. The device contains And 1 cells of the matrix, defining all possible conjunctions of the values of different argument bits, adders of 2 matrix cells, calculating the square of the argument by finding the weighted sum of the conjunction values and the argument bits. The device also contains a modulo seven convolution block 3, determining the remainder of dividing the result code by seven, a modulo convolution block of two 5, and the element OR 4. NOT 6 AND ELEMENT AND 7 ON SIGNALS FROM THE OUTPUTS OF BLOCK 5 AND ELEMENT 4 IDENTIFYING CODES RESIDUALS 3, 5 AND 6, INDICATING TO UNRESOLVED RESULTS CODES AND ACCORDINGLY TO THE WRONG FUNCTIONING OF THE DEVICE. 1 IL.

Description

one

(21) 4401437 / 24-24

(22) 03/31/88

(46) 11/07/89. Bul P 41

(71) Odessa Polytechnic Institute

(72). Drozd, E.L. Pauline, A.M. Romankevich, V.N. Valuisky and S.A. Not sterenko

(53) 681.325 (088.8).

(56) USSR Author's Certificate No. 842804, class G 06 F 7/552, 1979.

USSR Author's Certificate No. 1439583, cl. G 06 F 7/552, 1985,

(54) MATRIX DEVICE FOR INCLUSION IN SQUARES

(57) The invention relates to computing and allows calculating the square of the argument and controlling the calculations for unresolved

result codes. The device contains the elements And 1 cells of the matrix, determining all possible conjunctions of the values of different bits of the argument j-a, adders of 2 cells of the matrix, calculating the square of the argument by finding the weighted sum sign 1 | conjunctions and bits of argument. The device also contains a modulo seven convolution block 3, determining the remainder of dividing the result code by seven, modulo two convolution block 5 and the element OR 4. The HE element 6 and the AND 7 element identify the residual codes from the outputs of the block 5 and element 4. 3, 5 and b, indicate unresolved result codes and, accordingly, the device malfunction, t Il.

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The invention relates to computing and can be used in specialized computers.

The purpose of the invention is to increase the reliability of the operation.

The drawing shows a block diagram of the device for.

The device contains elements AND 1, adders 2, block 3 convolutions modulo seven, elements OR 4, block 5 modulo two modulo, element NOT b and element And 7,

; The device works as follows.

Operand bits are fed to the devices. In this case, the first bit of the operand is fed to the first output of the device, the second output of which constantly takes on the value of a logical zero. In addition, the first bit tp is fed to the first inputs of the And 1 elements of the first column, the second inputs of which receive the subsequent bits of the 2pj operand 3p, 4p, 5p, and 6p, respectively. At the output of the elements And 1 of the first column are formed of the conjunction 1p 2p., Tp; 3p, 1p-4p, 1p-5p and Tr-br, which Post

go to the second inputs of the corresponding adders 2 of the first column. The transfer signal spreads through the first inputs and outputs of these mathors 2, as well as the adders of the 2 subsequent columns (except for the first input of the first adder 2j which, as in the subsequent columns, is zeroed, and as well as the first output of the subsequent nth adder 2, from the output of which, as in the second column, the transfer signal arrives at the third input of the fourth adder 2 of the next column).

The third inputs of the even adders of the first column are zeroed, and the third inputs of the first, third, and fifth summers 2 of the first column receive bits of the operand, respectively 2p, Er and 4p.

In this case, the third and fourth bits of the result are determined, received from the second outputs of the first and second adders 2 of the first column to the third and fourth codes of the device. The sum signals from the second points of the third, fourth, and fifth adders 2 of the first column are received, as are the sum signals from the corresponding adders 2 of the second column0

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ca, to the third inputs, respectively, of the first, second and third adders of the next column. Elements I and 1 of the second column are calculated in accordance with the bits of the operand conjunctions 2p-3p, 2p 4p5 2p 5p 5 2p-6p and 4p 5p that are input to their inputs, which are fed to the second inputs of adders 2 of the second column. The third input of the second adder 2 of the second column receives the bit operand 5p.

In this case, the fifth and sixth bits of the result are determined, coming from the second outputs of the first and second from matrices 2 of the second column to the fifth and sixth outputs of the device. Elements And 1 of the third column are determined in accordance with the bits of the conjunction operand Zp-4p, Zp-Zp, Zp-6p, 4p6p and Zpbr set at their inputs, which are fed to the second inputs of the corresponding sum-TOROV 2 of the third column. The third input of the first adder 2 of the third column receives the 6p operand bit. The following bits of the result are determined from the second outputs ci MMaTopa 2 of the third column and the first output of the fifth adder 2 of the third column, respectively, at the output of the device from seventh to twelfth.

- In addition, all bits of the result are received respectively at the inputs of the convolution unit 3 modulo seven. In this case, block 3 determines the remainder of dividing the result by seven. The residual code goes to the inputs of the element OR 4 5 as well as to the inputs of block 5, the convolutions modulo two. Block 5 takes a single value when an odd number of units in the code of the remainder; This value is inverted by the element NOT 6 and sets the output of the element AND 7 to zero at the first input. At the second input, the AND 7 element is set to zero with a zero residual code, the detected element OR 4. Thus, all residual codes having an even number of ones other than zero, will determine the output of the AND 7 element, which is the control 1M output of the device single value.

A correctly calculated result of raising the operand to a square cannot have a residual code with an even number of ones, different from zero.

therefore, when the device is working properly, its control output assumes a zero value, and the occurrence of a single value at the control output of the device indicates its malfunction.

Claims (1)

Invention Formula A matrix squaring device containing NOT and AND elements, as well as a matrix of p / 2 column cells and n-1 rows, where n is an even number, operand width, each cell containing an adder and an And element, the first output of the adder The i-th row (, p-2) of each column is connected to the first input of the adder (1 + 1) -th row of the same column of the matrix, the output of the element AND each cell is connected to the second input of the adder of the same cell, the first output of the adder ( nt) -ft of the row j-ro of the column (, p / 2-1) is connected to the third input of the adder (n + 2) -th row (j + 1) -ro of the column, the second input of the adder of the i-th row (, n-1) of the th column is connected to the third input of the adder (1-2) -th row (j + 1) -ro of the column, the first inputs of the elements And the first n-1 rows of j-ro column (j 1, p / 2) are interconnected and connected to the j-ro input of the operand of the device, the second input of the element AND the 1st row of the j-ro column (, ni) is connected to the input (j + 1) -ro the device operand bit, the first inputs of the AND elements of the last (jl) -x rows of the j-ro column (for j 1) are interconnected and connected to the input (n / 2 + j) -ro of the device operand, the second input of the AND element 1st row of j-ro column (, n-1, j 1) oedinen ten 15 20 25 thirty 35 40 45 126 with the input (j + in / 2) -ro bit opera: - yes devices, the third input of the adder (2j-1) -th row of the first column is connected to the input (j + 1) -ro bit of the device operand, and the third inputs the adders of the first rows of the first column and the first inputs of the adders of the first rows of all columns are connected to the input of the logical zero of the device, the third input of the adder (n-1) and the rows of the j-ro column (j 1) is connected to the input (j + nV2) -ro bit Yes, the device operand, the first and second device outputs are connected respectively to the input of the first bit of the device operand and the logical zero input. devices, the second outputs of the adders of the first and second rows of the column are connected to (2j + 1) -My and (2j + 2) -My to the inputs of the device, respectively, the second output of the adder of the 1st row P / 2-nd column is connected to (1 + n a) -gm output of the device, the 2nth output of which is connected to the first output of the adder (p-1), and the rows of the D / 2th column, the output of the element is NOT connected to the first input of the AND element whose output is the control output of the device characterized in that, in order to increase the reliability of the operation, a modulo seven convolution block, the OR element and the block modulo two convolutions, the information outputs of the device are connected to the inputs of the convolution unit modulo seven, the first, second and third outputs of which are connected respectively to the same inputs of the OR element and the corresponding inputs of the convolution unit modulo two, the output of which is connected to the input of the HE element, and the output of the element OR is connected to the second input of the element I.