SU1179367A1 - Device for solving set of linear algebraic equations - Google Patents

Abstract

DEVICE FOR SOLUTION OF LINEAR ALGEBRAIC EQUATION SYSTEMS, a scientific research institute containing a matrix with PP size of registers of coefficients, m shift registers of unknowns, c shift registers of free members, P adders ( that, in order to increase speed, the first and second matrices of the AND-AND groups of the AND elements and the counter are entered into it, the first inputs of the AND elements and the counter, the first inputs of the AND elements (A, p-th groups of the first and the second matrices are connected, respectively, with direct and inverse outputs (.1,) of the matrix coefficients register, 4 tj-i t information input of the shift register of free members connected to the output of the 1st adder, i 1, п, inputs - the adder is connected to the information input of the i-ro shift register of free members and with the corresponding outputs of the elements and groups of the t-th rows of the first and second matrices, the output of the higher bit of the ith shift register of free members is connected to the input of the first junior bit of the i th shift register is not known and the second inputs of the elements And groups of the t-th columns of the first and second matrices, the direct output of the sign bit of the n-th shift register of free members is connected to the third inputs of the elements And groups of the 1st columns of the first (L matrix, the inverse output of the sign C bit -GS of the shift register of free members is connected to the input of the second least significant bit of the i -th shift register of unknowns and the third inputs of the elements AND groups of the second matrix of the second matrix, the forward clock pulse generator. connected to the write inputs of the shift M registers of free members and with the shift inputs of the unknown registers, the inverse output of the clock generator is connected to the shift inputs of the shift registers of the free members and with the counter input of the counter, the overflow output of which is connected to the clock pulses.

Description

The invention relates to computing and can be applied in the construction of specialized and problem-oriented processors for solving systems that are linear to algebraic | binary notation (SLAE) in binary number system. The purpose of the invention is to increase fastness. The algorithm for solving a SLAE of the form 1) j, i l, n. 21 a ;; V: ohm is represented digit-by-digit by the method as follows: 1 C "m-1-PE (eG)) H.) Jo. M with i-j. .К40 сС f-b;,; cb, or for the direct structural implementation in the proposed device in the form

,) j4 (-sign ()) Oh, if art.

. "10 G

1, if Art. Diff.

at

(3)

° HE-; g-.

(6)

tj - e If 2- “to

Xpexi Z-V

J krO J

i jHTn,. bVGfO, l $,

xl. e {1, 0 (7) The condition for the transition to the (K + 1) -th step is the fulfillment of the relation., 5 | e,. . (4) Thus, the transition to the next step is realized if, at this step, the value of caddy delay is reduced by at least two times, i.e. high bit in free member registers is zeroed. A guarantee of a one-off reduction of the SLAE level is the observance of the convergence condition, which for iterative processes is estimated by the following relationship "m. but; Oj.i The fidelity of the figures obtained at each step in the values of the roots is guaranteed by condition (5). All the coefficients, free terms, and the sought-after roots for a VLAU SLAE (1) are represented by regular fractions and are specified in the positional number system with a 2 p-bit base of symmetric komtsy in the form

b; - to the registers of free members

The drawing shows the structure-h shift registers 3 free

on the device diagram. 55 members, n adders 4, generator 5

The device contains a matrix of size-clock pulses, bus 6 records

rum pn registers 1 coefficients ,. coefficients, bus 7 records of the free shift registers 2 unknown terms, output bus 8, the first and second matrix of the size of an np of groups of elements And 9 and 10, respectively, with Getchik 11, the bus 12 of the initial installation. Since the information recorded in registers 2 at each step (namely, the bits of the unknowns) has a sign, and the coding of characters in the binary number system is carried out as follows: - - 0; + - 1, then the distinctive feature of these registers from the rest is only the doubled magnitude. The adder 4 is structurally made according to the combinational circuit and has (n + +1) p-bit inputs. Calculation of the SLAE root values with the required accuracy (p bits) in the device is performed until the transfer signal of counter 11 appears. This signal, when the counter reaches the value of p, blocks the operation of the clock generator 5. The capacity of the counter thus uniquely determines the accuracy (the number of bits in the values of the roots). The device works as follows. After writing to registers 1, the coefficients of the solved SLAE are set by us and the bus 11 is set up by the signal on bus 12, counter 11, i.e. transitions to the state of the output transfer. This allows the clock generator to be started. The first positive front of the pulse from the direct output of the generator synchronizes the recording from the bus 7 to the registers of 3 free members and produces an empty shift in the registers 2, because before the start of work the registers 3 were empty, i.e. the most significant bit was O state. This zero state is also provided without prior zeroing, since after termination of the solution in the device of any previous SLAW, by condition (4), the old bit is reset. The first positive front of the pulse from the inverted output of the generator 5 shifts the values of free members by one bit to the left, thereby entering the first significant bits of the free members for analysis, setting the inputs of the registers 2, controlling the corresponding groups of elements And 9 and 10. The ND over the entire process of computation over the time that passes between the occurrence of positive fronts from the direct output of generator 5, is written to registers 3, shifted in registers 2, and after equal lengths positive pulse from the forward output of the clock pulse generator - shift in registers 3. During the time between the positive fronts from the inverse and forward outputs the result is guaranteed on the codes of the adders 4. In addition, a positive front from the inverse output of the generator 5 connected to the counting input of summing counter 11 is added to its contents. After the appearance of 1 at the transfer output of the counter 11, the operation of the clock pulse generator is blocked. The calculation time of the n-th SLAE root order with p significant binary digits is determined as follows: C.Cj-.p,

Claims (1)

DEVICE FOR SOLVING SYSTEMS OF LINEAR ALGEBRAIC EQUATIONS, NII, containing a matrix of size η · η coefficient registers, P shift registers of unknowns, And shift registers of free terms, P adders (η is the order of the system of linear algebraic equations) and a clock pulse generator, characterized in that, in order to increase performance, the first and second matrices of size L · P of the groups of elements And and the counter are introduced into it, the first inputs of the elements And and the counter, the first inputs of the elements And (ί, J) -th groups of the first and second matrices are connected, respectively, with direct and inverse outputs (i, j) -ro of the matrix coefficient register, ί, j ~ ",, information input of the nth register of free members is connected to the i-ro output of the torus, ”= 1, p, the inputs of the 5th adder are connected to the information input of the i-ro shift register of free members and with the corresponding outputs of the elements AND groups of the tth rows of the first and the second matrix, the high-order output of the) -th shift register of free members is connected to the input of the first low-order bit of the> -th shift register of unknowns and with the second inputs of the elements And groups of the 1st columns of the first and second matrices, direct output of the sign bit of the η -th shift register liberties terms is connected to the third inputs of the elements AND groups of the ΐ -th columns of the first matrix, the inverse output of the sign digit of the 1st-hs shift register of free members is connected to the input of the second lower order of the tth shift register of unknowns and the third inputs of the elements AND groups of the 5th columns of the second matrices, the direct output of the clock generator is connected to the recording entries of the shift registers of the free members and to the inputs of the shift of the shift registers of unknowns, the inverse output of the clock is connected to the inputs of the shift shift registers free members and with the counter counting input, the overflow output is connected to the stop input of the clock. 1 1179367