SU370605A1 - DEVICE FOR READING - Google Patents

Description

one

The device relates to the field of automation of computer technology and can be used in the implementation of technical means of digital automation and specialized electronic computing machines.

Devices for subtracting numbers represented by codes with arbitrary bases are known, comprising two adders and logic circuits. The implementation of the subtraction is replaced by the addition of diminution with the additional code of the deductible. The first of the adders serves to add the operands and carry, and with the help of the second one introduces a correction code. However, using these devices to directly subtract the numbers represented by the combined codes in binary coding of numbers In pipelines, especially with heterogeneous bases, is difficult, since it is time consuming to get extra deduction.

The proposed device differs from the known ones in that the "OR circuit" is introduced into the transfer circuit of the first sum of the mattress, the other input is connected to the single pulse bus, and the output is connected to the input of the delay circuit; transfer output of the first adder through the circuit "And connected to the other output from one of the bus reference pulses connected to the input of the key, the other two inputs

are connected to the bus; new binary codes of the base of the counting in groups and another bus of the reference pulses, and the key output is connected to the second input of the second adder. The transfer output of the adder is connected via a sequential but connected circuit, a delay circuit, a delay circuit, and an OR circuit connected to its third input, and the second inputs of the OR circuit and the Ban circuit are connected to the sign change buses and the second line of support pulses, respectively. This allows direct subtraction of the numbers represented by combined codes when binary coding numbers in groups and an arbitrary number of bits in them.

The drawing is a block diagram of the proposed device.

The device contains a one-bit binary adder 1, the output of which carries through the OR 2 circuit and the delay line 3 is connected to one of its inputs. In addition, the transfer output of the adder 1 is additionally connected, nadrimer, to one of the inputs of the Matching Circuit AND 4. To the other input, the corresponding (control) pulses (OI1) are fed to the corresponding times. The output of the sum of the adder 1 through the delay line 5 is connected to one of the inputs of the second one-bit binary adder 6. On the other

the input of the adder 6 serves the binary codes of the bases of the counting in groups (giv), via key 7. The output of the circuit "I 4 of the head with the key-off input is 7, and it is turned on by other reference pulses (OI) . The output of the transfers of the second adder 6 is connected to its third input, through the prohibition scheme of 8 transfers between groups, delays 9 and the collective scheme "OR 10. The second reference pulses (OIa) are fed to the prohibiting input of the prohibition scheme, and the free input of the scheme" OR 10 - the signal of changing the value of the sign bit of the result (Hazn) - The output of the subtractor is the output of the sum of the last binary adder 6.

The device works as follows. A single pulse (ROO) is fed to the input of the OR 2 circuit, which is delayed by the delay line 3 and fed to one of the INPUTS of the one-bit binary adder 1. At the same time, the lower two bits of the combined The codes for decrement and subtraction, for example, the values of binary bits in Tpyliinax for the deductible must 1 be pre-inverted. Following the low-order bits, the following, aging, reduced and subtracted bits, as well as transfer pulses from the addition of the previous bits passing through the same, cut the “OR 2 and line delays 5.

Thus, the listed elements (nodes) provide the addition of a decrementing with a bitwise AI-version of the subtracted and an additional unit according to the simple binary addition rule, i.e., without taking into account the division of the combined code into groups of binary bits, within which the score must be produced on a given basis ( limit). However, such an addition cannot give the correct result directly in the used number system. In order to correct it, the presence of transfer pulses between groups is revealed using an AND 4 matching scheme, one input of which is connected to the transfer output of the adder, and reference (control) pulses (OHi) are supplied to the other at the appropriate time. In the case of the presence of a transfer pulse from one group of binary bits to the next result, the addition in it is equal to the required difference. If it is absent, the result from the first addition in this group requires correction. In the proposed subtraction device, the correction of groups is performed by adding the corresponding binary code of the base (limit) of the account and prohibiting the transfer from the data group to the next using another binary adder 6, in the hyphen chain of which the prohibition scheme 8 is included. the input includes a switch 7 serves other "porous (control) pulses (OI2). They determine the moments of the prohibition of transfers and preparation of the key 7. If the output of the AND 4 scheme is a pulse, indicating the presence of a transfer to the next t, ruppu, the key 7 is closed, interrupting the flow of the account base code to the input of the last adder 6. It should be noted that the equality of the base (limit) of the account in group 2 to any integer degree (2) the result of the first addition in it corresponds to the desired difference and does not require additional corrections. Therefore, the submission of the code of such a basis to the input of the key 7 should be omitted. In order to ensure the addition of the base code and the corresponding bits of the first sum, the receipt of the last ones at the input of the adder 6 is delayed (for the time of detecting the presence of a transfer to the next group) using the LIIII delay 5. When using a number system with heterogeneous bases

bills this delay is determined by the maximum number of high-order bits in the groups requiring correction. So, for example, for a time counting system encoded by groups of binary bits, we get:

For minutes. . or 1010

For ten years

minutes ... 6 or 110

For hours. (72 24 or 11000

Comparing the recordings of the accounts (O limit; B) of the account (o, gi, and dg) it is easy to see that for such a system it is sufficient to delay the code of the first sum by three frequencies in the sequence of bits, since the others do not require corrections.

The proposed subtraction device can also be used to translate an additional combined code into direct or reverse. It’s enough to file

This code is 1 at the input of the adder 1, having previously measured all its bits in groups, including the sign one, to subtract (from zero) in the described way and add a unit (Run) at the moment of arrival

the value of the sign bit at the input of the second adder 6.

The operation of the subtraction device does not change if the circuit "OR 2 and the delay line 3 are interchanged, but the impulse (Roo) in this case must be supplied simultaneously with the submission of the least significant codes. The “AND 4” matching scheme can be replaced by any other scheme for detecting the presence or absence of transfers between groups, but in the last

In this case, it is necessary to swap the on and off inputs of the key 7 and coordinate the arrival time of the pulses on them. The prohibition scheme 8 may be replaced, for example, by a coincidence scheme permitting transfers

inside groups. The “OR 10” scheme can be transferred to the input of the key 7, since the sign bit does not require correction. Finally, key 7 can be replaced, for example, with a register into which the base code is written.

bills or just his significant bits when

the absence of carries from any group of binary bits to the next.

Subject invention

A device for subtracting numbers, containing a double adder, two input operands and a transfer input, the output of which — through a delay circuit — is connected to the first input of the second adder, logic circuits and a key, characterized in that, in order to enable the subtraction of numbers, represented by consecutive combined code with binary coding of numbers in groups and an arbitrary number of bits in, the input transfer bus of the first adder is connected via the delay circuit with the OR circuit, the associated input s with the output of the transfer of the first adder and with a single pulse bus, the output

transferring the first adder via the ' scheme associated with one of the reference impulse buses is connected to the key input, the other two inputs of which are connected to the bus of the binary account base codes in groups and the other bus

reference pulses, and the output of the key is connected to the second input of the second adder, the transfer output of which through the series-connected prohibition circuit connected to the second bus of the reference pulses, the delay circuit

and the OR circuit, which is connected to the bus with a change of sign, is associated with its third input.

Quijiad

sign