SU1499335A1 - Adder-accumulator - Google Patents

Abstract

The invention relates to computing, and can also be used in oscillators and digital frequency synthesizers (in particular, in fractional frequency synthesizers). The purpose of the invention is to expand the scope of use due to the possibility of use in digital frequency synthesizers. The accumulating adder contains a combinational adder 1, a register 2, a memory block 3, a multiplexer 4, an information input 5, a decoder 6, a counter 7, a clock input 8, a control block 9, a synchronization block 10. 1 hp f-ly, 2 ill.

Description

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with y

The invention relates to the field of computing, and can also be used in generators and digital frequency synthesizers (in particular, in fractional frequency synthesizers).

The purpose of the invention is to expand the field of application by allowing the use in digital frequency synthesizers.

Fig, 1 shows the structural scheme of the accumulating adder; figure 2 - block diagram of the control unit "

The accumulating adder (FIG. O contains a combinational adder 1, a register 2, a memory block 3, a multiplexer 4, an information input 5, a decoder 6, a counter 7, a clock input 8, a control block 9, a synchronization block 10.

The control block 9 (Fig. 2) contains the first, second and third triggers 11-13, the HE element 14, the first and second And 15 and 16 elements.

Accumulating adder works as follows

The clock pulses go to the input of counter 7 and to the input of block 10 from input 8. Each input clock pulse transfers counter 7 to the next state. The output signal of counter 7 in the parallel code directly controls the operation of multiplexer 4, block 3 and decoder 6. Block 10 generates non-coincident impulses at the outputs. At the input of multiplexer 4, a multi-bit code is supplied.

Consider the operation of the accumulating adder during the action of one clock pulse. Using the code at the output of the counter 7, the corresponding part of the input code is selected and the corresponding part of the memory zone 3 of the block in which the information was recorded in the corresponding clock of the previous cycle. With the arrival of pulses from block 10, the clock input of register 2 information from the corresponding memory zone of block 3 is rewritten into register 2 and the MS steps onto the first information input of adder 1. The second information input of adder 1 through multiplexer 4 receives the corresponding code. In adder 1, you perform an arithmetic summation of three -cals: incoming from

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five

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the output of the register 2 to the first information input of the adder 1, coming from multiplexer 4 to the second information input of the adder I, coming from the output of block 9 to the transfer input of the adder 1 о With the arrival at the write inputs of block 3 and block 9 from the output of block 10 of the write pulse to the corresponding the memory area of block 3, which is determined by the parallel code coming from counter 7, is written down the code of the sum of three numbers, and the trigger 11 of block 9 from the transfer output of adder 1 overflow signal. The last signal will be used when summing the numbers the next cycle of operation of the accumulator

Using the decoder 6, the initial and final states of the counter 7, the beginning and the end of the operation cycle of the accumulating adder are recognized. At the beginning of the cycle, the decoder 6 identifies the zero state of the counter 7 and outputs a signal with a level of logical one at the first output. In block 9, this signal of the logical unit is inverted by the element NOT 14, blocks the element 15 and. Thus, with the arrival of the signal at the clock input of block 9, the trigger 12 records the signal with a logic zero level.

During other cycles of the cycle, the decoder 6 at its first output generates a signal with a logic level of zero. Element NOT 14 inverts the signal. Received at the output of the element NOT 14 signal with the level of the logical unit passes through the element 15 and the signal from the output of the trigger 11 to the information input of the trigger 12.

Thus, using the decoder 6 and block 9, the transfer input of the adder 1 is given a logical zero signal in the initial cycle cycle and a logical signal corresponding to the previous transfer output state of the adder 1 in the subsequent cycles of the accumulating adder cycle

At the second output of the decoder 6, a signal appears with the level of the logical unit in the last cycle cycle. This signal passes in block 9 through r the AND 16 element from the output of block 10 to the recording input of block 9

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synchronization pulse, with which the trigger 13 is recorded with

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transfer output of adder 1 to the first input of block 9 is the incoming overflow signal of adder 1; From the output of flip-flop 13, the overflow signal arrives at the output of accumulating adder.

When using the accumulating adder in the schemes of fractional, two-level and multi-level frequency synthesizers, information about the flow from the stand of the accumulating adder to the corresponding nodes can be output from the information output of the adder 1 o

Claims (1)

Invention Formula 1o Accumulating adder containing combinational adder, register, memory block, address counter, synchronization unit and control unit, the output of the adder is connected to the information input of the memory block, whose address input is connected to the output of the counter, the input of which is connected to the input of the block synchronization and with the clock input of the accumulating adder, the register output is connected to the first information input of the combinational adder, the first output of the synchronization block is connected to the recording input of the memory block, the second output of the block with synchronization is connected to the clock input of the register, which is due to the fact that, in order to expand the field of application by providing the possibility of using digital frequency synthesizers, a decoder and multiplexer are entered into it, the information input of which is connected to the information ten 15 20 993356 the input of the accumulating adder, and the address input with the output of the address counter and the input of the decoder, the inputs of the control unit from the first to the fifth are connected respectively to the first and second outputs of the synchronization unit, the first and second outputs of the decoder and the transfer output of the combinational adder, the second information input of which is connected with the multiplexer output, and the transfer input - with the first output of the control unit, the second output of which is connected to the frequency output of the accumulating adder, the code output of which is connected to the output Raman house adder, the output memory unit is connected to the data input of the register 2, the adder according to claim 1, about tl and h a-yu and and the fact that the control unit contains three flip-flops, two elements AND and the element NOT, and the output of the first trigger is connected to the first input of the first element And, the output of which connected to the D-input of the second trigger, the output of which is connected to the first output of the block, the first input of which is connected to the C-input of the first trigger and the first input of the second element And, the output of which is connected to the C-INPUT of the second trigger, whose output is connected to the second output of the block , the second input of which is connected to the C-input of the first trigger, rety input unit via the NOT element connected to the second input of the first AND gate, a second input of the second AND gate is connected to the fourth input unit, fifth input of which is connected to the D-BXO- rows of the first and third flip-flops. 25 thirty 35 40 with: "G t one 15 12 1B 9 C 13 Fsh.g