SU1197132A2 - Frequency-phase-shift keyer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase noise immunity by correcting a double error. At the inputs come information and tact. signals. The delayed delay element 4 carries the information signal to the input of the frequency manipulator 1. By switching the output signals of the multiplexer 6, a frequency-manipulated signal is generated. The source and delayed signals arrive at the inputs of the element OR 9. The inputs of the element And 10 receive clock signals from the output of the frequency divider 5 and from the output of the element OR 9. If the logical units coincide, all the inputs of the element 10 form a pulse at its output the state of trigger 11 is reversed. The output signal from the trigger 11 controls the operation of the switch 3, where the phase-controlled manipulation of the frequency-manipulated signal takes place. Invention dependent on auth. St. No. 919146. 2 nl.

Description

The invention relates to radio engineering and can be used to generate a signal with combined frequency-phase shift keying and is an improvement on invention 5 by ay. St. No. 919146.

The purpose of election is to increase noise immunity by correcting a double error.

In FIG. 1 shows a structural 10 electrical diagram of the proposed frequency-phase manipulator; in FIG. 2 is a timing diagram explaining its operation.

The frequency-phase manipulator 15 contains a frequency manipulator 1, a combination coding unit 2, a switch 3, a delay element 4, a frequency divider 5. The frequency manipulator 1 consists of a multiplexer 6, 20 of a 7-frequency synthesizer, a shift register 8, and a combination coding unit 2 of an OR 9 element, an I 10 element, and a trigger 11.

The device operates as follows 25.

The inputs receive information and clock signals (Fig. 2o, 8). Information signal delayed by the delay element 4, to the input ₃₀ of the frequency manipulator 1 (Figure 2 B.), Wherein is formed a frequency-keyed signal (FIG 2 ^.) By switching output signals (Figs 2, <|.?, E * ) multiplexer 6.

The initial (Fig. 2c) and delayed (Fig. 26) information signals come to the inputs of the OR element 9, the ² output signal (Fig. 2 {/) of which is fed to the Idins from the inputs of the And 10. The other inputs of the And element 10 clock signals come (Fig. 2k) from the output of the frequency divider 5. If logical units coincide (high voltage level) at all inputs of the And 10 element, a counting pulse is formed at its output (Fig. 2l), which changes the state of trigger 11 to the opposite. The output signal (Fig. 2m) of the trigger 11, which is the output signal of block 2, controls the operation of the switch 3, where the phase-shift keying of the frequency-manipulated signal is performed (Fig. 2 |). The resulting * signal is shown in (Fig. 2H).

Claims (1)

1 The invention relates to radio engineering and can be used to form a signal with a combined frequency-phase shift and VL. improvement of the invention on. St. 919146. The purpose of the avoidance is to improve noise immunity by correcting a double error. FIG. Figure 1 shows the structural electrical circuit of the proposed frequency-phase manipulator; in fig. 2 - time diagrams that show his work. The frequency-phase manipulator contains a frequency manipulator 1, a block 2 combinational coding, a switch 3, a delay element 4, a divider 5 frequencies. Frequency manipulator 1 consists of multiplexer 6, synthesizer 7-frequencies, shift register 8, and block 2 combinational coding - from the element OR 9, the element AND 10 and the trigger 11. The device works in the same way. , The inputs receive information and timing signals (Fig. 20.8). The information signal delayed by the delay element 4 is fed to the input of the frequency manipulator 1 (Fig. 2B), where the frequency-manipulated signal (Fig. 2) is formed by switching the output signals (Fig. 2g, F, e,) of the multiplexer 6. The original (Fig. 2a) and delayed (Fig. 26) information signals pos. blunt to the inputs of the element OR 9, the highest signal (Fig. 2 (/) which is fed to the ID of the inputs of the element AND 10. The other inputs of the element And 10 receive the clock signals (Fig. 2h) from the output of the frequency divider 5. When the logical units (high voltage level) at all inputs of the element I 10. A counting pulse (Fig. 2L) is formed at its output, changing the state of trigger 11 to the opposite. Output signal (Fig. trigger 11, which is the output signal of block 2, control There is a switch 3 operation where the phase shift of the frequencies o-manipulated signal (Fig. 2). The resultant signal is shown in (Fig. 24). the third input of the combinational coding unit is connected to an additional input of the frequency manipulator, and the frequency manipulator consists of a frequency synthesizer whose outputs are connected to one of the multiplexer inputs, the other inputs of which are connected to the outputs of the shift register, the first and second A swarm whose inputs are respectively an input and an additional input of a frequency manipulator .. KAA / WWWW   iWlA / l / lAM / VWVlAA | 1Ш / 1 / 1Ш1 / (( l V ALW A / l / lS WLLU / lSHLLLJ l rm -1g rm FIG. z -LJ l / l / l / lLU