SU1410104A1 - Memory unit inspection device - Google Patents

Abstract

The invention relates to a computing technique, in particular, to memory devices, and can be used to monitor memory blocks. The purpose of the invention is to increase the speed of the device. The device contains a control unit 1, which includes a delay element 2, keys 4 and 5, a frequency divider 6, a decoder 7, AND elements 8-10. The device also contains counters 12 and 19, an EXCLUSIVE OR element 13, a comparison block 14, triggers 15 and 16, an OR element 17 elements AND 18 and 23, an indication block 20. The device is connected to a controlled memory block 11. 2 Il.

Description

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The invention relates to computing, particularly storage devices, and can be used to control memory blocks.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 timing diagrams explaining how the device works.

These monitored memory block 11 reproduces the information from memory cell number 1 and cell number 2, since the negative edge of the pulse sequence from the output of the decoder 7 to the clock input of the counter 12 switches the addresses of the cells of block 11. Then O is written cell number 2 and reproduction of information from cell number 2 and cell number 3. Simultaneously reproducible information from the output of the monitored unit 11 is fed to the input of the comparison unit 14, the second input to orogo connected to the output

The device contains (Fig. 1) control block 1 consisting of a delay element 2, the input of which is the synchronization input 3 of the device, keys 4 and 5, frequency divider 6, decoder 7 and element 5 of the EXCLUSIVE OR element 13 8-10. One of the inputs of which enters the low K device is connected to the block 11 terminal level from the output of the trigger 16, and

controlled input memory. other input - pulse follower The device also contains the first character from the third output of the decoder 7

counter 12, the EXCLUSIVE element (FIG. 2e). The resulting comparison 13, block 14 comparison, the first 15 and 20 neither the error pulses arrive at one second 16 triggers, element OR 17, trans-from the inputs of the element 18, to the other input

And 18, the second counter 19, the display unit 20, the installation input 21, deciper 22 and the second And 23 element.

which receives the second gating sequence (Fig. 2h), which isolates errors only at the moments of reproducing information from the previously recorded memory cell of the monitored memory block 11, which allows detecting faulty memory cells whose outputs are permanently present high potential. Recording, playback, and comparing the Production Device works as follows.

which receives the second gating sequence (Fig. 2h), which isolates errors only at the moments of reproducing information from the previously recorded memory cell of the monitored memory block 11, which allows detecting faulty memory cells whose outputs are permanently present high potential. Recording, reproducing O, and comparing the output state at the output of the trigger 15, there is a low potential,; arriving at the control inputs of the keys 5 and 4 and prohibiting the passage of 30 dc to fully fill all the cells of the sync pulses at the input of the divider 6 and the input-controlled block AND memory of the 0-simy of the elements 9, 10 and 8. Upon arrival of the heels. The negative edge of the start of the pulse 21 of the installation (Fig. 2a) of the second bit of the counter 12 switches

divider 6, counters 12 and 19, trigger 16 and the trigger 16 sets up on its output, as well as the high potential input to

 cue potential at the trigger output 15. At 5, the information input of the controlled by this keys 4 and 5 are opened. There are 11 memories on the sync block. After the switch-over input of the splitter 6, the first to begin the pulse of the first clock pulse (FIG. 26) after trigger 16 of the trigger 16. Divider sequence into the cell

performs frequency division of memory sync-block 11 with number 1 produces pulses with a division factor equal to 40 record 1. Then it is produced by playback 3. At the outputs of the decoder 7, the information from the memory cell with

pulse sequences are formed (fig. 2d, d, e), which are fed to the inputs of the And 10, 9 and 8 elements, respectively. The other inputs of these elements are received via the key 5 delayed clock pulses (for example, for a half period) by element 2 (Fig. 20). As a result, the first, second, and third str

number 1 and cell number 2. Next, record 1 into cell number 2, play information from cell number 2 and cell number 3. Reproduced information from the output of the monitored unit 11 is fed to one of the inputs of the comparison unit 14, to another input which receives the pulse sequence from the output element

Pulse pulse sequential spn - EXCLUSIVE OR 13 (Fig. 2n). ti (Fig. 2es, s, s). Since the information pulses of the error received as a result of the comparison arrive at the input of the element I 18, where they are strobed with the fourth building pulses (Fig. 2k) obtained as a result of the addition of the second and

(Fig. 2g) O is recorded in the cell 55 of the third gating pulses at elem, memory block 11 with number 1. In the interval OR 17. Thus, during the repetition between the first and second pulminary, the memory of the first gated serial gates is interrupted. block 11, the recording control is performed

the input of the memory block 11 from the output of the trigger 16 receives a low potential, then the pulse of the first gate sequence, the first after the impulse of the pulse, is set up

These monitored memory block 11 reproduces the information from memory cell number 1 and cell number 2, since the negative edge of the pulse sequence from the output of the decoder 7 to the clock input of the counter 12 switches the addresses of the cells of block 11. Then O is written cell number 2 and reproduction of information from cell number 2 and cell number 3. Simultaneously reproducible information from the output of the monitored unit 11 is fed to the input of the comparison unit 14, the second input to orogo connected to the output

of the EXCLUSIVE or 13 element, at one of the inputs of which the pulses of the error go down to one of the inputs of the AND 18 element, at the other input

which receives the second gating sequence (Fig. 2h), which isolates errors only at the moments of reproduction of information from a previously recorded memory cell of the monitored memory block 11, which allows detecting faulty memory cells whose outputs are constantly present potential. Record, Play O, and Record Production Comparison 1. Then, reproduction of information from the memory cell with

number 1 and cell number 2. Next, record 1 into cell number 2, play information from cell number 2 and cell number 3. Reproduced information from the output of the monitored unit 11 is fed to one of the inputs of the comparison unit 14, to another input the pulses AND, the OR element and the display unit, the synchronization input of the control unit being the device synchronization input, the installation inputs of the flip-flops, the counters and the control unit are combined and are the installation input of the device counting The first counter is connected to the second output of the control unit, the bits of the first counter are connected to the information inputs of the decoder and are the device’s output outputs, the overflow output of the first counter is connected to the information input of the second trigger, the output of which is connected to the control input of the decoder 1 character in the cell memory and checking the invariance of the state of the next memory cell, which makes it possible to detect not only faulty memory cells whose output always has a low al, but all short-circuited with each other cell. Record 1, reading and comparing the recorded and read information is performed until the entire memory cells of the monitored block AND memory are filled with 1 characters. The decoder 22 extracts the pulse of the last address of the monitored block, the trigger 15 of which switches the negative edge at a negative front. The zero potential at its output blocks the key 4 and 5.

Pulses error from the output of the element AND 18 15 of the torus, the first input of the element is EXCLUDED to the input of the counter 19, where the counting OR OR, the first input of the second element AND is the input of the monitored memory block of the device, the third and fourth outputs of the control unit are connected respectively, with the second 20 input of the EXCLUSIVE OR element and the second input of the second AND element, the output of which is connected to the first input of the OR element, the second input of which is connected to the fifth output of the control unit,

a control unit whose first output 25 of the output of the OR element is connected to the first one is the write / read output of the device, the input of the first AND element; second entrance

the first input of the comparison unit is the information input of the device, the second input of the comparison unit is connected to the output of the EXCLUSIVE OR element, characterized in that, in order to increase the speed of the device, the second trigger, the first and second counters, the decoder, the first and second windings are entered into it and their number is displayed on block 20.

Claims (1)

Invention Formula A device for monitoring memory blocks, comprising a comparison unit, a first trigger, an EXCLUSIVE OR element, and  thirty which is connected to the output of the comparison unit, the output of the first element I is connected to the counting input of the second counter, the outputs of which bits are connected to the inputs of the display unit, the output of the first trigger is connected to the lock input of the control unit, the output of the decoder is connected to the information input of the first trigger. The AND elements, the OR element and the display unit, the synchronization input of the control unit being the device synchronization input, the installation inputs of the flip-flops, the counters and the control unit are combined and are the installation input of the device, the counting input of the first counter is connected to the second output of the control unit, the outputs of bits The first counter is connected to the information inputs of the decoder and is the address output of the device, the overflow output of the first counter is connected to the information input of the second trigger, the output of which It is connected to the control input of the decoder, the first input of the EXCLUSIVE OR element, the first input of the second output element of the OR element, and is connected to the first input of the first AND element; second entrance which is connected to the output of the comparison unit, the output of the first element I is connected to the counting input of the second counter, the outputs of which bits are connected to the inputs of the display unit, the output of the first trigger is connected to the lock input of the control unit, the output of the decoder is connected to the information input of the first trigger. a 6 8 g L