SU1241288A1 - Buffer storage - Google Patents

Abstract

The invention is intended for use in digital information processing systems. The purpose of the invention is to simplify the device. The buffer memory contains a register, the setup input of which is connected to the trigger setup input and is the setup input of the device; the group of setup inputs of the register is connected to the outputs of the AND elements, the first inputs of which are information inputs of the device; a trigger whose clock input (the input at which the trigger changes its initial state) of which is connected to the output of the OR-NOT element, whose inputs are connected to the outputs of the I. 1 ementov yl. from 9 (L S

Description

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The invention relates to the field of storage devices and is intended for use in digital information processing systems.

The purpose of the invention is to simplify the device and increase its speed.

The drawing is a functional diagram of the invention.

The device contains elements AND 1, register 2, element OR-NOT 3, trigger 4, setup input (reset) 5, information inputs 6.

The device works as follows.

When a signal arrives at the reset input 5, the triggers of register 2 are set to the zero state, and the trigger 4 is set to one. At the output of the element OR-NOT 3 at this time, a single potential determined by low-level signals at the information inputs 6 of the device is saved. .After switching the trigger 4, the level of the logical unit from its direct output opens the elements AND 1, preparing the device for recording the input information. Input information in parallel code enters the inputs 6 (the inputs of the elements And 1). In this case, the corresponding bits of register 2 are set to one. With the appearance of the first code pulse at the output of the AND 1 elements, the OR-NOT 3 element switches to the zero state, and with the end of the last, to the single state

12412882

Simultaneously with the termination of a negative impulse at the output of an element OR-NOT 3 trigger 4 with a positive voltage drop across its clock

The 5th input C switches to the zero state, since at its D input a constant zero is always present. Switching, trigger 4 low-level signal

10, from its forward output, blocks AND 1 elements. A blocking signal appears with the end of the last code pulse. Desynchronization of code pulses (in the word information),

5 incoming by. the information input to the device should not exceed the pulse duration.

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Claims (1)

Invention Formula The buffer memory device containing the register, the setup input of which is controlled by the clock of the device, the setup inputs of the register group are connected to the input of the OR-NO element and the outputs of the AND elements, the first inputs of which are the information inputs of the device, device outputs, characterized in that, in order to simplify the device and increase its speed, it contains a trigger, the setup input of which is connected to the register setup input, the second inputs ementov and connected to the output of the flip-flop, a clock input which is connected to VYH.ODU OR-NOT. Invention Formula The buffer memory device containing the register, the setup input of which is controlled by the clock of the device, the setup inputs of the register group are connected to the input of the OR-NO element and the outputs of the AND elements, the first inputs of which are the information inputs of the device, device outputs, characterized in that, in order to simplify the device and increase its speed, it contains a trigger, the setup input of which is connected to the register setup input, the second inputs ementov and connected to the output of the flip-flop, a clock input which is connected to VYH.ODU OR-NOT.