JPH03174818A - Integration type a/d conversion circuit - Google Patents

Abstract

PURPOSE:To quicken the A/D conversion speed by implementing 3 states such as the charging of a capacitor required for A/D conversion, 1st discharge and 2nd discharge simultaneously. CONSTITUTION:The connection of combinations of three capacitors 6a-6c, two constant current sources 7a, 7b and two comparator circuits 1a, 1b is selected by three switches 5a-5c. Then the period charging an input voltage to the capacitor, the period discharging the capacitor for applying coarse A/D conversion and a period discharging the capacitor for fine A/D conversion at a slower speed are simultaneously executed. Thus, the conversion speed thrice that of a conventional A/D converter circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integral type A/D conversion circuit, and particularly to an integral type A/D conversion circuit implemented as a semiconductor integrated circuit.

[Conventional technology]

A conventional integrating type A/D conversion circuit includes a capacitor charged by an analog input voltage, a plurality of constant current sources, a switch that switches between these sources to discharge the capacitor, a comparator, and a control section that controls the switch. It also includes a counter, a latch circuit, and the like.

FIG. 5 is a functional block diagram of an A/D conversion circuit showing an example of the conventional technology, and FIGS. 6(a) and 6(b) are diagrams showing switch changeover in the conversion circuit shown in FIG. 5, and input side diagrams, respectively. It is a terminal voltage characteristic diagram.

As shown in FIG. 5 and FIGS. 6(a) and (b), in the conventional integral type A/D converter, only the switch 5a connected to the analog human power vrN is turned on by the control unit 2 during the period T1. are doing. Therefore, the capacitor 6 is charged and the voltage value V at the terminal 8 becomes equal to the input voltage VIH. Next, in period T2, only the switch 5b is turned on, so that the capacitor 6a is discharged at a speed corresponding to the current value i of the constant current source 7a. The voltage at this terminal 8 is the input voltage of the comparator circuit 1, and when the comparison result with the ground voltage approaches approximately O, the control section 2 switches the switch. Next, in period T3, the switch 5c is turned on, so that the capacitor 6 is discharged again by the constant current source 7b. The discharge rate during this period T is set to be slower than the discharge rate during period T2. Furthermore, based on the comparison result of the comparator circuit 1 which inputs the voltage value of the terminal 8, the control unit 2 returns to the state where only the switch 5a is turned on, that is, returns to the period T1, and one A/D conversion cycle is completed. do.

The lengths of the periods T2 and T mentioned above are measured by counting clock pulses with counters 3a, 3b. The results are weighted according to the discharge speed of each constant current source 7a, 7b, and the latch 4a.

4b, the signals are digitally outputted at the same timing. In short, the current value i in the constant current source 7a is large, and the voltage value at the terminal 8 changes rapidly.

The resolution at this time is the voltage value that changes due to discharge within the interval of one p work pulse, and in this case is set roughly. On the other hand, the current value i at the constant current source 7b is small, the voltage value at the terminal 8 changes slowly, and the resolution is high.

In this way, the constant current source circuits 7a, 7b, which have different current values,
That is, by using two constant current source circuits 7a and 7b with different discharge speeds of the capacitor 6, the integral type A/D converter realizes faster conversion than when using a single constant current source circuit. can do.

[Problem to be solved by the invention]

The above-mentioned conventional integral type A/D conversion circuit discharges the voltage value held in the capacitor using a constant current source and counts the discharge time using clock pulses, so the speed of A/D conversion is determined by the time it takes to discharge the capacitor. becomes slower as it gets longer. Therefore, there is a drawback that as the resolution becomes higher, the A/D conversion speed becomes slower.

For example, when discharging a 10-bit A/D converter with a single constant current source, if the clock frequency is 10 MHz, at least 210 x 2 clocks are required for one conversion, -= 4. The conversion speed is 88 KHz048. On the other hand, divide 10 bits and top 5
If the discharge is divided into bit portion and lower 5 bit portion, 2″
The conversion is performed in two steps using ×2 clocks, and the conversion speed in this case is □=2878.125 KHz. However, it is difficult to realize such a fast A/D converter.

An object of the present invention is to provide such an integral type A/D converter with a high conversion speed.

[Means to solve the problem]

The integrating type A/D converter of the present invention includes a first switch connected to an analog input terminal for switching to a plurality of terminals, a capacitor connected to each of the plurality of terminals, and a capacitor connected to each of the plurality of terminals or directly connected to the plurality of terminals. second and third switches connected via a capacitor; first and second comparators connected to reference voltage comparison input sides via the second and third switches, respectively; a control unit that controls switching operations of the first to third switches based on the outputs of the first and second comparators; a counter that counts clock outputs from the control unit; It has a latch that weights the output according to the discharge rate of the capacitor and outputs the output at the same timing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of an integral type A/D conversion circuit showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes three capacitors 6a to 6C for holding analog human power vrN, and a first constant for discharging these capacitors 6a to 6C to perform rough A/D conversion. a current source circuit 7a; a first comparator circuit 1a in which the first constant current source circuit 7a and the charged side terminals of the capacitors 6a to 6c are connected to the comparison input side, and the other terminal is set to ground potential; a second constant current source circuit 7b whose discharge rate of the capacitors 6a to 6c is slower than that of the first constant current source circuit 7a and which performs fine A/D conversion;
This second constant current source circuit 7b and capacitors 6a to 6
A second comparator circuit 1b whose charged side terminal of c is connected to the comparison input side and whose other terminal is set to ground potential, and these 3
capacitors 6a to 6c and two constant current source circuits 7a,
7b and two comparator circuits 1a and lb, and switches 5a to 5c based on the output results of the comparator circuits 1a and lb, and outputs a clock pulse accordingly. a control section 2 for counting clock pulses from the control section 2, counters 3a and 3b for counting clock pulses from the control section 2, and a counter 3 for counting clock pulses from the control section 2.
The count results in a and 3b are sent to two constant current source circuits 7.
A latch 4a outputs a digital signal by weighting the signals a and 7b according to the discharge speed and aligning the timing.

4b.

FIGS. 2(a) to 2(d) are a switch correspondence diagram and three terminal voltage characteristic diagrams in the conversion circuit shown in FIG. 1, respectively.

As shown in FIG. 2(a), the relationship between the periods T1 to T6 and the switches 5a to 5c is such that, for example, when looking at the switch 5a, it is in the a position during periods T1 and T4, and in T2. T
3 indicates that it is in the b position.

Further, as shown in FIGS. 2(b) to 2(d), the voltages at the terminals 8a to 8c connected to the analog human power input terminal 1N are shifted by one period.

Next, the circuit operation of the above-mentioned integral type A/D converter will be explained with reference to FIG. 1 and FIGS. 2(a) to 2(d).

First, during period T shown in FIG. 2(a), the switch 5a is turned on by the control section 2. Therefore,
Only the capacitor 6a is charged, and the voltage value at the terminal 8a becomes equal to the input voltage VIH shown in FIG.

Next, during a period T2 shown in FIG. 2(a), the control unit 2 turns on the switch 5a to the B position and turns on the switch 5b to the A position. During the period tb3 of the period T2, the charged capacitor 6a is discharged by the constant current source 7a, and when the voltage at the terminal 8a becomes lower than the comparison voltage of the comparator 1a, 1
Based on the comparison result of the comparator a, the control section switches the switch 5b to floating for the remaining time of period T2, that is, for tb4.

Also, since the capacitor 6b is charged, the voltage value at the terminal 8b becomes equal to the input voltage VIH shown in FIG.

Next, during period T, the control section 2 turns on the switch 5a to the C position, and turns the switch 5b to the B position.
Switch 5C is turned on to position a. During period tc5 of period T, capacitor 6a
is being discharged by the constant current source 7b, and when the voltage at the terminal 8a becomes equal to or lower than the comparison voltage of the comparator 1b, the controller turns on the switch 5c for the remainder of the period T3, that is, according to the comparison result of the comparator 1b. Switch to floating during tc=.

At the same time, during period tbs of period T3, capacitor 6b
is being discharged by the constant current source 7a, and when the voltage at the terminal 8b becomes less than the comparison voltage of the comparator 1a, the control section switches the switch 5b for a period T according to the comparison result of the comparator 1a.
Switch to floating for the remaining time of 3 tbs. Further, since the capacitor 6c is charged by the switch 5a, the voltage value at the terminal 8c becomes equal to the input voltage vrN shown in FIG.

The operation of discharging the voltage value charged in the capacitor 6a in the above-described period T3 is completed. At this time, since the constant current source 7b is set to have a slower discharge rate than the constant current source 7a,
The number of clock pulses until the end of the discharge during period T2°T is weighted according to the speed, and the results counted by counters 3a and 3b are digitally outputted by latches 4a and 4b at the same timing.

Similarly, during period T4, the switch 5a is turned on to the A position, the switch 5b is turned on to the C position, and
Switch 5c is turned on at position b. Therefore,
The terminal 8a is charged and becomes equal to the input voltage value V1, and the terminal 8b is discharged by the constant current source 7b during the period tct, and then the switch is changed by the control section and becomes floating during the tea period.

The terminal 8c is discharged by the constant current source 7a during the period tbr, and then is switched by the control unit and becomes floating for the period tbs. During this period T4, the operation of discharging the voltage value charged in the capacitor 6b is completed, and digital output is performed in the same manner as the above-mentioned operation.

Furthermore, during period T, the switch 5a is turned on to the b position, the switch 5b is turned on to the a position, and the switch 5c is turned on.
is turned on in the C position.

Therefore, the terminal 8a is discharged by the constant current source 7a during the period tbe, and then the switch is changed over by the control section to reach the period tbl. It will be floating for a while.

On the other hand, the terminal 8b is charged and becomes equal to the input voltage value,
Further, the terminal 8c is discharged by the constant current source 7b during the period tce, and then the switch is changed by the control unit and becomes floating for the period tc.

After this period T ends, the input voltage charged in the capacitor 6c is similarly output digitally. In this way, the input voltage values charged in the three capacitors are sequentially discharged by switching the switches to obtain a digital output.

FIG. 3 is a functional block diagram of an integral type A/D conversion circuit showing a second embodiment of the present invention, and FIGS. 4(a) to 4(d) are switches in the conversion circuit shown in FIG. 3, respectively. They are a switching correspondence diagram and three terminal voltage characteristic diagrams.

As shown in FIG. 3 and FIGS. 4(a) to (d), the configuration of this embodiment is basically the same as that of the first embodiment described above, except for the differences in the first embodiment. Capacitors 6a to 6c that hold the analog input voltage VIN used
and a constant current source for discharging capacitors 6a to 6c? a, 7b to integrators 9a, 9b and these integrators 9a, 9b
capacitors 6a to 6c and capacitors 6a to 6c for
Five switches 5a are switching means for charging and discharging the
-5e were provided.

That is, in this embodiment, three capacitors 6 and 6c hold the input voltage VIN, and switching switches 5a and 5a for charging and discharging the capacitors 6 and 6c are provided.
5e, and a first integrating circuit 9a that roughly integrates the input voltage V(H) accumulated by the capacitors 6a to 6c.
A first comparator circuit 1a receives the output of the first integrating circuit 9a, a second integrating circuit 9b integrates the input voltage VIN more finely, and the output of the second integrating circuit 9b. A second comparator circuit 1b as an input, a control section 2 similar to the first embodiment described above, a counter 3a,
3b and latch circuits 4a and 4b.

In this embodiment, by changing the reference voltage values of the integrators 9a and 9b, the discharge speed of the capacitors 6&-6c can be set appropriately.

In short, according to the two embodiments described above, two comparator circuits and three capacitors are provided, and by switching them with a switch, charging of the capacitors required for A/D conversion,
Since the three states of the first discharge and the second discharge can be performed simultaneously, the A/D conversion speed can be increased.

〔Effect of the invention〕

As explained above, the integral type A/D converter of the present invention has the following features:
There are three capacitors for holding the input voltage, a first comparator circuit for performing coarse A/D conversion, a second comparator circuit for performing fine A/D conversion, and a second comparator circuit for performing fine A/D conversion. By using multiple switches for switching, there is a period for charging the capacitor with input voltage, a period for discharging the capacitor for coarse A/D conversion, and a period for discharging the capacitor for fine A/D conversion. It is possible to realize a period of discharging at a slow rate at the same time, and there is an effect that a conversion speed three times that of the conventional method can be obtained.

Furthermore, if this configuration is used, a sample and hold circuit that is slower than the conventional one can be used to configure the same A/D converter, so it is easy to implement.

Although it is possible to obtain such characteristics by using three A/D converters in parallel, the configuration is simpler than that.

Furthermore, since the capacitor determines the accuracy of the integral type A/D converter in the present invention, the accuracy can be improved by making the capacitors manufactured on the semiconductor substrate adjacent to each other.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an integral type A/D conversion circuit showing the first embodiment of the present invention, and FIGS. 2(a) to (d) respectively correspond to switch changes in the conversion circuit shown in FIG. 3 is a functional block diagram of an integral type A/D conversion circuit showing the second embodiment of the present invention, and FIGS. 4(a) to 4(d) are respectively shown in FIG. 3. FIG. 5 is a functional block diagram of a conventional A/D conversion circuit showing an example of a conventional A/D conversion circuit.
FIGS. 6(a) and 6(b) are a switch correspondence diagram and an input terminal voltage characteristic diagram in the conversion circuit shown in FIG. 5, respectively. la, lb...Comparator, 2...
Control section, 3&, 3b... Counter, 4
a, 4b...Latch, 5a-5e...
Switch, 6a-6c...Capacitor, 7a,
7b... Constant current source, 8a to 8e... Comparator input, 9a, 9b... Integrator.

Claims (1)

[Claims] a first switch connected to the analog input terminal and switching between the plurality of terminals; a capacitor connected to each of the plurality of terminals; and second and third switches connected to the plurality of terminals either directly or via the capacitor. a switch, first and second comparators connected to the comparison input side for the reference voltage via the second and third switches, respectively; a control section that controls the switching operations of the first to third switches; a counter that counts the clock output from the control section; and a control section that weights the count results of the counter according to the discharging speed of the capacitor and controls the timing. An integral type A/D conversion circuit characterized by having a latch that outputs in alignment.