JP2008092387A - Analog/digital conversion circuit, timing signal generating circuit, and controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform operation equivalent to high-frequency operation by using oscillation pulses having a lower frequency, without generating oscillation pulses of high frequency. <P>SOLUTION: In the analog/digital conversion circuit 1, a synchronizing signal output circuit 11 generates a series of N synchronizing signals sequentially at delay time intervals of (approximate value of one period (T) of each synchronizing signal)/N (number). By doing this way, a first to j-th pulse counting devices (counter 12) out of N pulse counting devices are made to count a count value X, and the remaining pulse counting devices are made to count a count value (X-1), respectively during a sample period. From the states of counting of the N pulse counting devices, a digital signal generating circuit converts an analog signal into a digital signal, with a resolution N times that of an A/D conversion by the sample period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides an analog-digital conversion circuit that can perform an operation equivalent to an operation at a high frequency with a low frequency oscillation pulse without generating a high frequency oscillation pulse, and a timing signal based on the above high frequency. And a control device using the analog / digital conversion circuit and the timing signal generation circuit.

  In digital control of a power conversion device, after A / D conversion, filter processing by a digital signal processing circuit, etc., a timing signal is generated by the timing signal generation circuit, and based on this, switching elements such as transistors are turned on / off Driving. In digital control, high quality control can be performed by increasing the resolution during A / D conversion.

  However, an oscillator that can generate an oscillation pulse with a high frequency is expensive. For example, an inexpensive oscillator of about 25 MHz is used to multiply the output of the oscillator to obtain an oscillation frequency on the order of GHz, but the circuit becomes large and cannot be manufactured at a low cost. is there.

  In addition, devices that operate with an oscillator such as an analog / digital converter circuit generally increase in power consumption as the frequency increases. Therefore, economic efficiency may deteriorate, and measures such as heat dissipation may be required. There is also a problem.

  An object of the present invention is to use an analog / digital conversion circuit, a timing signal generation circuit, and the like that can perform an operation equivalent to an operation with a high oscillation pulse with a low oscillation pulse without generating a high oscillation pulse. It is to provide a control device.

The analog-digital conversion circuit of the present invention is
A periodic signal output circuit for inputting a time-varying analog signal and replacing the analog signal with an N-sequence periodic signal having a frequency corresponding to the magnitude of the analog signal;
N pulse counting devices that respectively count the number of pulses of the N-sequence periodic signal;
A digital signal generation circuit that inputs the N series periodic signals and generates a digital signal corresponding to the magnitude of the analog signal for each sample period from these periodic signals;
With
The periodic signal output circuit sequentially outputs the N-sequence periodic signals.
[Approximate value of one period (T) of periodic signal] ÷ N (pieces)
Of the N pulse counters, the first to jth pulse counters of the N pulse counters and the remaining pulse counters of the counter value (X -1) is counted,
The digital signal generation circuit converts the analog signal to the digital signal from the counting state of the N pulse counting devices with N times the resolution when A / D conversion is performed in the sampling period. To do.

In the analog / digital conversion circuit according to the present invention, the periodic signal output circuit may be composed of converters that convert the magnitudes of N electrical signals into frequencies, and these converters may generate periodic signals.
In the present invention, the “pulse counting device” is typically a counter, but can also be constituted by a circuit including a shift register and a CPU.

  In the present invention, the “converter that converts the magnitude of an electric signal into a frequency” is a voltage-controlled oscillator, but the amplitude or the like of the voltage / current value to be converted is a frequency (specifically, a periodic pulse). As long as it can be changed to, it is not limited to a voltage controlled oscillator.

  In the analog-digital conversion circuit according to the present invention, the converter is configured by an integration circuit, and the periodic signal generated by the converter starts from the operation of the integration circuit by the input voltage until it ends (for example, integration When the circuit is a CR circuit, charging of the capacitor is started by the reference voltage, and when the charging voltage reaches the threshold value, charging of the capacitor is finished and discharging is started, and the charging voltage becomes the initial voltage. (Until it returns).

The timing signal generation circuit of the present invention includes:
A periodic signal output circuit for outputting an M-sequence periodic signal of a frequency;
M comparison pulse counting devices that input the M-sequence periodic signal corresponding to the magnitude of the digital signal and output a predetermined signal (full count signal) when the count value reaches the set value;
The M number of the predetermined signals (full count signals) are input from the M number of comparison pulse counting devices, and a timing signal having a time interval corresponding to the magnitude of the digital signal is generated for each reference period from these predetermined signals. A signal generation circuit;
With
Among the M comparison pulse counters, a count value is set in the first to k-th pulse counters, and a counter value is set in the remaining pulse counters.
The M-sequence periodic signals are sequentially
[Approximate value of one period (T) of periodic signal] ÷ M (pieces)
By entering at a delay time interval of
The signal generation circuit may generate a timing signal having a precision N times that when a timing signal is generated by one pulse counter from the output state of the M pulse counters.

  In the timing signal generation circuit of the present invention, a distribution circuit for setting the count value in the M comparison pulse counters can be provided.

  In the timing signal generation circuit of the present invention, the periodic signal output circuit is composed of M converters that convert the magnitude of an electric signal into a frequency, and these converters generate a periodic signal. it can.

  Further, in the timing signal generating circuit of the present invention, the converter is constituted by an integrating circuit, and the periodic signal generated by the converter is from the start of operation of the integrating circuit by the input voltage to the end of the operation (reference voltage). The charging of the capacitor is started, and when the charging voltage reaches the threshold value, the charging of the capacitor is finished and the discharging is started, and the charging voltage is returned to the initial voltage) until one cycle. .

The control device of the present invention
Any one of the analog-digital conversion circuits described above;
Any one of the timing signal generation circuits described above;
A digital signal processing circuit;
Consists of
The analog-digital conversion circuit digitizes the analog output from the controlled object,
The digital signal processing circuit processes the digitized signal to generate a digital timing value;
The timing signal generation circuit generates a control timing signal based on the digital timing value;
It is characterized by that.

  In the control device of the present invention, the periodic signal output circuit used in the analog / digital conversion circuit and the periodic signal output circuit used in the timing signal generation circuit can be shared.

  In the control apparatus of the present invention, the digital signal processing circuit can perform a digital filter, P control, I control, D control, or a combination of these.

  Further, in the control device of the present invention, the control target is configured by a power conversion circuit including a switch element, the analog / digital conversion circuit inputs an output voltage of the power conversion circuit, and the timing signal generation circuit is the power An on / off timing signal can be output to the switch element of the conversion circuit.

  In the present invention, it is possible to perform an operation equivalent to the operation with the high oscillation pulse by using a low oscillation pulse without generating a pulse with a high oscillation pulse. Compared to the timing signal generation circuit and the control device, it is possible to reduce the manufacturing cost and the power consumption.

  That is, the analog / digital conversion circuit and timing signal generation circuit of the present invention can operate at a high speed equivalent to an operation with several to several tens of times the oscillation pulse using a low frequency oscillation pulse. Moreover, in the control apparatus of this invention, a low-cost and high-performance control system can be constructed | assembled by comprising a control apparatus combining these.

FIG. 1 is an explanatory diagram showing a basic embodiment (first embodiment) of an analog-digital conversion circuit of the present invention. In FIG. 1, the analog / digital conversion circuit 1 includes a periodic signal output circuit 11, a counter 12, and a digital signal generation circuit 13.
The periodic signal output circuit 11 receives an analog signal _AIN that changes over time, and outputs the analog signal AIN by replacing it with N-sequence periodic signals P _{1 to} P _N having a frequency f _S corresponding to the magnitude of the analog signal A _IN .

Counter 12, of N counter CNTR ₁ ~CNTR _N for counting periodic signal N series P ₁ to P _N number of pulses, respectively. The digital signal generation circuit 13 receives N series of periodic signals P _{1 to} P _N, and generates a digital signal D _OUT corresponding to the magnitude of the analog signal A _IN from these periodic signals P _{1 to} P _N. Generate for each _SMPL .

In the present invention, the periodic signal output circuit 11 sequentially receives N-sequence periodic signals P _{1 to} P _N.
[Approximate value of one period (T) of periodic signals P _{1 to} P _N ] ÷ N (pieces)
Generate at the delay time interval. For example, P ₂ is a signal delayed by (1 / N) from P ₁ , and P ₃ is a signal delayed further by (1 / N) than P ₂ .

Thus, during the sample period T _SMPL, first to the counter CNTR ₁ ~CNTR _j is a count value X of the j, the count remaining counter counts the (X-1) each of the N counter 12 Will do. However, when j = N, there is no “remaining counter”. That is, the count values of all the counters CNTR _{1 to} CNTR _N are X.

When the accuracy of the counters CNTR _{1 to} CNTR _N is a bits, the accuracy (resolution) of the output signal of the periodic signal output circuit 11 is 2 ^a × N. That is, the digital signal generation circuit 13 outputs the analog signal A _IN with N times the accuracy when A / D conversion is performed from the count state of the _N counters 12 (counters CNTR _{1 to} CNTR _N ) in the sample period T _SMPL. Convert to digital signal (digital numerical value) _DOUT .

For example, a CNTR ₁ ~CNTR count of _j is X, when the count value of CNTR _j + 1 ~CNTR _N is X-1, the numerical total is the (X-1) + (j / N) .

FIG. 2 shows a basic embodiment (second embodiment) of the analog / digital conversion circuit of the present invention, and the periodic signal output circuit 11 can be composed of _N voltage / frequency conversion circuits VF _{1 to} VF _N. . In FIG. 2, VF ₁ generates operation start timing signals of P ₁ , P ₂ ,..., P _N (see the dotted line in FIG. 2), but operates as shown in the third embodiment described below. It is also possible for the controller to generate a start timing signal.

FIG. 3 is an explanatory diagram showing a specific embodiment (third embodiment) of the analog-digital conversion circuit of the present invention. In FIG. 3, the analog / digital conversion circuit 1 includes a periodic signal output circuit 11, a counter 12, a digital signal generation circuit 13, and a controller 14. In FIG. 3, the counter 12 is composed of CNTR _{1 to} CNTR ₈ . In this embodiment, the resolution of the counters CNTR _{1 to} CNTR ₈ is 5 bits, and the counter 12 is composed of 8 (2 ³ ) counters CNTR _{1 to} CNTR _8. Has an 8-bit resolution.

Periodic signal output circuit 11 outputs by replacing the voltage e _O apply voltage e _O as an analog signal which changes time period signal P ₁ to P ₈ 8 series of frequency f _S that corresponds to its size. Specifically, the periodic signal output circuit 11 is constituted by a voltage controlled oscillator (VCO ₁ ~VCO _N). The controller 14 generates an operation start timing signal SV ₁ Sv ₈ and duty cycle signal R of the analog-to-digital converter 1 of VCO ₁ ~VCO _N.

As shown in FIG. 4, the periodic signal output circuit 11 sequentially outputs eight series of periodic signals P _{1 to} P ₈ .
[Approximate value of one period (T) of periodic signals P _{1 to} P ₈ ] ÷ 8 (pieces)
Generate at the delay time interval.

The counters CNTR _{1 to} CNTR ₈ receive and count the period signals P _{1 to} P ₈ every sample period T _SMPL . In the counters CNTR _{1 to} CNTR ₈ , the count value of the counters CNTR _{1 to} CNTR ₃ is 22 and the count value of the remaining counters CNTR _{4 to} CNTR ₈ is 21 when the sample period T _SMPL has expired. Is shown.

The digital signal generation circuit 13 generates the voltage e _O with a resolution eight times that when the A / D conversion is performed in the sample period T _SMPL from the count state of the counters CNTR _{1 to} CNTR _N when the sample period T _SMPL expires. It can be converted to a digital signal D _OUT . The digital signal generation circuit 13 can sum the values of the counters CNTR _{4 to} CNTR ₈ and output a digital numerical value. For example, in the above example, the count value of CNTR _{1 to} CNTR ₃ is 22, and the count value of the remaining counters CNTR _{4 to} CNTR ₈ is 21, so that the output numerical value can be 22 × 3 + 21 × 5 = 171. . The full count value is 256 because the whole is 8 bits.

In this embodiment, VCO _{1 to} VCO ₈ have CR circuits, and periodic signals P _{1 to} P ₈ generated by VCO _{1 to} VCO ₈ charge C (capacitor) by the input voltage as shown in FIG. It starts, and when the charging voltage reaches the threshold value, the charging of the capacitor C is finished and the discharging is started, and the charging voltage is returned to the initial voltage as one cycle.

The operation of VCO ₁ to VCO _{8 in} FIG. 3 will be described with reference to FIG. The VCO ₁ starts to operate in response to the operation start timing signal SV ₁ generated by the controller 14, and the VCO ₁ generates the periodic signal P ₁ when the input voltage reaches the threshold value V _T.

On the other hand, the controller 14, the charging voltage 3V _T / 4,2V charging voltage _{V T / 4,2V T / 4,3V T} / 4, V T and when the voltage drop at the voltage rise C of the CR circuit of VCO ₁ The timing of _T / 4, V _T / 4 is detected. Then, the controller 14 is the charging voltage _{V T / 4,2V T / 4,3V T} / 4, V T, 3V T / 4,2V T / 4, V T / 4 to become the operation start timing timing signal SV ₂ , SV ₃ , SV ₄ , SV ₅ , SV ₆ , SV ₇ , SV ₈ are generated (only SV ₂ and SV ₃ are shown in FIG. 5). When VCO ₂ to VCO ₈ are driven by these operation start timing signals and the input voltages reach the respective threshold values V _T , periodic signals P _{2 to} P ₈ (only P ₂ and P ₃ are shown in FIG. 5). ) Is generated. The voltage rise of VCO _{1 to} VCO ₈ depends on the value of the input voltage during each operation. In Figure 5, there is shown the slope of the voltage rise of the VCO ₁ ~VCO ₃ in alpha ₁ to? _3.

FIG. 6 is an explanatory diagram showing another specific embodiment (fourth embodiment) of the analog-digital conversion circuit of the present invention. The periodic signal output circuit 11 in FIG. 6 includes one voltage controlled oscillator VCO and a plurality of delay circuits (DLY _{1 to} DLY ₇ ). The outputs of the voltage controlled oscillator VCO are sequentially delayed by DLY _{1 to} DLY ₇ to generate periodic signals P _{2 to} P ₈ .

  FIG. 7 is an explanatory diagram showing a basic embodiment (first embodiment) of the timing signal generating circuit of the present invention. In FIG. 7, the timing signal generation circuit 2 includes a periodic signal output circuit 21, a comparison counter 22, a signal generation circuit 23, and a distribution circuit 24.

  In the above-described analog / digital conversion circuit, the capital letter “P” is used as the periodic signal. However, in the following timing signal generation circuit, the small letter “p” is used as the periodic signal. In the above analog / digital conversion circuit, the counter is indicated by capital letter “CNTR”, the frequency conversion circuit is indicated by capital letter “VF”, and the frequency conversion circuit is indicated by capital letter “VCO”. The lower-case letter “cntr” is used to display the frequency conversion circuit using the capital letter “vf” and the frequency conversion circuit using the capital letter “vco”.

Periodic signal output circuit 21 outputs the periodic signal p ₁ ~p _M of M sequence in the frequency f _S.
Comparison counter 22 consists of M comparison counter _{cntr 1 ~cntr M, cntr 1 ~cntr} M is a digital signal D _IN of type a periodic signal p ₁ ~p _M of M sequence corresponding to the size count A full count signal is output when reaches the set value.

Signal generating circuit 23, from M enter the full count signal fc ₁ ~fc _M of the full count signal fc ₁ ~fc _M of M comparison counter 22, for each reference period T _REF, the magnitude of the digital signal D _IN A timing signal T _OUT at a time interval corresponding to the time is generated.

The distribution circuit 24 can set the count values Y and (Y−1) to the M comparison counters. When the distribution circuit 24 sets the count value Y to the _first to k-th counters cntr _{1 to} cntr _k and sets the count value (Y−1) to the remaining counters among the M comparison counters 22, M The periodic signals p _{1 to} p _{M of the} series are sequentially
[Approximate value of one period (T) of periodic signals p _{1 to} p _M ] ÷ M (pieces)
It is input at the delay time interval. The signal generation circuit 23 generates a timing signal having a precision N times that when a timing signal is generated by one counter from the output state of the _M counters 22 (counters cntr _{1 to} cntr _M ).

As shown in the basic embodiment (second embodiment) of FIG. 8, the periodic signal output circuit 21 can be composed of _N voltage / frequency conversion circuits vf _{1 to} vf _N. In FIG. 8, the operation start timing signal with vf ₁ of p ₁ , p ₂ ,..., P _N is generated (see the dotted line in FIG. 8), but the operation is performed as shown in the third embodiment described below. It is also possible for the controller to generate a start timing signal.

  FIG. 9 is an explanatory diagram showing a basic embodiment (third embodiment) of the timing signal generating circuit of the present invention. In FIG. 9, the timing signal generation circuit 2 includes a periodic signal output circuit 21, a comparison counter 22, a signal generation circuit 23, a distribution circuit 24, and a controller 25.

In FIG. 9, the counter 22 includes cntr _{1 to} cntr ₈ . In this embodiment, the resolution of the counters cntr _{1 to} cntr ₈ is 5 bits, and the counter 22 is composed of 8 (2 ³ ) counters cntr _{1 to} cntr _8. Has an 8-bit resolution.

Periodic signal output circuit 21 is replaced with the periodic signal p ₁ ~p _{8 8} series of frequency f _S that receives a reference voltage e _ref as an analog signal corresponding to the voltage e _ref its magnitude varies with time . Specifically, the periodic signal output circuit 21 includes voltage controlled oscillators (vco _{1 to} vco ₈ ). Controller 25, and generates an operation period signal R of operation start timing signal S ₁ to S ₈ and the timing signal generating circuit 2 of vco ₁ ~vco _8.

As shown in FIG. 10, the periodic signal output circuit 21 sequentially outputs eight series of periodic signals p _{1 to} p ₈ .
[Approximate value of one period (T) of periodic signals p _{1 to} p ₈ ] ÷ 8 (pieces)
Generate at the delay time interval.

Eight counters 22 (counters cntr _{1 to} cntr ₈ ) input and count the period signals p _{1 to} p ₈ for each sample period T _SMPL . Counters cntr _{1 to} cntr ₈ have count values of cntr _{1 to} cntr ₆ out of eight counters 12 _when the period of the sample period T _SMPL has expired, and the remaining counters CNTR ₇ and CNTR ₈ are counted. The case where the numerical value is 21 is shown.

The counters cntr _{1 to} cntr ₈ output a full count signal when the count value reaches a set value. The signal generation circuit 23 outputs a timing signal when a full count signal is input from all the cntr _{1 to} cntr ₈ . In the above example, since the value set in cntr _{1 to} cntr ₆ is 22 and the value set in the remaining counters cntr ₇ and cntr ₈ is 21, the signal generation circuit 23 has 22 × 6 + 21 × 2 = 174. A timing signal (for example, duty) corresponding to the numerical value of can be output.

In the present embodiment, vco ₁ ~vco ₈ includes a CR circuit, the periodic signal p ₁ ~p ₈ to vco ₁ ~vco ₈ occurs, as shown in FIG. 11, the charge of C (capacitor) by the input voltage It starts, and when the charging voltage reaches the threshold value, the charging of the capacitor C is finished and the discharging is started, and the charging voltage is returned to the initial voltage as one cycle.

The operation of vco ₁ to vco _{8 in} FIG. 9 will be described with reference to FIG. The operation vco ₁ starts in response to the operation start timing signal S ₁ generated by the controller 25. When the input voltage reaches the threshold value V _T , vco ₁ generates the periodic signal p ₁ .

On the other hand, the controller 25, the charging voltage during a voltage increase in C of the CR circuit of _{vco 1 V T / 4,2V T /} 4,3V T / 4, V T and the charging voltage during voltage falling 3V _T / 4,2V The timing of _T / 4, V _T / 4 is detected. Then, the controller 25 is the charging voltage _{V T / 4,2V T / 4,3V T} / 4, V T, 3V T / 4,2V T / 4, V T / 4 to become the operation start timing timing signal S ₂ , S ₃ , S ₄ , S ₅ , S ₆ , S ₇ , S ₈ are generated (only V ₂ and S ₃ are shown in FIG. 11). When vco ₂ to vco ₈ are driven by these operation start timing signals and the input voltage reaches the respective threshold value V _T , periodic signals P _{2 to} P ₈ (only P ₂ and P ₃ are shown in FIG. 5). ) Is generated. Note that the voltage rise of vco _{1 to} vco ₈ depends on the value of the input voltage during each operation. In Figure 11, there is shown the slope of the voltage rise of vco ₁ ~vco ₃ in β ₁ ~β _3.

FIG. 12 is an explanatory diagram showing another specific embodiment (fourth embodiment) of the timing signal generating circuit 2 of the present invention. The periodic signal output circuit 21 in FIG. 12 includes one voltage controlled oscillator vco and a plurality of delay circuits (dly _{1 to} dly ₇ ). Outputs of the voltage controlled oscillator vco are sequentially delayed by dly _{1 to} dly ₇ to generate periodic signals p _{2 to} p ₈ .

  FIG. 13 is an explanatory diagram showing a basic embodiment (first embodiment) of the control device of the present invention. In FIG. 13, the control device 4 includes the analog / digital conversion circuit 1 described above, the timing signal generation circuit 2 described above, and the digital signal processing circuit 3.

The analog / digital conversion circuit 1 inputs an analog signal _AIN from the controlled object 5 and digitizes it. The digital signal processing circuit 3 applies a digital filter, P control, I control, D control or a combination of these to the digitized signal to generate a digital timing value Q _TMNG .
The timing signal generation circuit 2 generates a control timing signal TMNG based on the digital timing value _QTMNG .

  FIG. 14 is an explanatory diagram showing another basic embodiment (second embodiment) of the control device of the present invention. In FIG. 14, the periodic signal output circuit 11 used in the analog / digital conversion circuit 1 and the periodic signal output circuit 21 used in the timing signal generation circuit 2 are shared.

  FIG. 15 is an explanatory diagram showing a specific embodiment (third embodiment) of the control device of the present invention. In FIG. 15, the control target 5 is a power conversion circuit including a switch element SW, and a power supply 61 is connected to the input side and an addition 62 is connected to the output side. The analog / digital conversion circuit 1 includes an on / off signal generation circuit 51 and receives the output voltage of the power conversion circuit. The timing signal generation circuit 2 can output an on / off timing signal TMNG to the switch element SW of the power conversion circuit 5.

It is explanatory drawing which shows fundamental embodiment (1st Embodiment) of the analog-digital conversion circuit of this invention. It is explanatory drawing shown in fundamental embodiment (2nd Embodiment) of the analog-digital conversion circuit of this invention. It is explanatory drawing which shows specific embodiment (3rd Embodiment) of the analog-digital conversion circuit of this invention. FIG. 4 is a timing diagram of signals generated by the periodic signal output circuit of FIG. 3. FIG. 4 is an explanatory diagram of the operation of the voltage controlled oscillator of FIG. 3. It is explanatory drawing which shows other specific embodiment (4th Embodiment) of the analog-digital conversion circuit of this invention. It is explanatory drawing which shows basic embodiment (1st Embodiment) of the timing signal generation circuit of this invention. It is explanatory drawing which shows fundamental embodiment (2nd Embodiment) of the timing signal generation circuit of this invention. It is explanatory drawing which shows fundamental embodiment (3rd Embodiment) of the timing signal generation circuit of this invention. FIG. 10 is a timing chart showing an output signal of the periodic signal output circuit of FIG. 9. FIG. 10 is an explanatory diagram of the operation of the voltage controlled oscillator of FIG. 9. It is explanatory drawing which shows other specific embodiment (4th Embodiment) of the timing signal generation circuit of this invention. It is explanatory drawing which shows fundamental embodiment (1st Embodiment) of the control apparatus of this invention. It is explanatory drawing which shows other basic embodiment (2nd Embodiment) of the control apparatus of this invention. It is explanatory drawing which shows specific embodiment (3rd Embodiment) of the control apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Analog-digital conversion circuit 2 Timing signal generation circuit 3 Digital signal processing circuit 4 Control apparatus 5 Control object 11 Periodic signal output circuit 12 Counter 13 Digital signal generation circuit 21 Periodic signal output circuit 22 Comparison counter 23 Signal generation circuit 24 Distribution circuit 51 ON / OFF signal generation circuit 61 Power supply 62 Load

Claims (11)

A periodic signal output circuit for inputting a time-varying analog signal and replacing the analog signal with an N-sequence periodic signal having a frequency corresponding to the magnitude of the analog signal;
N pulse counting devices that respectively count the number of pulses of the N-sequence periodic signal;
A digital signal generation circuit that inputs the N series periodic signals and generates a digital signal corresponding to the magnitude of the analog signal for each sample period from these periodic signals;
An analog / digital conversion circuit comprising:
The periodic signal output circuit sequentially outputs the N-sequence periodic signals.
[Approximate value of one period (T) of periodic signal] ÷ N (pieces)
Of the N pulse counters, the first to jth pulse counters of the N pulse counters and the remaining pulse counters of the counter value (X -1) is counted,
The digital signal generation circuit converts the analog signal to the digital signal from the counting state of the N pulse counting devices with N times the resolution when A / D conversion is performed in the sampling period. Analog / digital conversion circuit.   2. The analog / digital conversion circuit according to claim 1, wherein the periodic signal output circuit includes converters that convert the magnitudes of N electrical signals into frequencies, and these converters generate periodic signals. . The converter comprises an integrating circuit, and the periodic signal generated by the converter is:
Until the integration circuit starts operating by the input voltage and ends,
The analog-digital conversion circuit according to claim 2, wherein one period is a period. A periodic signal output circuit for outputting an M-sequence periodic signal of a frequency;
M comparison pulse counting devices that input the M-sequence periodic signal corresponding to the magnitude of the digital signal and output a predetermined signal when the count value reaches the set value;
A signal generation circuit that inputs the M predetermined signals from the M comparison pulse counters and generates a timing signal having a time interval corresponding to the magnitude of the digital signal for each reference period from the predetermined signals;
A timing signal generating circuit comprising:
Of the M comparison pulse counters, the count values are set in the first to kth pulse counters, and the counter values are set in the remaining pulse counters, respectively.
The M-sequence periodic signals are sequentially
[Approximate value of one period (T) of periodic signal] ÷ M (pieces)
By entering at a delay time interval of
The signal generation circuit generates a timing signal having a precision N times that of a timing signal generated by one pulse counting device from the output state of the M pulse counting devices. circuit.   5. The timing signal generation circuit according to claim 1, further comprising a distribution circuit that sets the count value in the M comparison pulse counting devices.   6. The timing signal generation circuit according to claim 5, wherein the periodic signal output circuit includes M converters that convert the magnitude of an electric signal into a frequency, and these converters generate a periodic signal. . The converter comprises an integrating circuit, and the periodic signal generated by the converter is:
Until the integration circuit starts operating by the input voltage and ends,
7. The timing signal generating circuit according to claim 4, wherein one period is a period. An analog / digital conversion circuit according to any one of claims 1 to 3,
A timing signal generation circuit according to any one of claims 4 to 7,
A digital signal processing circuit;
A control device comprising:
The analog-digital conversion circuit digitizes the analog output from the controlled object,
The digital signal processing circuit processes the digitized signal to generate a digital timing value;
The timing signal generation circuit generates a control timing signal based on the digital timing value;
A control device characterized by that.   9. The control apparatus according to claim 8, wherein the periodic signal output circuit used in the analog / digital conversion circuit and the periodic signal output circuit used in the timing signal generation circuit are shared.   The control device according to claim 8 or 9, wherein the digital signal processing circuit performs a digital filter, P control, I control, D control, or a combination thereof. The control object is a power conversion circuit including a switch element,
The analog-digital conversion circuit inputs the output voltage of the power conversion circuit,
The timing signal generation circuit outputs an on / off timing signal to the switch element of the power conversion circuit;
The control device according to claim 8, wherein the control device is a control device.

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