JP2012039273A - Double integration ad converter and integration ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double integration analog-to-digital (AD) converter in which the capacitance of a capacitor in its own integration circuit can be decreased to a size small enough to incorporate the capacitor into an integrated circuit (IC) even when the frequency of a clock pulse generator is comparatively low.SOLUTION: A double integration AD converter includes: a selector for selecting either a measured voltage or a reference voltage which has a polarity opposite to that of the measured voltage and outputting the selected voltage; an integration circuit for integrating the output of the selector; and clock pulse generator for generating clock pulses, and measures the time taken for an integrated value from the integration circuit to reach a predetermined value by counting the clock pulses, and performs analog-to-digital conversion based on the measured time. The double integration AD converter includes: a micro pulse generation circuit that, based on the clock pulses, generates micro pulses having a pulse width smaller than that of the clock pulses; and a switch that is provided between the selector and the integration circuit, is supplied with the micro pulses, and connects the selector to the integration circuit only during the period corresponding to the pulse width of the micro pulses.

Description

  The present invention relates to a double integration AD converter and an integration AD converter having an integration circuit. More specifically, the capacitance of the capacitor of the integration circuit is made small enough to be incorporated in an IC (Integrated Circuit). The present invention relates to a double integration type AD converter and an integration type AD converter.

A configuration example of a conventional double integration AD converter will be described with reference to the drawings. FIG. 6 is a diagram showing a configuration example of a conventional double integration AD converter.
In FIG. 6, the selector SEL has two terminals A and B. A measurement voltage (Vx) is applied to the terminal A. A standard voltage (−Vs) is applied to the terminal B. The standard voltage (−Vs) has a polarity opposite to that of the measurement voltage (Vx). The selector SEL selects either terminal A or B and outputs it.
One end of the resistor R is connected to the output of the selector SEL.
The integrating circuit 10 is a circuit that outputs a time integral value of the input voltage, and inputs the output of the other end of the resistor R.
The integration circuit 10 is composed of, for example, a capacitor C1 and an operational amplifier AMP. The output of the operational amplifier AMP is fed back to the inverting input terminal of the operational amplifier AMP via the capacitor C1. The non-inverting input terminal of the operational amplifier AMP is grounded.
The input part and the output part of the integrating circuit 10 are an inverting input terminal of the operational amplifier and an output part of the operational amplifier, respectively.
The control circuit 1 inputs the output of the integration circuit 10.
The control circuit 1 inputs the clock pulse from the clock pulse generator 2.
The selector SEL determines which of the terminals A and B is to be selected based on a command from the control circuit 1.
The counter 3 inputs the output of the control circuit 1.
The control circuit 1 acquires the count value of the counter 3.

The operation of such a conventional double integration AD converter will be described in detail.
FIG. 7 is a timing chart showing the measurement operation of the apparatus of FIG.
At the start of measurement (T1), the control circuit 1 instructs the selector SEL to select the terminal A.
When the measurement voltage (Vx) is supplied to the integration circuit 10 via the selector SEL and the resistor R, the integration circuit 10 outputs an integration value of the measurement voltage (Vx). The output of the integration circuit 10 drops from the initial value of 0 V at a constant rate according to Vx.
The control circuit 1 outputs the output of the clock pulse generator 2 to the counter 3 after the start of measurement (T1). The counter 3 counts the number of clock pulses input via the control circuit 1.
The control circuit 1 monitors the count value of the counter 3 and switches the input of the selector SEL to the terminal B at (T2) after a predetermined time (N1) has elapsed.
The standard voltage (-Vs) is supplied to the integrating circuit 10 after T2, and the output of the integrating circuit 10 rises at a rate corresponding to -Vs.
When the output of the integrating circuit 10 returns to 0V, the control circuit 1 stops the counter 3 and obtains T3 from the count value at that time.
Here, the control circuit 1 converts the measurement voltage (Vx) from analog to digital in the following manner.

The output of the integrating circuit 10 has a decreasing rate or increasing rate corresponding to the input voltage, and the following relationship is established.
Vx = (N2 / N1) × Vs (1)

However, N1 = T2-T1
N2 = T3-T2

Here, since N1 + N2 = T3−T1, if N1 and Vs are determined in advance, the measurement voltage Vx can be obtained by measuring T3.

  Patent Document 1 describes in detail a configuration example of a double integration AD converter including a selector for selecting a measurement voltage and a standard voltage, an integrator, and the like.

JP-A-4-200016

However, when such a double integration AD converter is built in an IC or the like, if the necessary resolution is ensured and the frequency of the clock pulse generator is low, the capacitance of the capacitor of the integration circuit is There was a problem of becoming too large.
For example, in order to suppress power consumption as much as possible, consider a case where a clock pulse generator having a relatively low frequency of 32.768 kHz as used in a quartz watch or the like is used and the required resolution is 1 mV. Such a condition is found in an AD converter with a built-in IC used for a thermometer of a field device.
The resolution is determined by ΔVc charged in the capacitor during one clock cycle of the clock pulse generator.
ΔVc = Ic / (C × f) (2)
C: Capacitance of capacitor C1
Ic: current flowing into the capacitor C1
f: Output frequency of clock pulse generator

Here, if Ic is 1 uA which is generally used when the IC is built in the IC, the value required for the capacitance C of the capacitor C1 is:

C = 1uA / (1mV × 32.768kHz)
= 31 nF (3)
It becomes.
When a capacitor is built in an IC, its capacitance is normally limited to about several hundred pF, and when a capacitance higher than that is required, an external capacitor is required. However, when a capacitor is externally attached, there is a problem that the cost is increased because a part and the like are also required to have a terminal for drawing a wiring from the IC.

  Therefore, the present invention provides a double integration type AD capable of reducing the capacitance of the capacitor of its own integration circuit to such an extent that it can be incorporated in the IC even when the frequency of the clock pulse generator is relatively low. The purpose is to realize a converter.

In order to solve such a problem, the invention described in claim 1 of the present invention is:
A selector that selects and outputs either the measurement voltage or a standard voltage having a polarity opposite to that of the measurement voltage; an integration circuit that integrates the output of the selector; and a clock pulse generator that generates a clock pulse. In the double integration type AD converter that measures the time until the integrated value of the circuit becomes a predetermined value with the clock pulse and performs analog-to-digital conversion based on the measured time,
A minute pulse generating circuit that generates a minute pulse having a smaller pulse width than the clock pulse based on the clock pulse;
A switch that is provided between the selector and the integration circuit, inputs the minute pulse, and connects the selector and the integration circuit only in a period corresponding to the pulse width;
It is provided with.

Invention of Claim 2 is invention of Claim 1, Comprising:
The integrating circuit includes an operational amplifier and a capacitor, and an output of the operational amplifier is fed back to an inverting input terminal of the operational amplifier through the capacitor, and a non-inverting input terminal of the operational amplifier is grounded.

Invention of Claim 3 is invention of Claim 1 or 2, Comprising:
The minute pulse generation circuit includes a delay circuit and an AND circuit,
The delay circuit inputs the clock pulse, delays and outputs it,
The AND circuit inputs the clock pulse from one input terminal, inputs the output of the delay circuit from the other input terminal, and generates a minute pulse having a pulse width smaller than the pulse width of the clock pulse. Features.

Invention of Claim 4 is invention of Claim 3, Comprising:
The delay circuit is configured by a NOT circuit, and outputs an input with an inverted delay.

The invention described in claim 5
An integration circuit that integrates the measurement voltage input from the input terminal, and a clock pulse generator that generates a clock pulse, and the time until the integration value of the integration circuit reaches a predetermined standard voltage value In an integral AD converter that measures with clock pulses and performs analog-to-digital conversion based on the measured time,
A minute pulse generating circuit that generates a minute pulse having a smaller pulse width than the clock pulse based on the clock pulse;
A switch that is provided between the input terminal and the integration circuit, inputs the minute pulse, and connects the selector and the integration circuit only in a period corresponding to the pulse width;
It is provided with.

  According to the present invention, a selector that selects and outputs either the measurement voltage or a standard voltage having a polarity opposite to the measurement voltage, an integration circuit that integrates the output of the selector, a clock pulse generator that generates a clock pulse, A double integration AD converter that measures the time until the integration value of the integration circuit reaches a predetermined value with the clock pulse, and performs analog-to-digital conversion based on the measured time. A minute pulse generation circuit that generates a minute pulse having a smaller pulse width than the clock pulse based on the pulse, and is provided between the selector and the integration circuit. The minute pulse is input and corresponds to the pulse width. A switch for connecting the selector and the integration circuit only in a period, so that the frequency of the clock pulse generator is compared Even when low, it is possible to realize the electrostatic capacitance of the double integral AD converter capable of reducing to the extent that allows remote IC capacitor of the integration circuit.

It is a block diagram of one Example of this invention. It is a figure which shows timing charts, such as a minute pulse generation circuit and its output signal. It is a figure explaining the operation | movement of the charge of the capacitor | condenser which comprises the apparatus shown in FIG. It is a figure which shows the timing chart at the time of operation | movement of the apparatus shown in FIG. It is a block diagram of the other Example of this invention. It is a block diagram which shows the Example of the conventional double integral type AD converter. It is a figure which shows the timing chart at the time of operation | movement of the apparatus shown in FIG.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those in FIG.
The minute pulse generation circuit 4 is a circuit that inputs the output of the clock pulse generator 2 and outputs H in a period shorter than the high level (H) period of the clock pulse.
The minute pulse generation circuit 4 includes an AND circuit 41 and a delay circuit (for example, NOT circuit) 42 as shown in FIG. As shown in FIG. 2B, an output Y that is inverted and delayed by the NOT circuit 42 with respect to the input signal X is obtained, and an output Z (small pulse) is obtained by the AND circuit 41 that inputs the input signal X and the output Y. Is obtained.
The switch SW is connected between the output of the selector SEL and one end of the resistor R, and receives the output of the minute pulse generation circuit 4, and when the minute pulse is at a high level (H), one end of the selector SEL and the resistor R. And is cut off when the level is low (L).
The integration circuit 20 is composed of, for example, a capacitor C2 and an operational amplifier AMP. The output of the operational amplifier AMP of the integrating circuit 20 is fed back to the inverting input terminal of the operational amplifier AMP via the capacitor C2. The non-inverting input terminal of the operational amplifier AMP is grounded.
The input part and the output part of the integrating circuit 20 correspond to the inverting input terminal of the operational amplifier AMP and the output part of the operational amplifier AMP, respectively.
The control circuit 1 is connected to the output of the integrating circuit 20.

The operation of such a double integration AD converter will be described in detail.
The minute pulse generation circuit 4 receives the clock pulse from the clock pulse generator 2 and generates a minute pulse having a pulse width shorter than the high level (H) period of the clock pulse.
For example, when the minute pulse generation circuit 4 has a configuration as shown in FIG. 2A, the input signal (clock) shown in FIG. 2B is adjusted by adjusting the delay time in the NOT circuit 42. A minute pulse Z having a pulse width (ΔT) shorter than (pulse) X can be generated.
The measurement voltage (Vx) is supplied to the integration circuit 20, and the integration of the voltage is started by the integration circuit 20. Since the switch SW connects between the selector SEL and one end of the resistor R in the interval of the pulse width (ΔT) of the minute pulse, the charging interval of the capacitor C2 is only during ΔT.
FIG. 3 is a diagram for explaining the charging operation of the capacitor C2 of the integrating circuit 20, and shows how the capacitor C2 is charged only in the interval of a minute pulse width (ΔT). The vertical axis represents voltage and the horizontal axis represents time. For reference, FIG. 3 also shows a charging operation of a capacitor having a relatively large capacitance (for example, a capacitor C1 in the case of a conventional device).

FIG. 4 is a timing chart of such a double integration AD converter operation.
At the start of measurement (T1), the control circuit 1 selects the terminal A to be the input of the selector SEL. The output of the integrating circuit 20 drops in a stepped manner from the initial value of 0 V at a constant rate according to Vx. The drop occurs in the interval of the pulse width (ΔT) of the minute pulse.
The control circuit 1 outputs the output of the clock pulse generator 2 to the counter 3 after the start of measurement (T1). The counter 3 counts the number of clock pulses input via the control circuit 1.
The control circuit 1 monitors the count value of the counter 3 and switches the input of the selector SEL to the terminal B at (T2) after a predetermined time (N1) has elapsed.
After T2, a standard voltage (-Vs) is supplied to the integrating circuit 20, and the output of the integrating circuit 20 increases at a constant rate according to -Vs. Since the output of the integration circuit rises only in the interval of the pulse width (ΔT) of the minute pulse, it rises stepwise.
When the output of the integrating circuit 20 returns to 0V, the control circuit 1 stops the counter 3 and obtains T3 from the count value at that time.
Here, when ΔVc is a voltage change caused by charging the capacitor C2 in the interval ΔT, the following is shown.

ΔVc = Ic × ΔT / C ′ (4)

C ′: Capacitance of capacitor C2
Ic: current flowing into the capacitor C2

Assuming that Ic, ΔVc, f are the same values as in the conventional example, from Equation (2),

C ′ = C × ΔT / Tc (5)

Tc: Clock cycle of clock pulse generator (= 1 / f)

That is, the capacitance of the capacitor C2 is “ΔT / Tc” times that of the conventional capacitor C2. For example, when the pulse width ΔT of a minute pulse is adjusted to “1/1000” times the clock cycle output by the clock pulse generator, that is, “Tc / 1000” by a minute pulse generation circuit,

C ′ = C × (Tc / 1000) / Tc (6)
= C / 1000

From equation (3), if the capacitance (C) of C1 used in the conventional example is 31 nF,
C ′ = 31 pF

It becomes.
If the capacitance is 31 pF, even if a relatively low frequency clock pulse generator such as a quartz watch is used in order to suppress power consumption as much as possible, it can be sufficiently realized even when incorporated in an IC. Value.
Therefore, it is not necessary to provide a capacitor externally, and there is no need for a terminal or the like for drawing out the wiring from the IC in terms of component cost, thereby preventing an increase in cost.

  As described above, according to the present invention, the selector SEL that selects and outputs either the measurement voltage or the standard voltage having the opposite polarity to the measurement voltage, the integration circuit 20 that integrates the output of the selector SEL, and the clock pulse A double integration type that has a clock pulse generator 2 to be generated, measures the time until the integration value of the integration circuit 20 reaches a predetermined value with a clock pulse, and performs analog-to-digital conversion based on the measured time In the AD converter, a minute pulse generating circuit 4 that generates a minute pulse having a smaller pulse width than the clock pulse based on the clock pulse, the selector SEL, and the integrating circuit 20 are provided. A switch that connects the selector SEL and the integration circuit 20 only during a period corresponding to the pulse width. Even when the frequency of the generator 2 is relatively low, it is possible to realize a double integration AD converter capable of reducing the capacitance of the capacitor of the integration circuit 20 to such an extent that it can be incorporated in the IC. it can.

The same effect can be obtained for an integrating AD converter that performs analog-to-digital conversion by integrating the measured voltage by the integrating circuit and measuring the time until it exceeds the reference voltage.
In this case, the configuration is as shown in FIG. 5 (the same components as those in FIG. That is, the measurement voltage Vx is input to the switch SW. The control circuit 1 receives the reference voltage Vref and compares the reference voltage Vref with the output of the integrating circuit 20. A reset circuit (not shown) for discharging electric charge is attached to the capacitor C2.
Also with this configuration, the voltage change ΔVc due to charging of the measurement voltage Vx to the capacitor C2 is the same as in the case of the double integration AD converter described in the embodiment.
Therefore, also in the integration type AD converter, it is possible to reduce the capacitance of the capacitor to such an extent that it can be built in the IC.

DESCRIPTION OF SYMBOLS 1 Control circuit 2 Clock pulse generator 3 Counter 20 Integration circuit 4 Minute pulse generation circuit 41 AND circuit 42 Delay circuit (NOT circuit)
SEL selector SW switch AMP operational amplifier C2 capacitor

Claims (5)

A selector that selects and outputs either the measurement voltage or a standard voltage having a polarity opposite to that of the measurement voltage; an integration circuit that integrates the output of the selector; and a clock pulse generator that generates a clock pulse. In the double integration type AD converter that measures the time until the integrated value of the circuit becomes a predetermined value with the clock pulse and performs analog-to-digital conversion based on the measured time,
A minute pulse generating circuit that generates a minute pulse having a smaller pulse width than the clock pulse based on the clock pulse;
A switch that is provided between the selector and the integration circuit, inputs the minute pulse, and connects the selector and the integration circuit only in a period corresponding to the pulse width;
A double integration type AD converter characterized by comprising:   The integration circuit includes an operational amplifier and a capacitor, and an output of the operational amplifier is fed back to an inverting input terminal of the operational amplifier via the capacitor, and a non-inverting input terminal of the operational amplifier is grounded. 2. The double integration AD converter according to 1. The minute pulse generation circuit includes a delay circuit and an AND circuit,
The delay circuit inputs the clock pulse, delays and outputs it,
The AND circuit inputs the clock pulse from one input terminal, inputs the output of the delay circuit from the other input terminal, and generates a minute pulse having a pulse width smaller than the pulse width of the clock pulse. The double integration AD converter according to claim 1 or 2, characterized in that:   4. The double integration type AD converter according to claim 3, wherein the delay circuit is configured by a NOT circuit and outputs an input with an inverted delay. An integration circuit that integrates the measurement voltage input from the input terminal, and a clock pulse generator that generates a clock pulse, and the time until the integration value of the integration circuit reaches a predetermined standard voltage value In an integral AD converter that measures with clock pulses and performs analog-to-digital conversion based on the measured time,
A minute pulse generating circuit that generates a minute pulse having a smaller pulse width than the clock pulse based on the clock pulse;
A switch that is provided between the input terminal and the integration circuit, inputs the minute pulse, and connects the selector and the integration circuit only in a period corresponding to the pulse width;
An integrated AD converter characterized by comprising:

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