JP2009118362A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accuracy of an A/D converter by a voltage to frequency conversion method. <P>SOLUTION: The A/D converter includes a voltage to frequency conversion circuit having a voltage controlled oscillator 24 with two equivalent saw tooth wave generating circuits 18A, 18B and a switching circuit 19 for alternately switching two saw tooth wave generating circuits 18A, 18B. Preferably, the A/D converter includes a first voltage controlled oscillator for outputting a first period cyclical signal and second voltage controlled oscillator for outputting a second period cyclical signal that not only is different from the first period but also keeps a predetermined ratio with the first period. Further, the A/D converter, calculates high order bits of a digital signal corresponding to an input analog signal based on the first cyclical signal included in a sampling period and then low order bits of the digital signal based on the number of waves of the cyclical signal to be included during the period from when the sampling signal is activated until the time when the phases of the first and second cyclical signals are coincided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an AD converter. More specifically, the present invention relates to an A / D conversion device including a voltage-frequency conversion circuit.

  Non-Patent Document 1 discloses an A-D converter (analog-digital converter) using voltage-frequency conversion (hereinafter referred to as VF (Voltage-Frequency) conversion). In this type of A / D converter, the frequency of the pulse signal output from the VF converter varies depending on the magnitude of the input voltage as an analog signal, and the number of pulses included in the pulse signal is used as a counter. The digital signal is generated by counting.

  There has been proposed a technique for realizing an A / D converter using voltage-frequency conversion, which can perform A / D conversion with high accuracy without increasing the conversion frequency (Patent Document 1). ). In the technique of Patent Document 1, two VCOs are provided, and a VF conversion value less than the period of the main VCO is obtained by using a period difference between both VCOs. The counter 4 counts the number of pulses of the pulse signal output from the main VCO, thereby generating the upper bits of the digital signal. On the other hand, for the lower bits, the third register 10 and the second and third subtracters 11 and 12 make the phase coincidence point of the output of the main VCO and the sub VCO from the activation point of the current sampling signal Ps every sampling period. Is generated by calculating the phase difference from the beginning of the sampling period to the first pulse generation within the sampling period of the main VCO based on the number of pulses of the output of the main VCO included in

  On the other hand, Non-Patent Document 2 describes a technique of a ΔΣ-AD converter using a current-controlled oscillator. The technology of Non-Patent Document 2 is a multivibrator current control type oscillator that obtains pulses by alternately charging input currents to capacitors C1 and C2.

  Patent Document 2 describes a technique for generating a sawtooth voltage. The sawtooth generation circuit disclosed in Patent Document 2 is alternately charged / discharged according to the comparison result of the voltage source that determines the reference voltage, the comparison circuit that compares the reference voltage of the voltage source and the output voltage of the sawtooth, and the comparison circuit. , A constant current circuit that charges the two capacitors with a current of a magnitude that determines the oscillation frequency of the sawtooth, a switch circuit that forms a discharge circuit for each of the two capacitors, and two And a switch circuit connected to each of the constant current circuits so as to charge the capacitors alternately. A sawtooth voltage having a predetermined amplitude can be generated from the output terminal according to the upper and lower reference voltages.

Japanese Patent No. 3701668 JP 2004-282352 A ANALOG DEVICES AN-277 APPLICATION NOTE, III INSTRUMENTATION APPLICATIONS, Analog-to-Digital Conversion, Fig. 9, Internet <URL: http: //www.analog.com/UploadedFiles/Application_Notes/511072672AN277.pdf> Proceedings of the IEICE General Conference, Vol. 2000, Electronics, No. 2 (20000307) p. 135, The Institute of Electronics, Information and Communication Engineers

  In the voltage-frequency conversion type AD converter, the resolution is determined by the frequency, and the linearity of the voltage-frequency characteristic of the voltage controlled oscillator is important. Even if the voltage-frequency characteristic is not a straight line, it can be corrected if the characteristic is known in advance. However, a circuit for the correction process is required, and the response is delayed by the correction process. With the technique of Patent Document 1, the resolution can be improved without increasing the frequency of the oscillator. However, the linearity of the voltage-frequency characteristic of the voltage controlled oscillator remains important.

  This invention is made | formed in view of such a condition, The objective is to improve the precision of the AD converter of a voltage-frequency conversion system.

  To achieve the above object, an AD converter according to a first aspect of the present invention includes two equivalent sawtooth wave generation circuits and a switch circuit that alternately switches the two sawtooth wave generation circuits. A voltage-frequency conversion circuit having a voltage controlled oscillator is provided.

  According to the present invention, the linearity of voltage-frequency conversion can be improved. As a result, the accuracy of the voltage-frequency conversion type AD converter can be improved.

  Preferably, the voltage-frequency conversion circuit is different from the first voltage-controlled oscillator that outputs a first periodic signal that oscillates in a first period, the first period, and the first And a second voltage-controlled oscillator that outputs a second periodic signal that oscillates in a second period that maintains a constant ratio with the period, wherein the first voltage-controlled oscillator is free-running by the self-running. The oscillation of the first periodic signal is started, and the second voltage-controlled oscillator starts oscillating the second periodic signal in response to the activation of the sampling signal indicating the sampling period of AD conversion, Based on the wave number of the first periodic signal included in the sampling period, upper bit calculating means for calculating upper bits of a digital signal corresponding to an analog signal that is an input; from the activation time of the sampling signal, First And low-order bit calculation means for calculating low-order bits of the digital signal based on the wave number of the first or second periodic signal included until the phase of the second periodic signal matches. .

  As a result, it is possible to perform AD conversion with high accuracy without increasing the conversion frequency.

  Preferably, the input voltages of the first and second voltage controlled oscillators are each given by the same voltage divided by resistance.

  As a result, the periodic ratio of the two periodic signals can be kept constant regardless of the voltage value of the input signal, so that the accuracy of A-D conversion can be improved.

  Preferably, in the voltage-controlled oscillator having the two sawtooth wave generation circuits, the switch circuit is configured by a flip-flop using an inverting circuit having a single configuration of an N-channel transistor.

  By using an inverting circuit having a single configuration of an N-channel transistor, the switching operation of the two sawtooth waves of the voltage controlled oscillator can be speeded up. As a result, AD conversion with better frequency characteristics can be obtained.

  Preferably, in the voltage controlled oscillator having the two sawtooth wave generation circuits, the capacitor is connected in series between the capacitor that performs charge / discharge operation according to the result of comparison with the reference voltage of the sawtooth voltage and the discharge voltage terminal. And a transistor for compensation.

  This makes it possible to improve the linearity of the voltage-frequency characteristics of the voltage controlled oscillator by slightly increasing the discharge reference voltage of the capacitor that performs the charge / discharge operation and correcting the time for switching the two sawtooth waves. .

  Preferably, in the voltage controlled oscillator having the two sawtooth wave generation circuits, the switch circuit includes a flip-flop of an inverting circuit loop.

  As a result, the circuit configuration of the voltage controlled oscillator can be simplified, the number of gates can be reduced, and the switching operation of the two sawtooth waves of the voltage controlled oscillator can be accelerated.

  According to the A / D conversion device of the present invention, the accuracy of the voltage-frequency conversion type A / D conversion device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an A / D conversion device 20 according to an embodiment of the present invention. As shown in FIG. 1, the A / D converter 20 includes an input terminal 21 for inputting an analog signal, a voltage controlled oscillator 24 (also referred to as a VCO (Voltage Controlled Oscillator)), a counter 25, a register 26, It comprises a sampling clock generator 23 and an output terminal 22 for outputting a digital value. The AD converter 20 outputs from the output terminal 22 a digital value of a level corresponding to the analog signal input from the input terminal 21 for each sampling period.

  The sampling clock generator 23 generates a sampling clock that is a periodic signal having a sampling period T that is a reference for A-D conversion. The sampling period T is a predetermined period for converting an analog signal into a digital value.

  The voltage controlled oscillator 24 generates a periodic signal having a frequency proportional to the voltage of the input signal. The counter 25 counts the wave number of the periodic signal output from the voltage controlled oscillator 24 every sampling period T, and outputs the counted value (digital value) to the register 26. The register 26 holds the input digital value during the sampling period T and outputs it to the output terminal 22. As a result, a digital value proportional to the voltage for each sampling clock of the input analog signal is output.

  The resolution of the AD converter 20 is determined by the frequency of the periodic signal generated by the voltage controlled oscillator 24 with respect to the input voltage. The higher the frequency for the same input voltage, the higher the resolution. In order to correctly convert an analog signal into a digital value, the frequency of the periodic signal generated by the voltage controlled oscillator 24 needs to be proportional to the input voltage. If the input voltage-frequency characteristic deviates from the straight line, the accuracy of A-D conversion decreases.

  FIG. 2 is a block diagram showing an example of the configuration of the voltage controlled oscillator 24 according to the first embodiment. The voltage controlled oscillator 24 generates a sawtooth wave having a period corresponding to the input voltage of the input terminal 27, generates a pulse (periodic signal) for each period of the sawtooth wave, and outputs the pulse to the output terminal 28. The basic part for generating a sawtooth wave is a current source 29, two capacitors 32A and 32B, switches 31A and 31B for connecting the capacitors 32A and 32B to the current source 29, and a capacitor connected to a discharge potential (ground 34). It comprises switches 33A and 33B. The characteristics of the capacitors 32A and 32B are the same. The voltage controlled oscillator 24 includes a constant voltage source 35, a comparator 36, and a T-flip flop 37. In addition, two comparators 38A and 38B connected to the input terminal 27 and AND circuits 39A and 39B are provided.

  The voltage controlled oscillator 24 includes two sawtooth wave generation circuits 18A and 18B. That is, one sawtooth wave generation circuit 18A is formed by the current source 29, the capacitor 32A, the switches 31A, 33A, and the ground 34. Similarly, the current source 29, the capacitor 32B, the switches 31B, 33B, and the ground 34 are already used. One sawtooth wave generation circuit 18B is formed. In FIG. 2, since the current source 29 and the ground 34 are common, they are shown outside the frame showing the sawtooth wave generation circuits 18A and 18B for easy understanding.

  When the switch 31A is closed and the switch 31A is closed and the capacitor 32A is charged from the current source 29, the terminal voltage V1 increases in proportion to the amount of charge stored in the capacitor 32A. When the switch 31A is opened and the switch 33A is closed, the charge of the capacitor 32A flows to the ground 34, and the capacitor is discharged. Since the discharge current is larger than the charge current, the discharge time is shorter than the charge time. As a result, the terminal voltage V1 of the capacitor 32A exhibits a sawtooth wave. Similarly, the capacitor 32B is charged by closing the switch 31B while the switch 33B is opened, and discharging the switch 31B by closing the switch 33B, so that the terminal voltage V2 of the capacitor 32B becomes a sawtooth waveform. The voltage controlled oscillator 24 uses two sawtooth wave generation circuits 18A and 18B alternately to generate a continuous sawtooth wave that is independent of the discharge time.

The constant voltage source 35, the comparator 36, the T-flip-flop 37, the comparators 38A and 38B, and the AND circuits 39A and 39B constitute a switch circuit 19 that switches between the two sawtooth wave generation circuits 18A and 18B. The current source 29 side of the switches 31A and 31B is connected to one input of the comparator 36. The other input of the comparator 36 is connected to the constant voltage source 35. Voltage of the constant voltage source 35 is _{V H.} The output of the comparator 36 is connected to a T-flip flop 37. The comparator 36 compares the inputs, and outputs 0 when the switches 31A and 31B are smaller than the voltage VH, and outputs 1 when the voltage is equal to or higher than the voltage VH. The T-flip-flop 37 switches the state of the output Q from 1 to 0 or from 0 to 1 every time one pulse is input to the terminal T.

  The output Q is connected to the switch 31A and the AND circuit 39B. In FIG. 2, notQ, which is an inversion of the output Q indicated by an overlined Q, is connected to the switch 31B and the AND circuit 39A. Therefore, the switch 31A and the switch 31B are alternately turned ON, and when one is closed, the other is open.

  The terminals of the capacitors 32A and 32B are connected to one input of the comparators 38A and 38B, respectively. The other inputs of the comparators 38A and 38B are connected to the input terminal 27. The voltage VH of the constant voltage source 35 is set higher than the maximum input voltage. The outputs of the comparators 38A and 38B are connected to the other inputs of the AND circuits 39A and 39B, respectively. The outputs of the AND circuits 39A and 39B are connected to the switches 33A and 33B, respectively. The comparators 38A and 38B output 0 when the terminal side of the capacitors 32A and 32B is lower than the input voltage, respectively, and 1 when the input voltage is equal to or higher than the input voltage.

  The AND circuits 39A and 39B output 1 when both inputs are 1, and output 0 otherwise. Accordingly, the switch 33B is closed only when both Q and the output of the comparator 38B are 1. Further, the switch 33A is closed only when both the notQ and the output of the comparator 38A are 1.

  The current source 29 side of the switches 31A and 31B is connected to the pulse generator 30. The pulse generator 30 generates a pulse at the falling edge of the sawtooth wave and outputs it to the output terminal 28.

  Next, the operation of the voltage controlled oscillator 24 will be described. First, it is assumed that the output Q of the T-flip flop 37 is 1. Since the output Q is 1, the switch 31A is closed and the switch 31B is open. Since notQ is 0, the switch 33A is open. In this state, the capacitor 32A is charged by the current from the current source 29, and the terminal voltage rises. At that time, if the terminal voltage of the capacitor 32B is higher than the input, the switch 33B is closed and the capacitor 32B is discharged.

  When the terminal voltage of the capacitor 32A rises and Vout becomes equal to or higher than the voltage VH, the output of the comparator 36 becomes 1, and the output Q of the T-flip flop 37 becomes 0. This time, the switch 31A is opened and the switch 31B is closed. Then, the switch 33B is opened. At this time, the output of the comparator 36 returns to zero. In this state, the capacitor 32B is charged by the current from the current source 29, and the terminal voltage rises.

  Since the terminal voltage of the capacitor 32A is VH or higher and higher than the input voltage VL, the output of the comparator 38A is 1. Since notQ is 1 and the output of the AND circuit 39A becomes 1, and the switch 33A is closed, the capacitor 32A is discharged. When the terminal voltage of the capacitor 32A becomes lower than the input voltage VL, the output of the comparator 38A becomes 0, the output of the AND circuit 39A becomes 0, and the switch 33A opens. Therefore, the terminal voltage of the capacitor 32A is held when it becomes lower than the input voltage VL.

  When the terminal voltage of the capacitor 32B rises and Vout becomes equal to or higher than the voltage VH, the output of the comparator 36 becomes 1, and the output Q of the T-flip flop 37 becomes 1. Then, it returns to the initial state, the switch 31B is opened, and the switch 31A is closed. At this time, the output of the comparator 36 returns to zero. In this state, the capacitor 32A is charged by the current from the current source 29, and the terminal voltage rises.

  Since the terminal voltage of the capacitor 32B is VH or higher and higher than the input voltage VL, the output of the comparator 38B is 1. Since Q is 1 and the output of the AND circuit 39B becomes 1, and the switch 33B is closed, the capacitor 32B is discharged. When the terminal voltage of the capacitor 32B becomes lower than the input voltage VL, the output of the comparator 38B becomes 0, the output of the AND circuit 39B becomes 0, and the switch 33B opens. Therefore, the terminal voltage of the capacitor 32B is held when it becomes lower than the input voltage VL.

  By repeating the above operation, the current source 29 side of the switches 31A and 31B exhibits a sawtooth wave having a lower potential VL and an upper potential VH. Since the charging current is constant depending on the current of the current source 29, the speed at which the terminal voltages of the capacitors 32A and 32B rise is constant. When the input voltage VL is high, the time until the terminal voltages of the capacitors 32A and 32B change from VL to VH is short, and when the input voltage VL is low, the time is long. Therefore, the frequency of the sawtooth wave is proportional to the input voltage VL.

  The pulse generator 30 generates a pulse at the falling edge of the sawtooth wave. Since the characteristics of the capacitors 32A and 32B are the same and the current source 29 is common, the shape of the sawtooth wave is the same for both. That is, the period of both sawtooth waves is equal. Therefore, the voltage controlled oscillator 24 outputs a pulse having a frequency proportional to the input voltage.

  FIG. 3 is a block diagram illustrating an example of a different configuration of the voltage controlled oscillator 24 according to the first embodiment. The voltage controlled oscillator 24 includes two sawtooth wave generation circuits 18A and 18B. That is, the voltage-current amplifier 17, which is a current source, the capacitor 32A, the switches 31A and 33A, and the ground 34 form one sawtooth wave generation circuit 18A. Similarly, the voltage-current amplifier 17, the capacitor 32B, and the switch Another sawtooth wave generation circuit 18B is formed by 31B, 33B and ground 34. In FIG. 3, since the voltage-current amplifier 17 and the ground 34 are common, they are shown outside the frame showing the sawtooth wave generation circuits 18A and 18B for easy understanding. The voltage-current amplifier 17 which is a current source generates a current proportional to the voltage at the input terminal 27.

  In the voltage controlled oscillator 24 of FIG. 3, the current for charging the capacitors 32A and 32B is not constant but is proportional to the input voltage. The peak potential (VH) of the sawtooth wave is determined by the switching voltages of the transistors 41A and 41B. The inverting circuits 42 and 43 constitute an inverting circuit loop. For switching between the sawtooth wave generation circuits 18A and 18B, an inverting circuit loop is used instead of the T-flip flop 37 of FIG.

  When the terminal voltages V1 and V2 of the capacitors 32A and 32B become higher than the switching voltage (VH) of the transistors 41A and 41B, the transistors 41A and 41B are turned on to bring the terminal of the inverting circuit loop to a low potential. The potential of is switched. Both sides of the inverting circuit loop correspond to the outputs Q and notQ of the T-flip flop 37 in FIG.

  The charge current is proportional to the input voltage, and the peak voltage VH and the discharge voltage (ground 34) for switching the capacitors 32A and 32B are constant. Therefore, if the input voltage is high, the capacitor is charged faster and reaches the peak voltage faster and switches. If it is low, it will be charged slowly and the peak voltage will be slow to reach. Therefore, the sawtooth period is inversely proportional to the input voltage, and the frequency is proportional to the input voltage.

  In the circuit of FIG. 2, since the charging current is constant, the rising slope of the sawtooth wave is the same angle, and when the input voltage changes, the sawtooth wave changes in a similar shape. In the circuit of FIG. 3, since the charging current is proportional to the input voltage and the peak voltage is constant, the height of the sawtooth wave is constant and the period changes. FIG. 4 shows the difference between the sawtooth waves of the two voltage controlled oscillators 24 by focusing on one sawtooth wave generation circuit. FIG. 4A representatively shows the sawtooth waveform at an input voltage of two circuits. FIG. 4B shows a sawtooth waveform when the input voltage is doubled in the voltage controlled oscillator 24 of FIG. FIG. 4C shows a sawtooth waveform when the input voltage is doubled in the voltage controlled oscillator 24 of FIG. As shown in FIG. 4B, the sawtooth wave changes in a similar manner in the circuit of FIG. As shown in FIG. 4C, in the circuit of FIG. 3, the sawtooth wave has a constant height and the cycle changes. In either case, a periodic signal having a frequency proportional to the input voltage is generated.

  FIG. 5 is a time chart showing an example of pulse signal generation according to the first embodiment. It is shown that the capacitor to be charged is switched each time the state of the output Q of the T-flip flop 37 is switched. The voltage of Vout, which is the input of the pulse generation circuit, is a sawtooth wave consisting only of the charging time, excluding the discharging time of the capacitor.

  While the charging currents of the capacitors 32A and 32B are constant during the charging time, the discharging current is not constant, and the discharging time is not proportional to the potential difference between the power supply voltage VH and the input voltage VL. It also changes depending on the ON resistance of the discharging switch. That is, the falling times of the sawtooth waves of V1 and V2 in FIG. 5 are not proportional to the voltage. Therefore, when the discharge period of the capacitor is included in the output period of the voltage controlled oscillator (VCO) 24, the frequency is not exactly proportional to the input voltage. In the present embodiment, since the discharge time of the capacitor is not included in the cycle of the VCO 24 output, the frequency of the periodic signal is proportional to the input voltage, and the voltage-frequency characteristic is close to a straight line. As a result, the accuracy of A-D conversion is improved.

  In the circuit of FIG. 3, since an inverting circuit loop is used for the flip-flop, the number of gates is small and the switching operation is fast. Therefore, the switching operation of the two sawtooth wave generation circuits 18A and 18B becomes faster. As a result, the linearity of the voltage-frequency characteristic of the voltage controlled oscillator 24 is improved.

(Embodiment 2)
The second embodiment is an AD conversion apparatus 20 using VF conversion, which includes two VCOs, and uses a difference between both VCOs to obtain a VF conversion value less than the period of the main VCO. A-D conversion is performed with high accuracy.

  FIG. 6 is a block diagram of the AD conversion apparatus 20 according to Embodiment 2 of the present invention. As shown in FIG. 6, this A-D converter 20 is an A-D converter 20 that converts an analog signal voltage Vin input to an input terminal 21 into a digital signal, and oscillates at a period Tbase. A voltage controlled oscillator 1 (hereinafter referred to as BASE-VCO (Voltage Controlled Oscillator)) that outputs a pulse signal and a voltage controlled oscillator 2 (hereinafter referred to as JAW-VCO) that outputs a pulse signal that oscillates at a period Tjaw different from the period Tbase. ). The BASE-VCO 1 and the JAW-VCO 2 have the same configuration as that of the voltage controlled oscillator 24 used in the first embodiment. That is, two equivalent sawtooth wave generation circuits 18A and 18B are provided, respectively, and two sawtooth wave generation circuits 18A and 18B are alternately used to generate a continuous sawtooth wave irrelevant to the discharge time.

  The AD converter 20 includes a phase difference determination circuit 3, a counter 4 and a first register 5 that are higher-order digit calculation units, an upper and lower digit synthesis unit 6, a second register 7, and a first subtractor. 8, an operation control circuit 9, a third register 10 which is a lower digit calculation unit, and second and third subtractors 11 and 12. Phase difference determination circuit 3, upper digit calculation unit (counter 4 and first register 5), upper and lower digit synthesis unit 6, second register 7, first subtractor 8, operation control circuit 9, and lower digit calculation unit (first digit) The three registers 10, the second and third subtractors 11, 12) cooperate to function as a digital value calculation unit.

  Also in the present embodiment, basically, the digital signal is obtained by counting the number of pulses of the pulse signal output from the BASE-VCO 1 by the counter 4 as in the case of the AD converter 20 of the first embodiment. Generate. An output signal from the BASE-VCO 1 is input to the clock input terminal T of the counter 4, and the counter 4 can count the number of oscillations of the BASE-VCO 1.

  That is, the input voltage Vin, which is an analog signal, is applied to the BASE-VCO 1 as a voltage control signal for the BASE-VCO 1. Then, the cycle Tbase of the BASE-VCO 1 is controlled by the input voltage Vin.

  Since the BASE-VCO 1 operates at a higher speed as the input voltage Vin is higher, the cycle Tbase becomes smaller. If the period Tbase is small, the number of pulses of the pulse signal output from the BASE-VCO 1 per unit time increases. On the other hand, since the BASE-VCO 1 operates at a lower speed as the input voltage Vin is lower, the cycle Tbase becomes larger. If the period Tbase is large, the number of pulses of the pulse signal output from the BASE-VCO 1 per unit time decreases.

Therefore, if the counter 4 counts the number of pulses of the pulse signal output from the BASE-VCO 1 during a predetermined period (= 1 sampling period) generated by the sampling clock generator 13, the magnitude of the count value is an analog signal. The magnitude of the input voltage Vin is a value, and the count value itself corresponds to the converted value of the input voltage Vin, which is an analog signal, into a digital signal. If this count value is output, AD conversion using VF conversion can be realized. The resolution of the AD converter 20 is obtained as AD resolution = log ₂ (oscillation frequency / sampling frequency of BASE-VCO1) using the oscillation frequency and sampling frequency of BASE-VCO1. For example, when the oscillation frequency of BASE-VCO 1 is 50 [MHz] and the sampling frequency is 44 [kHz], the resolution is calculated as 10 bits.

  However, as described in the above problem, when the number of pulses included in the pulse signal is small by simply counting the pulse signal of the BASE-VCO 1, the count value in the counter 4 hardly changes. High-precision A / D conversion cannot be performed.

  More specifically, for example, when the input voltage Vin is 4 [V] or more and less than 5 [V], the number of pulses of the pulse signal output from the BASE-VCO 1 during one sampling period is four, and the input voltage Vin Is 3 [V] or more and less than 4 [V], assuming that the number of pulses in one sampling period is three, even if the input voltage Vin is 4.2 [V], it is 4.8 [V]. Even so, the number of pulses counted is four, and the number of pulses counted is three regardless of whether the input voltage Vin is 3.5 [V] or 3.9 [V]. It is said that.

  In other words, when A / D conversion is performed by counting the number of pulses, it is impossible to distinguish even the fractional part of the number of pulses to be counted. Therefore, in analog voltages such as 4.2 [V] and 4.8 [V] In any case, a numerical value of “4” is output in the converted digital signal in spite of slight differences. Of course, the conversion frequency of VF conversion is increased, that is, the oscillation frequency of the BASE-VCO 1 is increased (in the case of the above numerical example, for example, 40 to 49 pulses when the frequency is 4 [V] or more and less than 5 [V]) A-D conversion can be made more accurate (in the case of the above numerical example, for example, 42 and 48 can be distinguished). However, the conversion frequency is not easily increased due to limitations on circuit manufacturing process conditions, allowable frequency jitter values, and the like.

  Therefore, in the present embodiment, JAW-VCO 2 having a period difference with respect to BASE-VCO 1 is prepared, and the phase difference between both VCO outputs is measured to obtain a VF conversion value less than the period Tbase of BASE-VCO 1. . Increasing the conversion accuracy in AD conversion using VF conversion means measuring the fractional part of the count that cannot be counted by the number of pulses of the pulse signal output from BASE-VCO1. In this embodiment, JAW-VCO2 is employed for the fractional part measurement of the number of pulses.

  Note that the input voltage Vin as an analog signal also functions as a voltage control signal for the JAW-VCO 2. The period Tjaw of JAW-VCO 2 is also controlled by the input voltage Vin. Here, assuming that the ratio of the period Tbase to the period Tjaw is A: B (A ≠ B), the values of the periods Tbase and Tjaw are controlled by the input voltage Vin while maintaining the ratio of A: B.

  In order to keep the ratio of the period of BASE-VCO1 and the period of JAW-VCO2 constant, for example, as shown in FIG. 6, the potential difference between the input terminal 21 and the ground 16 is input to one VCO by resistors 14 and 15. Is divided into resistors and input to the other VCO. Even if the input voltage changes, the ratio of the voltages input to the two VCOs is constant. If the VCO characteristics are the same, the cycle ratio is kept constant. In addition, a fixed ratio input may be generated by an amplifier circuit.

  In the present embodiment, the upper bits of the digital signal to be output are calculated based on the number of pulses of the pulse signal output from BASE-VCO 1 during one sampling period. On the other hand, for the lower bits of the digital signal, the period from the activation of the sampling signal Ps indicating the sampling period of the digital signal to the time when the phase of the pulse signal of the BASE-VCO1 and the phase of the pulse signal of the JAW-VCO2 match. Is calculated based on the number of pulses of the BASE-VCO1 or JAW-VCO2 pulse signal.

  If the periods Tbase and Tjaw are set to different values, the phases of the oscillation outputs of the two VCOs BASE-VCO1 and JAW-VCO2 coincide with each other at regular intervals. Let this interval be M. About BASE-VCO1, the oscillation of the output pulse signal is started by self-running. On the other hand, the JAW-VCO 2 starts to oscillate as the sampling signal Ps is activated. That is, the JAW-VCO 2 starts oscillating simultaneously with the activation of the sampling signal Ps, and the activation point of the sampling signal Ps is set as the oscillation starting point of the JAW-VCO 2.

  FIG. 7 is a timing chart showing an example of a BASE-VCO1 pulse signal and a JAW-VCO2 pulse signal. In FIG. 7, the activation time of the sampling signal Ps (that is, the oscillation start point of JAW-VCO2) is just at the same time as the rise of a pulse of BASE-VCO1, and the number of pulses of BASE-VCO1 is 9 The case where the number of pulses of JAW-VCO2 is 8 is shown. In this case, the ratio A: B between the period Tbase and the period Tjaw is 8: 9.

  FIG. 8 is a timing chart showing another example of the BASE-VCO1 pulse signal and the JAW-VCO2 pulse signal. FIG. 8 also shows a case where the activation time of the sampling signal Ps (that is, the oscillation start point of JAW-VCO2) is just at the same time as the rise of a pulse of BASE-VCO1, but in FIG. In this example, the number of JAW-VCO2 pulses is 9 with respect to 8 pulses. In this case, the ratio A: B between the period Tbase and the period Tjaw is 9: 8.

  In the present embodiment, the period difference between BASE-VCO1 and JAW-VCO2 may be set so that the period Tjaw of JAW-VCO2 becomes large as shown in FIG. 7, or as shown in FIG. Alternatively, the BASE-VCO 1 cycle Tbase may be set to be large. However, if the period Tjaw of JAW-VCO2 is made larger than the period Tbase of BASE-VCO1, detection of the phase difference between the two VCO outputs becomes easier. Therefore, in the following, as shown in FIG. The case where the number of JAW-VCO2 pulses is 8 with respect to the number 9 will be described as an example.

  FIG. 9 is a timing chart for explaining the principle that a VF conversion value less than the cycle Tbase is obtained by using BASE-VCO1 and JAW-VCO2.

  The digital value to be generated by the AD converter 20 using the VF conversion is the total number of pulses including an integer and a decimal number of pulses from the BASE-VCO 1 within one sampling period of the sampling signal Ps. is there. Referring to FIG. 9, during the first sampling period of the sampling signal Ps, the first pulse generation of the BASE-VCO 1 within the sampling period from the activation point of the sampling signal Ps (ie, the beginning of the sampling period) ( Decimal (i) until BASE-VCO1 rising edge of “2” pulse), first generation of BASE-VCO1 pulse within sampling period (rising edge of “2nd” pulse of BASE-VCO1) The number of BASE-VCO1 pulses from the start of the sampling period to the start of the next sampling period (positive number, ii), and the last pulse generation of the BASE-VCO1 within the sampling period (rising of the “5th” pulse of the BASE-VCO1 3 points including the decimal point (iii) from the time point to the start of the next sampling cycle. It can be seen that.

  In FIG. 9, the positive number ii can be obtained by counting the number of BASE-VCO 1 pulses as in the prior art. On the other hand, according to the present invention, it is possible to count even the fractions i and iii in FIG.

  The portion i in FIG. 9 has a period of Tdiff × 5 as an example, where Tdiff is the period difference between the period Tbase and the period Tjaw. The portion iii has a period of Tdiff × 7 as an example. The period difference Tdiff satisfies the relationship of Tbase = A × Tdiff = 8 × Tdiff and Tjaw = B × Tdiff = 9 × Tdiff, as shown in FIG. Therefore, the portion i in FIG. 9 is a period of 5/8 of the period Tbase. 9 is a period of Tdiff × 7, that is, a period of 7/8 of the period Tbase.

  If all the parts i to iii in FIG. 9 are added, the value becomes the total number of pulses including an integer and a decimal number of pulses from the BASE-VCO 1 within one sampling period. That is, this value becomes an AD conversion value with higher accuracy. In the first sampling period in FIG. 9, since i part = 5/8, ii part = 3, and iii part = 7/8, the sum of i to iii is positive number 4 and decimal number 4/8. It becomes. Similarly, in the second sampling period in FIG. 9, the i part = 1/8, the ii part = 4, and the iii part = 4/8, so that the total of i to iii is a positive number 4. The decimal number is 5/8. Similarly, in the third sampling period in FIG. 9, the i part = 4/8, the ii part = 4, and the iii part = 0/8, so that the total of i to iii is a positive number 4. Decimal number is 4/8.

  Here, as shown in the first sampling period, even if the portions i and iii are decimal numbers, a carry may occur in the sum of both. In this case, it is not possible to determine the number of pulses using only the part ii. Therefore, a counting method including such a carry is necessary. The method will be described below.

  First, in the Nth sampling, a portion corresponding to i can be calculated as (1- [iii numerical value]) using the numerical value iii in the N-1th sampling. For example, in the first sampling period in FIG. 9, the i part can be calculated as 1-3 / 8 = 5/8, and in the second sampling period, the i part = 1-7 / 8 = 1/8. In the third sampling period, the i part can be calculated as 1-4 / 8 = 4/8.

  In the N-th sampling, the total of i to iii is the sum of the count value in the (N + 1) th sampling of BASE-VCO1 plus the decimal value of the Nth iii portion, and the Nth sampling of BASE-VCO1. It can be calculated by the difference from the value obtained by adding the decimal value of the iii portion of the (N-1) th time to the count value at.

  For example, in the first sampling period in FIG. 9, from the sum of the count value “5” of BASE-VCO 1 at the start of the second sampling and the decimal value “7/8” of the part iii in the first sampling period, Subtract the total of the BASE-VCO1 count value “1” at the start of sampling and the fractional value “3/8” in part iii in the previous sampling period (not present because it was before the first sampling) (5 + 7/8) − (1 + 3/8) = 4 + 4/8.

  Similarly, in the second sampling cycle in FIG. 9, the count value “10” of BASE-VCO 1 at the start of the third sampling and the decimal value “4/8” of the portion iii in the second sampling cycle. By subtracting the total of the count value “5” of the BASE-VCO 1 at the start of the second sampling and the decimal value “7/8” of the part iii in the previous sampling period, (10 + 4/8) − (5 + 7/8) = 4 + 5/8, and in the third sampling period, the BASE-VCO1 count value “15” at the start of the fourth sampling period and the decimal value of the part iii in the third sampling period From the total of “0/8”, the count value of BASE-VCO 1 at the start of the third sampling “10” By subtracting the total of the decimal value “4/8” of the portion “iii” in the previous sampling period, it can be calculated as (15 + 0/8) − (10 + 4/8) = 4 + 4/8.

  That is, for each sampling period, a pair of the count value of BASE-VCO1 and the decimal value of the part iii is generated, and the value of the Nth pair is subtracted from the value of the N + 1th pair, so that A -D converted digital values can be generated. In addition, by calculating the difference in this way, there is also an effect of reducing a digital value conversion error with respect to the input voltage of the AD converter 20. This is because the error of the (N + 1) th pair and the error of the Nth pair are the same amount, and the error is canceled out by subtraction.

  Next, a method for calculating the numerical value iii in FIG. 9 will be described. In FIG. 9, in order to obtain the fraction iii, the phase difference between the activation time of the BASE-VCO 1 immediately before the start of sampling and the sampling start time may be measured.

  For example, the first activation point of the sampling signal Ps in FIG. 9 exists in the middle of the “1” th pulse of the BASE-VCO 1. That is, the activation time of the BASE-VCO 1 immediately before the first activation of the sampling signal Ps is the oscillation time of the “1” -th pulse, and the first activation time of the sampling signal Ps is the BASE-VCO 1 activation time. It exists at a position delayed by a period of 3/8 of the period Tbase from the oscillation time point of the “1” -th pulse. This numerical value of 3/8 corresponds to the complement of 5/8, which is the period of i.

  Since the JAW-VCO 2 starts oscillating simultaneously with the activation of the sampling signal Ps, the JAW-VCO 2 also oscillates at the first activation time of the sampling signal Ps. Referring to FIG. 8, the rise of JAW-VCO2 is delayed from the rise of BASE-VCO1 by a period of 3/8 of the period Tbase. The pulse P3 indicated by the shift amount “3” is shown in FIG. It is.

  In FIG. 8, if the rising edge of the pulse P3 indicated as the deviation amount “3” is regarded as the oscillation start time of the JAW-VCO2, the time point when the phases of the pulse signals of both VCOs coincide with each other from the pulse P3 (the deviation amount “ The number of pulses included until the time point indicated as “8” or “0”) is 5 in both BASE-VCO1 and JAW-VCO2. This value corresponds to 5/8 numerator “5” which is the period of i in the first sampling period. The numerical value of 5/8 corresponds to the complement of 3/8, which is the period iii in the previous sampling period (not present because it is before the first sampling).

  That is, N + 1 based on the number of pulses of the BASE-VCO1 or JAW-VCO2 pulse signal included between the activation time of the sampling signal Ps and the time point when the phases of the pulse signals of the BASE-VCO1 and JAW-VCO2 match. It is possible to measure a fractional part less than the period Tbase as the period i in the first sampling and the period iii in the Nth sampling.

  The part iii in the first sampling period in FIG. 9 is included between the time when the second sampling signal Ps is activated and the time when the pulse signals of the BASE-VCO1 and JAW-VCO2 coincide with each other. The number of pulses of BASE-VCO1 or JAW-VCO2 is counted, and the fractional part i in the second sampling signal Ps is obtained in the same manner as described above, and the value is subtracted from 1.

  The second activation time of the sampling signal Ps in FIG. 9 exists in the middle of the “5th” pulse of the BASE-VCO 1. That is, the second activation time of the sampling signal Ps exists at a position delayed by a period of 7/8 of the period Tbase from the oscillation time of the “5” -th pulse of the BASE-VCO 1. The numerical value of 7/8 corresponds to a 1/8 complement that is a fractional period located at the beginning of the second sampling period.

  Since the JAW-VCO 2 starts oscillating simultaneously with the activation of the sampling signal Ps, the JAW-VCO 2 also oscillates at the second activation time of the sampling signal Ps. Referring to FIG. 8, the rise of JAW-VCO2 is delayed from the rise of BASE-VCO1 by a period of 7/8 of the period Tbase. The pulse P7 indicated by the shift amount “7” is shown in FIG. It is.

  In FIG. 8, between the pulse P7 indicated as the deviation amount “7” and the time point when the phases of the pulse signals of both VCOs coincide (the time point indicated as the deviation amount “8” or “0”). The number of pulses included is one for both BASE-VCO1 and JAW-VCO2. This numerical value corresponds to 1/8 numerator as the period of i in the second sampling cycle. The numerical value 1/8 corresponds to a complement of 7/8, which is a period iii in the immediately preceding sampling period (first sampling period).

  That is, by counting the number of pulses of the BASE-VCO1 and JAW-VCO2 pulse signals included between the activation of the sampling signal Ps and the time when the phases of the BASE-VCO1 and JAW-VCO2 pulse signals coincide with each other. Based on the number of pulses, a fractional part less than the period Tbase (i period in the (N + 1) th sampling and iii period in the Nth sampling) can be measured.

  The above is generally described as follows. Since Tbase: Tjaw = A: B, Tjaw / Tbase = B / A, and thus Tjaw · A = Tbase · B = M, and the BASE-VCO1 is equal to the lap of the cycle Tjaw of the JAW-VCO2 output pulse signal. The phases of the two VCOs coincide with each other in the Bth cycle of the cycle Tbase of the output pulse signal.

  Consider a case where the oscillation start of the output pulse signal of the JAW-VCO 2 is delayed by Tdiff · X from the oscillation start of the output pulse signal of the BASE-VCO 1 immediately before that. When the output pulse signal of the JAW-VCO 2 oscillates X times with this delay, referring to FIG. 8, Tjaw · (A−X) + Tdiff · X = Tjaw · A− (Tjaw−Tdiff) · X = Tjaw · A−Tbase · X = Tbase · (B−X) Therefore, the count value of the pulse signal until the phases of the two VCOs coincide with each other is the count using the output pulse signal of the BASE-VCO 1 and the count of the pulse signal using the output pulse signal of the JAW-VCO 2 as A−. X.

  From Tbase = Tdiff · A, the maximum value Xmax of X is A-1. This is because X = A cannot be distinguished from X = 0. The greater the maximum value Xmax, the higher the resolution of A-D conversion. Further, as numerical examples of Tbase and Tjaw, for example, Tbase = 32 [nsec], Tdiff = 2 [nsec], Tjaw = 34 [nsec], Tbase = 16 [nsec], Tdiff = 2 [nsec], Tjaw = 18 [nsec] may be set. In the former case, A: B = 16: 17, and in the latter case, A: B = 8: 9.

  Next, the operation of the A / D converter 20 in FIG. 7 will be described with reference to FIG. FIG. 10 is a timing chart showing the operation of the AD converter 20 according to the present embodiment. First, the output pulse signal of the BASE-VCO 1 oscillates by free-running, and the counter 4 counts the number of oscillations. FIG. 10 shows how the count value of the counter 4 changes from “8” to “23”.

  The sampling signal Ps is input to the JAW-VCO2. The JAW-VCO 2 starts oscillating with the activation of the sampling signal Ps. The ratio A: B between the period Tbase of the oscillation output of the BASE-VCO 1 and the period Tjaw of the oscillation output of the JAW-VCO 2 is set to 8: 9 as in the case of FIG.

  The counter 4 and the first register 5, which are the upper digit calculation unit, of the BASE-VCO1 from the start of oscillation of the output pulse signal of the BASE-VCO1 to the activation point of the current sampling signal Ps are obtained every sampling cycle of the sampling signal Ps. The number of pulses of the output pulse signal is calculated as an upper digit (indicated as “upper bit” in FIG. 7). Specifically, the output of the counter 4 is given to the data input terminal D of the first register 5, the sampling signal Ps is given to the clock input terminal T of the first register 5, and the activation of the sampling signal Ps Accordingly, the first register 5 holds the output value of the counter 4 when the sampling signal Ps is activated.

  In FIG. 10, since the sampling signal Ps is activated when the count value of the counter 4 is “10”, the information of “10” is held in the first register 5. That is, the first register 5 holds the number of pulses of the counter 4 at the time of activation of the sampling signal Ps for each sampling period, and outputs it as the upper digit.

  On the other hand, the third register 10 and the second and third subtractors 11 and 12, which are the lower digit calculation unit, output the output pulses of the BASE-VCO 1 and the JAW-VCO 2 from the current activation time of the sampling signal Ps for each sampling period. Based on the number of pulses of the output pulse signal of BASE-VCO1 included in the period until the phase of the signal matches, from the last pulse in the sampling period of the output pulse signal of BASE-VCO1 to the end of the sampling period The phase difference (that is, the portion iii in FIG. 9) is calculated as the lower digit (indicated as “lower bit” in FIG. 7).

  The phase difference determination circuit 3 is a circuit that detects the coincidence of the rising phases of the output pulse signals of the BASE-VCO 1 and the JAW-VCO 2 and activates the output upon detection. The phase difference determination circuit 3 is configured by a general SR (Set-Reset) flip-flop circuit. Further, the operation control circuit 9 activates the output S1 with the activation of the sampling signal Ps, and with the detection of the phase coincidence of the output pulse signals of the BASE-VCO1 and the JAW-VCO2 in the phase difference determination circuit 3, This circuit deactivates the output S1. The operation control circuit 9 is also composed of a general SR flip-flop circuit.

  The output of the counter 4 is given to the data input terminal D of the third register 10, and the output pulse signal of BASE-VCO 1 is given to the clock input terminal T of the third register 10. Further, the output S1 from the operation control circuit 9 is given to the enable input terminal enable of the third register 10.

  The third register 10 can be operated in a one-shot manner when the signal at the enable input terminal enable is switched from Hi to Low, and the third register 10 is in accordance with the oscillation of the output pulse signal of the BASE-VCO 1. -Hold the output value of the counter 4 at the rising edge of the output pulse signal of VCO1.

  In FIG. 10, in each case (X = 0 to 7) when the oscillation start of the output pulse signal of JAW-VCO2 is delayed by Tdiff · X from the oscillation start of the output pulse signal of BASE-VCO1 immediately before that. This is shown as Delay0 to Delay7.

Assuming that X = 4, when the count value of the counter 4 is “15”, the rising phases of the output pulse signals of the BASE-VCO 1 and the JAW-VCO 2 coincide. Therefore, at this time, the output pulse signal of the BASE-VCO 1 rises, and the signal S1 at the enable input terminal enable is switched from Hi to Low, so the third register 10 holds the number of pulses “15” output from the counter 4. To do.

  The second subtractor 11, which is another component of the lower digit calculation unit, subtracts the count value “10” held in the first register 5 from the count value “15” held in the third register 10. Therefore, in this case, the output value of the second subtractor 11 is 15-10 = “5”. Note that the output value of the second subtractor 11 varies depending on each case of Delay0 to Delay7. For example, in the case of Delay0, the value held in the third register 10 is “19”, so the value is 19− Since 10 = “9” and Delay 7 is held, the value held in the third register 10 is “12”, so the value is 12−10 = “2”.

  Then, the third subtractor 12, which is another component of the low-order digit calculation unit, has a predetermined numerical value “9” (the numerical value with “9” is from “9” in the ratio A: B = 8: 9). ) Is subtracted from the value “5” calculated by the second subtractor 11. Therefore, the output value of the third subtractor 12 is 9−5 = “4” when X = 4. The output value of the third subtracter 12 becomes the phase difference (that is, the part iii in FIG. 9) from the last pulse in the sampling period of the output pulse signal of the BASE-VCO 1 to the end point of the sampling period, that is, the lower digit. .

Note that the output value of the third subtractor 12 varies depending on each case of Delay0 to Delay7. For example, in the case of Delay0, the value of the second subtractor 11 is “9”, so the value is 9-9. = “0”, and in the case of Delay7, the value of the second subtractor 11 is “2”, so that the value is 9−2 = “7”.

  The upper / lower digit combining unit 6 combines the upper digit information output from the first register 5 and the lower digit information output from the third subtractor 12 to generate a combined value. Specifically, the upper / lower digit combining unit 6 is configured by, for example, a shift register, and holds information on lower digits on the lower bit side and information on higher digits on the upper bit side. The lower bit side corresponds to the decimal value of the portion iii in FIG. 9, and the upper bit side corresponds to the count value of BASE-VCO 1 when the sampling signal Ps in FIG. 9 is activated.

  In FIG. 10, when X = 4, since the upper digit is “10” and the lower digit is “4”, the combined value in the upper and lower digit combining unit 6 is “10 + 4/8”. This synthesized value is held in the second register 7 when the sampling signal Ps is activated.

  The data input terminal D of the second register 7 is supplied with the output of the upper / lower digit combining unit 6, and the clock input terminal T of the second register 7 is supplied with the sampling signal Ps. As the sampling signal Ps is activated, The second register 7 holds the composite value “10 + 4/8” at the Nth sampling. Before the composite value “10 + 4/8” is held, the second register 7 holds information “5 + 7/8” as the composite value at the N−1th sampling. These values correspond to the respective numerical values in the second sampling cycle in FIG.

  Then, the first subtracter 8 holds the value “5 + 7/8” held in the second register 7 and the current combined value “10 + 4/8” in the previous sampling cycle (N−1th sampling cycle) from the present. The difference value “4 + 5/8” is output as a digital signal composed of upper bits and lower bits.

  The decimal number (iii) from the last pulse generation of BASE-VCO1 within the sampling cycle to the start of the next sampling cycle is calculated from the time when the cycles of BASE-VCO1 and JAW-VCO2 last match until the start of the next sampling cycle. The number of pulses of BASE-VCO1 or JAW-VCO2 may be used. The phase difference of the last pulse can be known from the number of pulses from the time when the periods of the two VCOs finally coincide. In addition, the start of the next sampling cycle does not always coincide with one of the two VCO pulses. The difference between the start of the sampling period and the VCO pulse is a quantization error.

  In the present embodiment, each value of the cycle Tbase of BASE-VCO1 and the cycle Tjaw of JAW-VCO2 is controlled by the input voltage Vin while maintaining the ratio of A: B. If the sensitivity of the two VCOs to the analog input voltage Vin is, for example, a linear expression, the sensitivity of the period difference Tdiff between the two VCOs is also a linear expression. This period difference Tdiff corresponds to the minimum resolution of the lower bits. Although the width of the cycle Tbase changes according to the analog input voltage Vin, the width of the cycle difference Tdiff also changes with the same sensitivity. Therefore, the value of Tbase / Tdiff is constant regardless of the value of the analog input voltage Vin, The resolution is constant regardless of the analog input voltage Vin.

(Modification 1 of embodiment)
The operation of the voltage controlled oscillator 24 used in the first and second embodiments has been described so as to generate a sawtooth wave that oscillates between the input VL and the voltage VH of the constant voltage source 35, as shown in FIG. Actually, the sawtooth waveform overshoots or undershoots for the switching time of the comparator 36 and the T-flip-flop 37 and the like. In general, since the time of overshoot or undershoot is not proportional to the input voltage, the voltage-frequency characteristic will deviate from the straight line accordingly. Therefore, it is desirable that the switching time is short.

  Therefore, as a first modification, an inverting circuit having a single configuration of an N-channel transistor is used for a circuit related to switching, particularly an inverting circuit of a flip-flop. FIG. 11 is a circuit diagram showing an example of the configuration of the inverting circuit. In general, a CMOS (Complementary MOS) inverter circuit using a P-channel transistor and an N-channel transistor is often used as an inverting circuit (inverter circuit). The circuit shown in FIG. 11 has a configuration in which a resistor R is used instead of the P-channel transistor of the CMOS inverter.

  When the input I is at a high potential with respect to the ground G, the transistor N is turned on, the source and drain are conducted, and the output O becomes a low potential due to a voltage drop due to the current of the resistor R. When the input I is at a low potential, the transistor N is off and does not conduct, and the output O becomes a high potential close to the power supply voltage VDD. That is, the output O is an inversion of the input I.

  According to the single configuration of the N-channel transistor, the carrier of the transistor N is only electrons, has high mobility, and fast switching operation. As a result, in any of the voltage controlled oscillators 24 in FIG. 2 and FIG. 3, the time required for switching between the two sawtooth wave generation circuits can be shortened.

(Modification 2 of embodiment)
FIG. 12 is a block diagram showing a different example of the voltage controlled oscillator 24. The voltage controlled oscillator 24 of FIG. 12 includes compensation transistors 40A and 40B in series with a capacitor between a capacitor that performs a charge / discharge operation and a discharge voltage terminal. As described above, at the peak voltage (VH) of the sawtooth wave, it overshoots only for the switching time. If the reference potential of the capacitor is increased by the voltage corresponding to the overshooting time, the charging time is shortened accordingly, so that the voltage-frequency characteristics can be compensated by offsetting the overshooting time.

  The compensating transistors 40A and 40B are set so that the switching time is just compensated. Note that the inverting circuit having a single configuration of the N-channel transistor of FIG. 11 may also be used for the circuit of FIG. In the circuit of FIG. 12, a configuration including the compensation transistors 40A and 40B is shown by taking the voltage control oscillator 24 of FIG. 2 as an example, but the compensation transistor 40A and 40B is similarly provided for the voltage control oscillator 24 of FIG. However, the same effect is obtained.

(Modification 3 of embodiment)
FIG. 13 is a block diagram showing a different example of the voltage controlled oscillator 24. FIG. 13 shows two sawtooth wave generation circuits 18A and 18B symmetrically. The two sawtooth wave generation circuits 18A and 18B are the same as the voltage controlled oscillator 24 of FIG. In the circuit of FIG. 13, the peak potential (VH) of the sawtooth is determined by the switching voltages of the transistors 41A and 41B. The inverting circuits 42 and 43 constitute an inverting circuit loop. An inverting circuit loop is used instead of the T-flip flop 37 of FIG.

  When the terminal voltages V1 and V2 of the capacitors 32A and 32B become higher than the switching voltage (VH) of the transistors 41A and 41B, the transistors 41A and 41B are turned on to bring the terminal of the inverting circuit loop to a low potential. The potential of is switched. The inverting circuits 44, 45, 46 and 47 are for driving the switches 31A and 31B and the AND circuits 39A and 39B. Both sides of the inverting circuit loop correspond to the outputs Q and notQ of the T-flip flop 37 in FIG. The configuration of the comparator and AND circuit of the circuit of FIG. 13 is the same as that of FIG.

  In the circuit of FIG. 13, the flip-flop is an inverting circuit loop, has a small number of gates, and has a fast switching operation. Therefore, the switching operation of the two sawtooth wave generation circuits 18A and 18B becomes faster. As a result, the linearity of the voltage-frequency characteristic of the voltage controlled oscillator 24 is improved. A circuit that changes the current charged in the capacitors 32A and 32B in proportion to the input voltage uses an inverting circuit loop as shown in FIG.

  Also in the circuit of FIG. 13, the use of a single N-channel transistor configuration for the inverting circuit has the effect of further speeding up the switching operation. Furthermore, compensation transistors 40A and 40B may be provided between the capacitor and the discharge voltage terminal.

  Note that the circuit configuration of the A-D conversion device 20 described in each embodiment is an example, and can be arbitrarily changed and modified. The configurations of the voltage controlled oscillation circuits 13A to 13C and the like are not limited to those shown in the embodiment, and are not limited to these.

It is a block diagram which shows the structure of the AD converter which concerns on Embodiment 1 of this invention. 2 is a block diagram illustrating an example of a configuration of a voltage controlled oscillator according to Embodiment 1. FIG. 3 is a block diagram illustrating an example of a different configuration of the voltage controlled oscillator according to the first embodiment. FIG. It is a figure which shows the difference of the sawtooth wave of two voltage control oscillators. 3 is a time chart illustrating an example of pulse signal generation according to the first embodiment. It is a block diagram which shows the structure of the AD converter which concerns on Embodiment 2 of this invention. It is a timing chart which shows an example of the pulse signal of BASE-VCO and the pulse signal of JAW-VCO. It is a timing chart which shows another example of the pulse signal of BASE-VCO and the pulse signal of JAW-VCO. It is a timing chart explaining the principle by which the VF conversion value less than the period of VCO is calculated | required. 6 is a timing chart illustrating an operation of the A / D conversion device according to the second embodiment. It is a circuit diagram which shows the structural example of an inverting circuit. It is a block diagram which shows the structural example of the voltage controlled oscillator in the case of using the transistor for compensation. It is a block diagram which shows the structural example of a voltage controlled oscillator provided with the flip-flop of an inverting circuit loop.

Explanation of symbols

1 BASE-VCO
2 JAW-VCO
3 Phase difference judgment circuit
4 counter
5 First register
6 Upper and lower girder composition
7 Second register
8 First subtractor
9 Operation control circuit
10 Third register
11 Second subtractor
12 Third subtractor
13 Sampling clock generator 14, 15 Resistor
16 Grounding
17 voltage-current amplifier 18A, 18B sawtooth wave generation circuit
19 Switch circuit
20 AD converter
21 Input terminal
22 Output terminal
23 Sampling clock generator
24 Voltage controlled oscillator
25 counter
26 registers
27 Input terminal
28 Output terminal
29 Current source
30 Pulse generator 31A, 31B Switch (charging)
32A, 32B Capacitor 33A, 33B Switch (discharge)
34 Grounding
35 Constant voltage source
36 Comparator
37 T-flip-flop 38A, 38B Comparator 39A, 39B AND circuit 40A, 40B Compensating transistor 41A, 41B Transistor 42, 43 Inverting circuit

Claims (6)

Two equivalent sawtooth generators;
A switch circuit for alternately switching the two sawtooth wave generation circuits;
Having a voltage controlled oscillator comprising:
An A-D conversion device comprising a voltage-frequency conversion circuit. The voltage-frequency conversion circuit includes:
A first voltage-controlled oscillator that outputs a first periodic signal that oscillates in a first period;
A second voltage-controlled oscillator that outputs a second periodic signal that oscillates in a second period that is different from the first period and that maintains a constant ratio to the first period;
With
The first voltage controlled oscillator starts oscillation of the first periodic signal by self-running,
The second voltage controlled oscillator starts oscillating the second periodic signal triggered by activation of a sampling signal indicating a sampling period of A-D conversion,
Upper bit calculation means for calculating upper bits of a digital signal corresponding to an analog signal as an input based on the wave number of the first periodic signal included in the sampling period;
Based on the wave number of the first or second periodic signal included between the activation time of the sampling signal and the time when the phases of the first and second periodic signals match, the lower bits of the digital signal Low-order bit calculation means for calculating
The AD converter according to claim 1, comprising:   3. The A / D converter according to claim 2, wherein the input voltages of the first and second voltage controlled oscillators are each given by the same voltage divided by resistance.   2. The voltage control type oscillator having the two sawtooth wave generation circuits, wherein the switch circuit is constituted by a flip-flop that uses an inverting circuit having a single configuration of an N-channel transistor. D converter.   In the voltage controlled oscillator having the two sawtooth wave generation circuits, compensation is performed in series with the capacitor between a capacitor that performs charge / discharge operation according to a result of comparison with the reference voltage of the sawtooth voltage and a discharge voltage terminal. The AD converter according to claim 1, further comprising:   2. The A / D converter according to claim 1, wherein in the voltage-controlled oscillator having the two sawtooth wave generation circuits, the switch circuit includes a flip-flop of an inverting circuit loop.

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