JPS5838031A - Circulating type analog-to-digital converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter with high accuracy and faster converting speed, by constutiting the titled converter with an analog signal switching circuit, a current balancing type A/D conversion circuit, a sample hold circuit and a digital value synthesis circuit. CONSTITUTION:When a conversion start signal is applied to a conversion start signal input terminal 27, a control circuit 28 transmits a signal to a current balancing type A/D conversion circuit 23, a sample hold circuit 24, and a digital value synthesis circuit 25 to let the circuit 22 select an analog input signal from a terminal 21 and this sitnal is A/D-converted at the circuit 23. After a prescribed time, this conversion is finished and an output signal at the end of conversion of an integrator in the circuit 23 is picked up and held in the circuit 24. The circuit 22 selects the output signal of the circuit 24, this signal is A/D- converted at the circuit 23, an output signal of the integrator at the end of conversion after a prescribed time is picked up and held at the circuit 24 and this signal is again A/D-converted at the circuit 23. Digital values obtained from the operations above for a required number of times are synthesized at the circuit 25 and outputted from a terminal 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circular analog-to-digital converter with means for combining a plurality of digital values.

In recent years, with the spread of digital devices such as computers, the need to digitize physical quantities such as voltage, current, and temperature has rapidly increased. The technology to digitize these analog quantities has been around for a long time, and the methods can be roughly divided into 3 types:
It can be classified into These are called an integral method, a feedback comparison method, and a non-feedback comparison method.

Of these methods, the present invention basically belongs to the integral method, but it also includes elements of the feedback comparison method and belongs to a new method. Regarding analog-to-digital converters. Conventionally, the integral method has been widely used for high-precision conversion.

This is because highly accurate analog-to-digital conversion is possible. However, with the conventional integration method, the number of conversions is 211.
Performing 1 analog-to-digital conversion usually requires about 1 degree of time, and if the number of conversions is 221, the conversion time of about 10 seconds is required. Certain fields, e.g.
In fields such as chemistry, medicine, and needle engineering, there is a deep-rooted desire to complete conversion in a shorter time. However, it is difficult to meet these demands using conventional analog-to-digital conversion technology.

SUMMARY OF THE INVENTION In response to these demands, it is an object of the present invention to provide a novel analog-to-digital converter that is highly accurate and has a significantly shorter conversion time than conventional integrators.

FIG. 1 is a diagram illustrating the operating principle of a charge-balanced analog-to-digital converter, which is often used as a high-precision analog-to-digital converter.

It will be done. This analog input signal is applied to the input of an integrator 4 through a resistor 2 and an input switch 3. A reference current is applied to the (c) input of this integrator 4 from a reference power supply 9 through a resistor 8 and a switch 7. The output of the integrator 4 is applied to one input of a voltage comparator 11, and a constant voltage from a comparison voltage source 10 is applied to the other input of the voltage comparator 11. The output of voltage comparator 11 is applied to the D input of a D-type clamp flop 12, and the Q output of this flip flop 12 is applied to one input of AND gate 13. The output of the AND gate 13 is output to the output terminal 14 and controls the switch 7. CK large input AND gate 13 of D-type clamp flop 12
A clock signal of a constant frequency is applied to the other input from the clock input terminal 15.

The operation shown in FIG. 1 will be explained with reference to FIG. 2. Before starting analog/digital conversion, input switch 3 is OFF.
In the FF state, the integrator reset switch 6 is in the ON state. In this state, the integrator output signal is zero volts,
Since a constant negative voltage is applied to the (c) input of the voltage comparator 11, the output of the voltage comparator 11 is at a high level. Since a clock signal is continuously applied to the clock input terminal 15, the Q of the D-type clamp flop 12 is
The output will be at a high level. As a result, the output of the AND gate 13 becomes low level, and the switch 7 continues to be in the OFF state.

As soon as the conversion is started (the starting point is indicated by T in FIG. 2), the integrator reset switch 6 is turned OFF and the input switch 3 is turned ON.

Therefore, the analog input signal VX is integrated by the integrator 4. As time passes, the output voltage of the integrator 4 continues to drop (here, the analog input signal is of positive polarity), and eventually becomes lower than the voltage level of the comparison voltage source 10 (shown as Vc in Fig. 2). . In this state, the output of the voltage comparator 11 is at a low level, and at the rising edge of the cyclic signal, the Q output of the D-type clamp flop 1-2 becomes a low level.

Next, when the clock signal becomes low level, the output of the AND gate 13 becomes high level and the switch 7 is turned on. This state lasts as long as the clock signal is low. When the switch 7 is in the ON state, the resistor 8 is connected to the reference voltage source 9.
A current having a polarity opposite to that of the analog input signal (in this case, fish type) flows into the input of the integrator 40 through the integrator 40, thereby increasing the output of the integrator 4. (This section is shown as td in Figure 2)
As a result, at the rising edge of the next clock, the output of the integrator 4 is higher than the comparison voltage Vc, the D input of the D-type clamp flop 12 changes to a high level, and therefore the Q output also changes to a high level. In this state, even if the clock signal becomes low level next time, the output of the AND gate 13 continues to be low level. That is, the switch 7 is not turned on and the output of the integrator continues to fall. (This interval is shown as tc in FIG. 4) At the next rising edge of the clock signal, the output of the integrator 4 is lower than the comparison voltage Vc, so the D-type clamp prop 12 (D output Then, while the clock signal is at a low level, the switch 7 is turned on. As a result of this operation, the amount of charge due to the analog input signal input to the integrator 4 and the charge due to the reference power source are The amount remains in equilibrium. (From here on, this analog-to-digital conversion method is called the charge balance method.) After continuing the above operation for a certain period of time (indicated by T in Figure 2),
Turn input switch 3 and switch 7 off.

(This positive amount is shown as th in FIG. 2) Next, the integrator reset switch 6 is turned on, and this conversion operation is completed. The number of times the switch 7 is turned on during this conversion operation is the output digital value.

Now, in order to double the number of conversions in a charge-balanced analog-to-digital converter, it is necessary to double the clock signal frequency or double the conversion time. If the clock signal frequency is doubled, the conversion nonlinearity error will be doubled if the circuit configuration is the same. However, it is common sense that if the number of conversions is doubled, the conversion nonlinearity error must be halved. Therefore, if the circuit configuration is the same, doubling the number of conversions will halve the clock signal frequency and the conversion time will be 4
It will be doubled. l) The conversion time of this type of analog-to-digital converter with a large number of conversions becomes unbearably long. To solve this problem, we made improvements to the circuit configuration, especially the widening of the integrator's bandwidth and the faster switching speed of the switch.

Even if maximum efforts are made to improve the circuit configuration, it is difficult to increase the clock signal frequency higher than 200 kilohertz in a converter with 218 conversions at the current level of technology. If the clock signal frequency is −1200 kHz, the conversion time for this 21″ converter is about 1.
It will be 31 seconds. Other integral type analog to digital converters...For example, single sweep type analog to digital converters, double integral type analog to digital converters...
Although there are some differences, broadly speaking, the same can be said of the above-mentioned charge-balanced analog-to-digital converter.

However, despite the technical difficulties, there are strong demands from various fields to increase the number of conversions and shorten the conversion time. Among them, the one that was particularly troublesome was that the number of conversions was 221 (approximately 2×10 6 ) and the conversion time was 2 milliseconds.

In order to realize an analog-to-digital converter that satisfies this performance using the charge-balanced type described above, the clock signal frequency must be 1.
000 megahertz. It is easy to understand that this is not possible. It is an object of the present invention to make it possible to realize an analog-to-digital converter with high precision and short conversion time, which is completely unrealizable with the conventional technology.

In order to achieve this object, in the present invention, an analog-to-digital converter is constituted by an analog signal switching circuit, a charge-balanced analog-to-digital conversion circuit, a sample/halt circuit, and a digital value synthesis circuit. The atero two-power signal to be converted into a digital value is connected to one input of the analog switching circuit, and the output of the analog signal switching circuit is connected to the input of the charge balance type analog-to-digital conversion circuit.

The output of the integrator included in this conversion circuit is connected to the input of a sample and hold circuit, and the output of this sample and hold circuit is connected to the other input of the analog signal switching circuit.

Further, the digital output of the charge-balanced analog-to-digital conversion circuit is connected to the input of a digital value synthesis circuit, and the output of this digital value synthesis circuit is connected to a digital output terminal.

In this state, the analog input signal is first converted into a digital value by the analog-to-digital conversion circuit, and the output signal of the integrator of this conversion circuit at the end of the conversion operation is extracted and held by the sample-and-hold circuit. The output signal of this sample-and-hold circuit is input to the analog-to-digital conversion circuit through an analog signal switching circuit, and is converted into a digital value. Furthermore, if necessary, the output signal of the integrator of this conversion circuit at the end of the second conversion operation is extracted and held by a sample and hold circuit. The output signal of this sample-and-hold circuit is input to the analog-to-digital conversion circuit through an analog signal switching circuit, and is converted into a digital value. Thereafter, the same operation is repeated as many times as necessary. In the process of this repetition, each conversion operation divides and converts a part of the final required digital output.

That is, the first conversion operation converts the top part of the digital output, the second conversion operation converts the next highest part of the digital output, and the final conversion operation converts the lowest part of the digital output. . The digital values obtained in each of these conversion operations are multiplied by necessary weights in a digital value synthesis circuit, and then electrically applied to form the final digital output.

Now, the principle of this operation will be explained with reference to FIG.

Output voltage v1 of the integrator at the end of conversion time TI in Fig. 2
represents the amount of residual charge remaining without being digitized in the analog input signal input to the integrator.

This vl corresponds to the remainder in division in mathematics. In division, if you multiply the remainder part by the basic value (10 times in the case of decimal data) and continue the division, you can obtain a lower division result. - If you perform digital conversion, you will obtain a lower-order digital value.If you expand the output voltage of the integrator by an appropriate multiple and then perform analog-to-digital conversion again, you will obtain an even lower-order digital value. The fact that this operation can be repeated an arbitrary number of times can be easily understood from the previous example of division in mathematics. After all conversion operations are completed, the digital values obtained in each conversion operation are weighted and added together to obtain the desired digital output.

To expand the above vl by an appropriate multiple, Vl
can be amplified using an operational amplifier. Furthermore, it is well known that the same effect can be obtained by simply reducing the resistance value of resistor 2 in FIG. 1 without using an operational amplifier.

Now, let us compare the conversion times of the conventional charge balance analog-to-digital converter and the analog-to-digital converter according to the present invention. Now, assuming that the number of conversions is N1, the frequency of the clock signal is FC, and the analog-to-digital converter of the present invention performs M conversion operations, the conversion time is approximately as follows.

Conversion time in the conventional method TA TA=-C seconds] ・・・・・・・・・U) FC Conversion time in the method of the present invention TB ↓ Which formula is the high-performance analog-to-digital conversion described above? Let's try applying numerical examples required for the vessel. With this converter, the number of conversions is 2! 1, the clock signal frequency is 200 kHz, and the number of conversion operations in the converter of the present invention is 3. Conversion time according to the conventional method ゛i''A = 10.486 seconds Conversion time according to the method according to the present invention TB = 0.0019 Second It can be seen from these values that if the present invention is used, the conversion time can be shortened to 1/5ooo or less without impairing conversion accuracy, and the above-mentioned object of the present invention can be achieved.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 3, 21 is an analog signal input terminal, 22 is an analog signal switching circuit, 23 is a charge-balanced analog-to-digital conversion circuit, 24 is a sample and hold circuit, and 2
5 is a digital value synthesis circuit, 26 is a digital output terminal, 27 is a conversion start signal input terminal, and 28 is a control circuit.

The operation of this embodiment will be explained with reference to FIG. When the conversion start signal is applied to the conversion start signal input terminal 27, the control circuit 28 switches between the analog signal switching circuit 22, the analog/digital conversion circuit 23, and the sample/hold circuit 2.
4. Send a signal to each of the digital value synthesis circuits 25 to cause them to perform the following operations.

First, the analog signal switching circuit 22 selects an analog input signal, and then the analog-to-digital conversion circuit 23 starts conversion (indicated as To in FIG. 4) and finishes this conversion after a certain period of time [in FIG. The output signal of the integrator (not shown) included in the analog-to-digital conversion circuit 23 at the end of customer exchange is extracted and held in the sample-and-hold circuit 24. Thereafter, the analog signal switching circuit 22 is Reconfigure sample/hold circuit 2
Select output signal 4. When the analog-to-digital conversion circuit 23 starts conversion again, the output signal of the sample and hold circuit is digitized. The conversion is completed after a certain period of time (shown as T2 in FIG. 4), and the output signal of the integrator (not shown) included in the analog-to-digital conversion circuit 23 at the time of completion of the conversion is transferred to the pull/hold circuit. Extract and hold at 24. Thereafter, when the analog-to-digital conversion circuit 23 starts conversion again, the output signal of the sample-and-hold circuit is digitized. The conversion is terminated after a certain period of time (indicated by T in FIG. 4).

Next, the digital values obtained by the three analog-to-digital conversion operations described above are synthesized by the digital value synthesis circuit 25, and the digital values obtained here are transferred to the digital output terminal 2.
Output from 6. 2nd time. The analog-to-digital conversion of the eye can be started at any time after T3 in FIG. 4 (indicated as Tto in FIG. 4).
The conversion time of this analog-to-digital converter (Ta
It shows that it can be defined as "o)".

To further aid understanding, embodiments will now be described with reference to detailed drawings. In FIG. 5, 21 is an analog signal input terminal, 22 is an analog signal switching circuit, and 2
3 is a charge-balanced analog-to-digital conversion circuit, 24
25 is a sample and hold circuit, 25 is a digital value synthesis circuit, and 26 is a digital output terminal, which have the same functions as those having the same reference numerals in FIG. 31 is an input switch control signal connection point, 32 is a circulation switch control signal connection point, 33 is an integrator reset signal connection point, 34 is a sample/hold signal connection point, 35 is a counter 1 gate signal connection point, and 36 is a connection point for the counter 1 gate signal. Counter 2 gate signal connection point, 37 is counter 3
gate signal connection point, 38 is a counter reset signal connection point,
Reference numeral 39 indicates clock signal connection points, and each of these connection points is connected to each connection point with the same reference numeral in FIG.

In FIG. 5, 41 is an input switch, 42 is a circulation switch, 43 is a resistor, 44 is an integrator, 45 is an integrating capacitor, 46 is an integrator reset switch, 47 is a reference current switch, 48 is a resistor, 49 5 is a reference power source, 50 is a comparator pressure source, 51 is a voltage comparator, 52 is a D-type flip-flop, 53 is an AND gate, 54 is an OFt gate, 5
5 and 56 are resistors, 57 is a variable resistor, 58 is an amplifier, 59 is a sampling switch, 60 is a capacitor, 61 is a buffer amplifier, 62, 63 and 64 are AND gates, 65 is a counter 1. 66 is a counter Counter 2.67 and counters 3.68 and 69 are OR gates.

The operation of the embodiment shown in FIG. 5 will be explained with reference to the operation diagram shown in FIG.

Before starting conversion, integrator reset switch 46 is ON.
The input switch 41 and circulation switch 42 are both OFF, and the sampling switch 59 is ON (
sampling state), the counter 1 gate signal applied to connection point 35, the counter 2 gate signal applied to connection point 365, and the counter 3 gate signal applied to connection point 37 are all at low levels (62, 63, 64 AN/D gates are in the 0FF-state).

Here, when the conversion is started (shown as ts in FIG. 7), the integrator reset switch 46 is in the OFF state, the input switch 41 is in the ON state, and the gate 62 of counter 1 is in the ON state.
state. As a result, a first conversion operation is started, and by an operation similar to that described in FIGS. 1 and 2,
The analog voltage applied to the analog signal input terminal 21 is converted to digital. The converted digital data is obtained as a pulse train at the output of AND gate 53.

This pulse train continues while the first conversion operation is being carried out (
(from ts to tl in FIG. 7), AND gate 62
, passes through an OR gate 68 and is counted by a counter 65.

At the end of the first conversion operation (shown as tl in Figure 7)
'The digital value corresponding to the analog voltage applied to the analog signal input terminal 21 is the small force (A) of the counter 65.
, B...H).

@Figure 7 1. At this point, the input switch 41 is turned OFF, and the counter l gate signal applied to 35 is applied to the reference current switch 4 through the OFL gate 54 and the AND gate 53.
Turn 7 off as well. Therefore, the integrator 4 at the end of the conversion
The output voltage of 4 remains unchanged and is held in the integrator. This voltage is amplified and polarized by an amplifier 58, and is 11 in FIG.
Between time points 12 and 12, the sampling switch 59 is turned OFF.
Since the voltage becomes N, it is stored in the capacitor 6o, and is held in the capacitor 60 even after the sampling switch 59 is turned off at time t2. The output voltage of the integrator at the end of the first conversion held in the capacitor 60 passes through the buffer amplifier 61 and the circulation switch 42 while the second conversion operation is being performed (from t3 to t14 in Figure 5g7). ) is applied to the charge-balanced analog-to-digital conversion circuit 23 as an analog signal to be digitally converted.

This conversion circuit 23 turns on the integrator reset switch 46 (between 12 and t in FIG. 7) before starting the second conversion operation, so that the first Discharge the remaining charge from the conversion operation and reset the integrator to its initial state.

A second conversion operation is performed between t and t4 shown in FIG.

During this conversion operation, the pulse train that appears at the output of the AND gate 53 passes through the AND gate 63 and the OR gate 69.
It is input to a counter 66, where the number of pulses is counted. When the number of pulses is greater than 2' (64), the counter 66
A carry signal is generated at the output terminal F, and this carry signal passes through an OR gate 68 and is counted by a counter 67. The end point of the second conversion operation (shown as t4 in Figure 7)
Then, the circulation switch 42 is turned off and the sampling switch 59 is turned on.

The operation from 14 to t in FIG. 7 is the same as the operation from t to t2 in the same figure as described above.
The output voltage of the integrator 44 at the end of the conversion operation is stored in the capacitor 60 and held while the next conversion operation is performed. t in FIG.

The operation from 12 to t6 in the same figure explained earlier
, the same operation as before is performed, and the integrating capacitor 45
The remaining charge is discharged and the integrator is reset to its initial state.

At t6, the integrator reset switch 46td is turned off, the circulation switch 42 is turned on again, and the third conversion operation is started. While the third conversion operation is being performed (from t6 to t@ in Figure 7), AND gate 5
The pulse train appearing at the output of 3 passes through an AND gate 64 and is input to a counter 67, where the number of pulses is counted. When the number of pulses is greater than 26 (64), the counter 67
A carry signal is generated at the output terminal F, and this carry signal passes through an OR gate 68 and is counted by a counter 66.

At time tII in FIG. 7, the series of analog-to-digital conversion operations is completed, and each circuit is reset to its initial state (the state before the start of the first conversion operation, that is, the state before t@ in FIG. 7), and the conversion is in progress. The signal (obtained from the converting signal output terminal 4o in Figure 6) is at a low level and informs an external device (e.g. a computer) that the analog-to-digital conversion has been completed. Upon completion, the digital output data is read from the digital output terminal 26.

Next, the operation shown in FIG. 6 will be explained. In FIG. 6, 27 is a conversion start signal input terminal, 28 is a control circuit, 31 is an input switch control signal connection point, 32 is a circulation switch control signal connection point, 33 is an integrator reset signal connection point, and 34 is a sample hold. Signal connection points, 35 is the counter 1 gate signal connection point, 36 is the counter 2 gate signal connection point, 37 is the counter 3 gate signal connection point, 38 is the counter reset signal liquid point d, 39 is a clock signal connection point, and each connection point 31 to 39 is connected to each connection point with the same reference numeral in FIG. 5 described above. Further, 40 is a signal output terminal during conversion. In FIG. 6, 80 is an oscillator, 81 is a timer circuit,
82 is an initial state setting circuit, 83 is an OR gate, 84 is D
type flip-flop, 85 is a triggered monostable circuit, 8
6,87°88.89,90,91,92.93 and 94 are OR gates, 95,96,97,98,99°1
00 and 101 are flip-flops.

The operation of the embodiment shown in FIG. 6 will be explained with reference to the operation diagram shown in FIG. 7.

In FIG. 6, when the power is turned on, the initial state setting circuit 82 operates to reset the flip-flop 84. When the flip-flop 84 is reset, the output Q of the flip-flop 84 is at a low level υ, the timer circuit 81 is also reset, and all seven flip-flops 95 to 101 are also reset. In this state, the timer circuit does not operate, and the signals at the connection points 31 to 38 are held at the level before (to the left) the time point shown as t- in FIG. 27
continues until a conversion start signal is applied.

Now, when a conversion start signal is applied to this input terminal 27, flip-flop 84 is inverted and its output Q becomes high level. The timer circuit 81 now starts operating, and after the set time elapses, each output terminal "e tI'm" t
Negative pulses are generated sequentially at *"R,"4e"H*ta*t (this situation is shown as the timer circuit output signal in FIG. 7).Furthermore, the inversion of the flip-flop 84 is performed by the flip-flop 95. ,96,97,98,99,
100 and 101 are released from the reset state, and each of these flip-flops is enabled to operate according to the output signal from the timer circuit 81, and the triggered monostable circuit 85 is triggered to generate an extremely short time width. 9) (Generate a pulse and reset the counters 65, 66, and 67 in FIG. 5.

When the timer circuit 81 starts operating, first the output t'a
A negative pulse is generated at the flip-flop 95.97
, 98.99 are set. As a result, the input switch control signal 31, the counter 1 gate signal 36, and the gate signal 36 of the counter 1 change to a high level, and the integrator reset signal 33 and the sample/hold signal 34 change to a low level. This situation can be seen in the seventh
This is shown as a signal change at 18 in the figure. Now,
This condition continues until a negative pulse occurs at the output t1 of the timer circuit, when the flip-flop 95°98.99 is reset and the input switch control signal 31 , 35 go low, and the sample-and-hold signal at 34 goes high. This situation is shown as a signal change at tl in FIG. Similarly, each flip-flop is set or reset each time a negative pulse is generated at each output of the timer circuit, and from 31 to 3
The signals at each connection point up to 7 change as shown in FIG.

Now, when a negative pulse occurs in the output t of the timer circuit 81, the D-type flip-flop 84 is reset,
The signal at the converting signal output terminal 40 changes to low level, notifying the external device of the end of conversion, and the timer circuit 81,
Flip flop 95.96, 97.9g, 99.1
00 and 101 are also reset and return to the initial state. The series of operations of the control circuit 28 is thus completed, and the initial state continues until the conversion start signal is applied to the conversion start signal input terminal 27 again.

Due to the operations described above, in the embodiments shown in FIGS. , conversion time 2.64 mi! J seconds high precision, high speed analog
A digital converter is obtained. The breakdown of the conversion time in this example is that the clock frequency is 200 kilohertz, and the first
1.28 milliseconds for the conversion operation (between ta and tl in Figure 7), 0.64 milliseconds for the second conversion operation (between t and t4), and 0.64 milliseconds for the third conversion operation (between t0 and t4 in Figure 7). to t-) to 0.6
4 mIJ seconds, operation 1 for integrator reset and sampling
Shiloh. Assign 0.02 milliseconds.

An analog model with the same number of conversions and nonlinear errors as this example.
If the digital converter were implemented using conventional technology, the conversion time would be approximately 5.24 seconds. This is 1985 times longer than the time required by the analog-to-digital converter according to this embodiment.

In the above embodiment, the analog input signal is converted into a digital value by three conversion operations, but this is not limited to three conversion operations. An arbitrary number of times greater than or equal to two can be selected in consideration of the required number of conversions, required conversion time, etc.

In the embodiments shown in Figures 5 and 6, the analog signal is converted into a digital value by converting the upper 8 bits in the first conversion operation, the middle 6 bits in the second conversion operation, and the lower 6 bits in the third conversion operation. However, this combination is not limited to this. Any combination can be selected by considering the number of conversions required.

In addition, in the embodiment shown in FIG. 5, the digital value synthesis was configured by combining three sets of counters, but if this analog-to-digital converter is conveniently used in computer application equipment,
It is also possible to have a computer perform this part of the function. Similarly, the functions of the control circuit of the embodiment shown in FIG. 6 can be performed by a computer, but this does not change the essence of the present invention.

As described above, according to the present invention, the conversion time can be reduced to several tenths with a relatively simple circuit configuration. That is, the present invention makes it possible to realize a high-precision, high-speed analog-to-digital converter that was impossible to achieve with the conventional technology, and can greatly contribute to the advancement of technology in fields such as chemistry, medicine, and measurement.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the operating principle of a charge-balanced analog-to-digital converter, Figure 2 is an operating waveform diagram of the circuit in Figure 1, and Figure 3
The figure is an embodiment of the present invention, FIG. 4 is an explanatory diagram of the operation of the embodiment of FIG. 3, FIGS. 5 and 6 are detailed diagrams of the embodiment of the present invention, and FIG. FIG. 6 is an explanatory diagram of the operation of FIG. 6; 21... Analog signal input terminal, 22... Analog signal switching circuit, 23... Charge balanced analog-to-digital conversion circuit, 24... Sample/hold circuit, 2
5... Digital value synthesis circuit, 26... Digital output terminal, 27... Conversion start signal input terminal, 28...
- Control circuit, 41... Input switch, 42... Circulation switch, 44... Integrator, 49... Reference power supply, 5
o... Comparison voltage source, 51... Voltage comparator, 52...
・D-type frit No. l Zuka 2 Ro no.

Claims (1)

[Claims] 1. Select a charge-balanced analog-to-digital conversion means, a sample-and-hold means for extracting and holding the output signal of the integrator included in this conversion means, and an output signal of this sample-and-hold means and an analog input signal. In a circulating analog-to-digital converter, the circuit includes an analog signal switching means for inputting to the converting means, and a digital value synthesizing means for synthesizing a plurality of digital values obtained from the converting means. The switching means selects an analog input signal, the converting means converts this analog signal into a digital value, and the second
As a conversion operation, the output signal of the integrator at the end of the previous conversion operation is extracted and held by the sample and hold means, and then the analog signal switching means is switched to send the output signal of the sample and hold means to the conversion means. Here, it is converted into a digital value, and if necessary, a second
A circulation type characterized in that an operation similar to the conversion operation is repeatedly performed, and the digital values obtained in each of the conversion operations are synthesized by the digital value synthesis means to obtain a digital output corresponding to the analog input signal. Analog to digital converter.